Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is in response to the amendment filed on 12/22/2025.
Claims 1-20 are pending.
Examiner’s Note
Please note that Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirely as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Claim Rejections – 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter.
1. A method comprising:
converting register transfer level (RTL) code for a reference specification into a specification dataflow graph;
building an equivalence graph (e-graph) of the reference specification based on the specification dataflow graph;
applying an equivalence preserving rewrite to the e-graph of the reference specification;
inserting an e-graph node for an expression in a design implementation into the e-graph of the reference specification; and
extracting an expression having a correction to a defect within the design implementation based on the equivalence preserving rewrite to the e-graph of the reference specification.
Claim 1, this claim is within at least one of the four categories of patent eligible subject matter as it is directing to a method claim under Step 1.
Regarding claim 1, the limitations “converting register transfer level (RTL) code for a reference specification into a specification dataflow graph” and “building an equivalence graph (e-graph) of the reference specification based on the specification dataflow graph” as drafted, are functions that, under its broadest reasonable interpretation, recite the abstract idea of a mental process. For example, a person is capable converting RTL code to create an e-graph of data. In same manner, a person is capable of converting RTL code with the aid of pen and paper from using the reference specification of data in creating the RTL design. Therefore, these limitations encompass a human mind carrying out the function through observation, evaluation judgment and /or opinion, or even with the aid of pen and paper. Thus, these limitations recite and falls within the “Mental Processes” grouping of abstract ideas under Prong 1.
Under Prong 2, the additional elements “applying an equivalence preserving rewrite to the e-graph of the reference specification” is recited at a high-level of generality such that it amounts no more than mere instructions for executing/applying computer model to rewrite the specification which merely using generic computing equipment to execute/run the software tools to perform the abstract idea. See MPEP 2106.05(f). For the additional elements “inserting an e-graph node for an expression in a design implementation into the e-graph of the reference specification; and extracting an expression having a correction to a defect within the design implementation based on the equivalence preserving rewrite to the e-graph of the reference specification” do nothing more than to add insignificant extra solution activity to the judicial exception of merely storing/gathering data for automation. See MPEP § 2106.05(h).
Under Step 2B, the claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “applying an equivalence preserving rewrite to the e-graph of the reference specification” amount to no more than mere instructions, or generic computer and/or computer components to carry out the exception, thus, cannot amount to an inventive concept. See MPEP 2105.06(f). For the additional elements “inserting an e-graph node for an expression in a design implementation into the e-graph of the reference specification; and extracting an expression having a correction to a defect within the design implementation based on the equivalence preserving rewrite to the e-graph of the reference specification” the courts have recognized storing and retrieving information in memory and performing repetitive calculation as a well‐understood, routine, and conventional functions in a merely generic manner (e.g., at a high level of generality) or an insignificant extra-solution activity. See MPEP 2106.05(d).II.iv and 2106.05(d).II.ii. Accordingly, the claims are not patent eligible under 35 USC 101.
2. The method of claim 1, further comprising:
converting RTL code for the design implementation to an implementation dataflow graph; and generating the e-graph node for the expression in the design implementation based on the implementation dataflow graph.
Regarding claim 2, the limitations converting RTL code for the design implementation to an implementation dataflow graph; and generating the e-graph node for the expression in the design implementation based on the implementation dataflow graph is an additional mental process under prong 1.
3. The method of claim 2, wherein the implementation dataflow graph and the specification dataflow graph each include first nodes to represent operators and second nodes to represent operands of the operators.
Regarding claim 3, the limitations the implementation dataflow graph and the specification dataflow graph each include first nodes to represent operators and second nodes to represent operands of the operators is an additional insignificant extra solution activity under prong 2.
4. The method of claim 3, wherein the implementation dataflow graph and the specification dataflow graph each include edges between the first nodes and the second nodes.
Regarding claim 4, the limitations the implementation dataflow graph and the specification dataflow graph each include edges between the first nodes and the second nodes is an additional insignificant extra solution activity under prong 2.
5. The method of claim 4, wherein edges between the first nodes and the second nodes are associated with a bitwidth of a datapath defined in the RTL between the operands and the operators.
Regarding claim 5, the limitations edges between the first nodes and the second nodes are associated with a bitwidth of a datapath defined in the RTL between the operands and the operators is an additional insignificant extra solution activity under prong 2.
6. The method of claim 5, further comprising conditionally applying the equivalence preserving rewrite based on the bitwidth of the datapath associated with the equivalence preserving rewrite.
Regarding claim 6, the limitations comprising conditionally applying the equivalence preserving rewrite based on the bitwidth of the datapath associated with the equivalence preserving rewrite is an additional insignificant extra solution activity under prong 2.
7. The method of claim 1, further comprising: building a set of equivalent specifications via equivalence preserving rewrites to the e-graph of the reference specification; evaluating equivalent specifications in the set of equivalent specifications via a syntactic difference cost model; and selecting an equivalent specification having a lowest syntactic difference cost according to the syntactic difference cost model.
Regarding claim 7, the limitations building a set of equivalent specifications via equivalence preserving rewrites to the e-graph of the reference specification is an additional mental process under prong 1. Under prong 2, the evaluating equivalent specifications in the set of equivalent specifications via a syntactic difference cost model; and selecting an equivalent specification having a lowest syntactic difference cost according to the syntactic difference cost model limitations are additional elements that recite insignificant extra solution activity which do not amount to a practical application, nor amount to significantly more under step 2B as explained above.
8. The method of claim 7, further comprising extracting the expression having the correction to the defect within the design implementation from the equivalent specification having the lowest syntactic difference cost.
Regarding claim 8, the limitations comprising extracting the expression having the correction to the defect within the design implementation from the equivalent specification having the lowest syntactic difference cost is an additional insignificant extra solution activity under prong 2.
9. The method of claim 8, further comprising: extracting expressions from the equivalent specification having the lowest syntactic difference cost to implement a reference specification that is syntactically near the design implementation; and converting an extracted expressions into RTL code.
Regarding claim 9, the limitations, Under prong 2, the extracting expressions from the equivalent specification having the lowest syntactic difference cost to implement a reference specification that is syntactically near the design implementation limitations are additional elements that recite insignificant extra solution activity which do not amount to a practical application, nor amount to significantly more under step 2B as explained above. Under prong 1, converting an extracted expressions into RTL code is an additional mental process.
10. The method of claim 9, further comprising synthesizing the RTL code for the extracted expressions.
Regarding claim 6, the limitations comprising synthesizing the RTL code for the extracted expressions is an additional insignificant extra solution activity under prong 2.
11. A non-transitory machine-readable medium having instructions stored thereon, which when executed, cause one or more processors perform operations comprising:
converting register transfer level (RTL) code for a reference specification into a specification dataflow graph;
building a set of equivalent specifications based on equivalence preserving rewrites to a specification e-graph generated based on the specification dataflow graph;
evaluating equivalent specifications within the set of equivalent specifications via a syntactic difference cost model to determine a syntactic difference metric between the equivalent specifications and a design implementation;
selecting an equivalent specification with a lowest syntactic difference cost as a nearest specification to the design implementation; and
converting the nearest specification to RTL.
Claim 11, this claim is within at least one of the four categories of patent eligible subject matter as it is directing to a medium claim under Step 1.
Regarding claim 11, the limitations “converting register transfer level (RTL) code for a reference specification into a specification dataflow graph; building a set of equivalent specifications based on equivalence preserving rewrites to a specification e-graph generated based on the specification dataflow graph” and “converting the nearest specification to RTL” as drafted, are functions that, under its broadest reasonable interpretation, recite the abstract idea of a mental process. For example, a person is capable converting RTL code to create an e-graph of data. In same manner, a person is capable of converting RTL code with the aid of pen and paper from using the reference specification of data in creating the RTL design. Therefore, these limitations encompass a human mind carrying out the function through observation, evaluation judgment and /or opinion, or even with the aid of pen and paper. Thus, these limitations recite and falls within the “Mental Processes” grouping of abstract ideas under Prong 1.
Under Prong 2, the additional elements “non-transitory machine-readable medium having instructions stored thereon, which when executed, cause one or more processors” is recited at a high-level of generality such that it amounts no more than mere instructions for executing/applying computer model to rewrite the specification which merely using generic computing equipment to execute/run the software tools to perform the abstract idea. See MPEP 2106.05(f). For the additional elements “evaluating equivalent specifications within the set of equivalent specifications via a syntactic difference cost model to determine a syntactic difference metric between the equivalent specifications and a design implementation; selecting an equivalent specification with a lowest syntactic difference cost as a nearest specification to the design implementation” do nothing more than to add insignificant extra solution activity to the judicial exception of merely storing/gathering data for automation. See MPEP § 2106.05(h).
Under Step 2B, the claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “non-transitory machine-readable medium having instructions stored thereon, which when executed, cause one or more processors” amount to no more than mere instructions, or generic computer and/or computer components to carry out the exception, thus, cannot amount to an inventive concept. See MPEP 2105.06(f). For the additional elements “evaluating equivalent specifications within the set of equivalent specifications via a syntactic difference cost model to determine a syntactic difference metric between the equivalent specifications and a design implementation; selecting an equivalent specification with a lowest syntactic difference cost as a nearest specification to the design implementation” the courts have recognized storing and retrieving information in memory and performing repetitive calculation as a well‐understood, routine, and conventional functions in a merely generic manner (e.g., at a high level of generality) or an insignificant extra-solution activity. See MPEP 2106.05(d).II.iv and 2106.05(d).II.ii. Accordingly, the claims are not patent eligible under 35 USC 101.
12. The non-transitory machine-readable medium of claim 11, the operations further comprising:
converting RTL code for a design implementation to an implementation dataflow graph;
inserting implementation e-graph nodes generated based on the implementation dataflow graph into the specification e-graph; and evaluating equivalent specifications within the set of equivalent specifications based at least in part on the implementation e-graph nodes.
Regarding claim 12, the limitations building a set of equivalent specifications via equivalence preserving rewrites to the e-graph of the reference specification is an additional mental process under prong 1. Under prong 2, the evaluating equivalent specifications in the set of equivalent specifications via a syntactic difference cost model; and selecting an equivalent specification having a lowest syntactic difference cost according to the syntactic difference cost model limitations are additional elements that recite insignificant extra solution activity which do not amount to a practical application, nor amount to significantly more under step 2B as explained above.
13. The non-transitory machine-readable medium of claim 12, wherein building the set of equivalent specifications includes: generating the specification e-graph based on the specification dataflow graph; applying equivalence preserving rewrites to the specification e-graph;
extracting equivalent specifications from the specification e-graph that include expressions derived from the equivalence preserving rewrites; and building the set of equivalent specifications using extracted equivalent specifications.
Regarding claim 13, the limitations generating the specification e-graph based on the specification dataflow graph and building the set of equivalent specifications using extracted equivalent specifications is an additional mental process under prong 1. Under prong 2, the applying equivalence preserving rewrites to the specification e-graph; extracting equivalent specifications from the specification e-graph that include expressions derived from the equivalence preserving rewrites limitations are additional elements that recite insignificant extra solution activity which do not amount to a practical application, nor amount to significantly more under step 2B as explained above.
14. The non-transitory machine-readable medium of claim 13, the operations further comprising applying equivalence preserving rewrites to the specification e-graph until equivalence saturation of the specification e-graph is reached.
Regarding claim 14, the limitations comprising applying equivalence preserving rewrites to the specification e-graph until equivalence saturation of the specification e-graph is reached is an additional insignificant extra solution activity under prong 2.
15. The non-transitory machine-readable medium of claim 13, wherein the implementation dataflow graph and the specification dataflow graph each include first nodes to represent operators and second nodes to represent operands of the operators, the implementation dataflow graph and the specification dataflow graph each include edges between the first nodes and the second nodes, and the edges between the first nodes and the second nodes are associated with a bitwidth of a datapath defined in the RTL between the operands and the operators.
Regarding claim 15, the limitations comprising the implementation dataflow graph and the specification dataflow graph each include first nodes to represent operators and second nodes to represent operands of the operators, the implementation dataflow graph and the specification dataflow graph each include edges between the first nodes and the second nodes, and the edges between the first nodes and the second nodes are associated with a bitwidth of a datapath defined in the RTL between the operands and the operators is an additional insignificant extra solution activity under prong 2.
16. A system comprising:
one or more processors; and
a memory device having instructions stored thereon, which when executed, cause the one or more processors perform operations comprising:
converting register transfer level (RTL) code for a reference specification into a specification dataflow graph;
building a set of equivalent specifications based on equivalence preserving rewrites to a specification e-graph that is generated based on the specification dataflow graph;
evaluating equivalent specifications within the set of equivalent specifications via a syntactic difference cost model to determine a syntactic difference metric between the equivalent specifications and a design implementation;
selecting an equivalent specification with a lowest syntactic difference cost as a nearest specification to the design implementation; and
converting the nearest specification to RTL.
Claim 16, this claim is within at least one of the four categories of patent eligible subject matter as it is directing to a system claim under Step 1.
Regarding claim 16, the limitations “converting register transfer level (RTL) code for a reference specification into a specification dataflow graph; building a set of equivalent specifications based on equivalence preserving rewrites to a specification e-graph that is generated based on the specification dataflow graph” as drafted, are functions that, under its broadest reasonable interpretation, recite the abstract idea of a mental process. For example, a person is capable converting RTL code to create an e-graph of data. In same manner, a person is capable of converting RTL code with the aid of pen and paper from using the reference specification of data in creating the RTL design. Therefore, these limitations encompass a human mind carrying out the function through observation, evaluation judgment and /or opinion, or even with the aid of pen and paper. Thus, these limitations recite and falls within the “Mental Processes” grouping of abstract ideas under Prong 1.
Under Prong 2, the additional elements “one or more processors; and a memory device having instructions stored thereon, which when executed, cause the one or more processors” is recited at a high-level of generality such that it amounts no more than mere instructions for executing/applying computer model to rewrite the specification which merely using generic computing equipment to execute/run the software tools to perform the abstract idea. See MPEP 2106.05(f). For the additional elements “evaluating equivalent specifications within the set of equivalent specifications via a syntactic difference cost model to determine a syntactic difference metric between the equivalent specifications and a design implementation; selecting an equivalent specification with a lowest syntactic difference cost as a nearest specification to the design implementation” do nothing more than to add insignificant extra solution activity to the judicial exception of merely storing/gathering data for automation. See MPEP § 2106.05(h).
Under Step 2B, the claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of “one or more processors; and a memory device having instructions stored thereon, which when executed, cause the one or more processors” amount to no more than mere instructions, or generic computer and/or computer components to carry out the exception, thus, cannot amount to an inventive concept. See MPEP 2105.06(f). For the additional elements “evaluating equivalent specifications within the set of equivalent specifications via a syntactic difference cost model to determine a syntactic difference metric between the equivalent specifications and a design implementation; selecting an equivalent specification with a lowest syntactic difference cost as a nearest specification to the design implementation” the courts have recognized storing and retrieving information in memory and performing repetitive calculation as a well‐understood, routine, and conventional functions in a merely generic manner (e.g., at a high level of generality) or an insignificant extra-solution activity. See MPEP 2106.05(d).II.iv and 2106.05(d).II.ii. Accordingly, the claims are not patent eligible under 35 USC 101.
17. The system of claim 16, the operations further comprising: converting RTL code for a design implementation to an implementation dataflow graph; inserting implementation e-graph nodes generated based on the implementation dataflow graph into the specification e-graph; and evaluating equivalent specifications within the set of equivalent specifications based at least in part on the implementation e-graph nodes.
Regarding claim 17, the limitations converting RTL code for a design implementation to an implementation dataflow graph; inserting implementation e-graph nodes generated based on the implementation dataflow graph into the specification e-graph is an additional mental process under prong 1. Under prong 2, the evaluating equivalent specifications within the set of equivalent specifications based at least in part on the implementation e-graph nodes limitations are additional elements that recite insignificant extra solution activity which do not amount to a practical application, nor amount to significantly more under step 2B as explained above.
18. The system of claim 17, wherein building the set of equivalent specifications includes: generating the specification e-graph of the reference specification based on the specification dataflow graph; applying equivalence preserving rewrites to the specification e-graph; extracting equivalent specifications from the specification e-graph that include expressions derived from the equivalence preserving rewrites; and building the set of equivalent specifications using extracted equivalent specifications.
Regarding claim 18, the limitations generating the specification e-graph of the reference specification based on the specification dataflow graph and building the set of equivalent specifications using extracted equivalent specifications is an additional mental process under prong 1. Under prong 2, the applying equivalence preserving rewrites to the specification e-graph; extracting equivalent specifications from the specification e-graph that include expressions derived from the equivalence preserving rewrites limitations are additional elements that recite insignificant extra solution activity which do not amount to a practical application, nor amount to significantly more under step 2B as explained above.
19. The system of claim 18, the operations further comprising applying equivalence preserving rewrites to the specification e-graph until equivalence saturation of the specification e-graph is reached.
Regarding claim 19, the limitations comprising applying equivalence preserving rewrites to the specification e-graph until equivalence saturation of the specification e-graph is reached is an additional insignificant extra solution activity under prong 2.
20. The system of claim 18, wherein the implementation dataflow graph and the specification dataflow graph each include first nodes to represent operators and second nodes to represent operands of the operators, the implementation dataflow graph and the specification dataflow graph each include edges between the first nodes and the second nodes, and the edges between the first nodes and the second nodes are associated with a bitwidth of a datapath defined in the RTL between the operands and the operators.
Regarding claim 20, the limitations comprising the implementation dataflow graph and the specification dataflow graph each include first nodes to represent operators and second nodes to represent operands of the operators, the implementation dataflow graph and the specification dataflow graph each include edges between the first nodes and the second nodes, and the edges between the first nodes and the second nodes are associated with a bitwidth of a datapath defined in the RTL between the operands and the operators is an additional insignificant extra solution activity under prong 2.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-8 and 11-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over USPN 20220366112 to Drane et al. in view of USPN 20240320406 to Kathuria et al.
Per claim 1:
Drane discloses:
1. A method comprising:
converting register transfer level (RTL) code (Paragraph [0062] “converting RTL into an initial e-graph”) for a reference specification into a specification dataflow graph (Paragraph [0031] “from a higher-abstraction level representation of the circuit such as SystemVerilog, or from another RTL representation of the circuit, e.g., as defined in the Verilog or VHDL hardware description language”);
building an equivalence graph (e-graph) of the reference specification based on the specification dataflow graph (Paragraph [0031] “generating the graph representation of the circuit… generate the graph representation from a further RTL representation of the circuit”);
applying an equivalence preserving rewrite to the e-graph of the reference specification (Paragraph [0062] “Applying re-writes to this e-graph, the space of equivalent designs can be explored, whilst maintaining a history of all the designs we have generated”);
inserting an e-graph node for an expression in a design implementation into the e-graph of the reference specification (Paragraph [0054] “e-graphs may be modified with appropriate nodes and re-writes to reflect logic synthesis, which may improve correlation with hardware design”); and
Drane does not explicitly disclose extracting an expression having a correction to a defect within the design implementation based on the equivalence preserving rewrite to the e-graph of the reference specification.
However, Kathuria discloses in an analogous computer system extracting an expression (Paragraph [0082] “analysis and extraction 1126”)having a correction to a defect within the design implementation based on the equivalence preserving rewrite to the e-graph of the reference specification (Paragraph [0040] “recommendation tool 140, the user can make edits to the RTL design, in an iterative manner, until a desired level of equivalence is achieved… potential errors are identified and fixed… generate a report of weights of data paths that are potentially problematic, cost of potentially problematic data path, and/or an analysis of potential abort points for the downstream equivalence checking tool”).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to incorporate the method of extracting an expression having a correction to a defect within the design implementation based on the equivalence preserving rewrite to the e-graph of the reference specification as taught by Kathuria into the method of generating a register transfer level (RTL) representation of a circuit as taught by Drane. The modification would be obvious because of one of ordinary skill in the art would be motivated to add/incorporate the features of extracting an expression having a correction to a defect within the design implementation based on the equivalence preserving rewrite to the e-graph of the reference specification to provide an efficient technique to correct a defect design for optimizing the digital circuit design as suggested by Kathuria (paragraph [0005-0008]).
Per claim 2:
Drane discloses:
2. The method of claim 1, further comprising:
converting RTL code for the design implementation to an implementation dataflow graph (Paragraph [0031-0032] “generate the graph representation from a further RTL representation… the graph representation of the circuit may model a data flow between the components of the circuits, i.e., the graph representation may be a data-flow graph representing the circuit”); and
generating the e-graph node for the expression in the design implementation based on the implementation dataflow graph (Paragraph [0026] “generating a register transfer level representation of a circuit. The method comprises generating 110 the graph representation of the circuit”).
Per claim 3:
Drane discloses:
3. The method of claim 2, wherein the implementation dataflow graph and the specification dataflow graph each include first nodes to represent operators and second nodes to represent operands of the operators (Paragraph [0057] “FIG. 2, where the second e-graph contains two nodes within a single equivalence class. Nodes (ellipses) represent operators/operands, and the dashed boxes represent equivalence classes”).
Per claim 4:
Drane discloses:
4. The method of claim 3, wherein the implementation dataflow graph and the specification dataflow graph each include edges between the first nodes and the second nodes (Paragraph [0032] “vertices representing the operands are connected to the vertices representing the operators via the edges of the graph structures”).
Per claim 5:
Drane discloses:
5. The method of claim 4, wherein edges between the first nodes and the second nodes are associated with a bitwidth of a datapath defined in the RTL between the operands and the operators (Paragraph [0033] “a bit-width of the operands in the graph representation as edge labels of the edges between the vertices representing the operands and the vertices representing the operators accessing the operands”).
Per claim 6:
Drane discloses:
6. The method of claim 5, further comprising conditionally applying the equivalence preserving rewrite based on the bitwidth of the datapath associated with the equivalence preserving rewrite (Paragraph [0063] “rewrites that can be conditionally applied to the e-graph (e.g., if the matched bit-widths satisfy certain constraints), are described in FIG. 5. FIG. 5 shows a table of an example of a (bit-width dependent) set of rewrites.”).
Per claim 7:
Drane discloses:
7. The method of claim 1, further comprising:
building a set of equivalent specifications via equivalence preserving rewrites to the e-graph of the reference specification (Paragraph [0059] “Rewrites of the form l→r define equivalence relations between expressions, l˜r. Constructively applying rewrites to the e-graph”);
evaluating equivalent specifications in the set of equivalent specifications via a syntactic difference cost model (Paragraph [0065] “bit-widths in the e-graph optimization enables to correctly evaluate the cost of implementing different operators in hardware. Using a relevant hardware cost metric that can differentiate between designs, an improved or optimal architecture can be selected from the set of designs in the e-graph”); and
selecting an equivalent specification having a lowest syntactic difference cost according to the syntactic difference cost model (Paragraph [0065] “Using a relevant hardware cost metric that can differentiate between designs, an improved or optimal architecture can be selected from the set of designs in the e-graph”).
Per claim 8:
The rejection of claim 7 is incorporated and further, Drane does not explicitly discloses extracting the expression having the correction to the defect within the design implementation from the equivalent specification having the lowest syntactic difference cost.
However, Kathuria discloses in an analogous computer system extracting the expression (Paragraph [0082] “analysis and extraction 1126”) having the correction to the defect within the design implementation from the equivalent specification having the lowest syntactic difference cost (Paragraph [0040] “recommendation tool 140, the user can make edits to the RTL design, in an iterative manner, until a desired level of equivalence is achieved… potential errors are identified and fixed… generate a report of weights of data paths that are potentially problematic, cost of potentially problematic data path, and/or an analysis of potential abort points for the downstream equivalence checking tool”).
The feature of providing extracting the expression having the correction to the defect within the design implementation from the equivalent specification having the lowest syntactic difference cost would be obvious for the reasons set forth in the rejection of claim 1.
Per claim 11:
Drane discloses:
11. A non-transitory machine-readable medium having instructions stored thereon, which when executed, cause one or more processors perform operations comprising:
converting register transfer level (RTL) code (Paragraph [0062] “converting RTL into an initial e-graph”) for a reference specification into a specification dataflow graph Paragraph [0031] “from a higher-abstraction level representation of the circuit such as SystemVerilog, or from another RTL representation of the circuit, e.g., as defined in the Verilog or VHDL hardware description language”);
building a set of equivalent specifications based on equivalence preserving rewrites to a specification e-graph generated based on the specification dataflow graph (Paragraph [0031] “generating the graph representation of the circuit… generate the graph representation from a further RTL representation of the circuit”);
selecting an equivalent specification with a lowest syntactic difference cost as a nearest specification to the design implementation(Paragraph [0065] “Using a relevant hardware cost metric that can differentiate between designs, an improved or optimal architecture can be selected from the set of designs in the e-graph”); and
converting the nearest specification to RTL (Paragraph [0031-0032] “generate the graph representation from a further RTL representation… the graph representation of the circuit may model a data flow between the components of the circuits, i.e., the graph representation may be a data-flow graph representing the circuit”).
Drane does not explicitly disclose evaluating equivalent specifications within the set of equivalent specifications via a syntactic difference cost model to determine a syntactic difference metric between the equivalent specifications and a design implementation.
However, Kathuria discloses in an analogous computer system evaluating equivalent specifications within the set of equivalent specifications via a syntactic difference cost model to determine a syntactic difference metric between the equivalent specifications and a design implementation (Paragraph [0040] “recommendation tool 140, the user can make edits to the RTL design, in an iterative manner, until a desired level of equivalence is achieved… potential errors are identified and fixed… generate a report of weights of data paths that are potentially problematic, cost of potentially problematic data path, and/or an analysis of potential abort points for the downstream equivalence checking tool”);
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to incorporate the method of evaluating equivalent specifications within the set of equivalent specifications via a syntactic difference cost model to determine a syntactic difference metric between the equivalent specifications and a design implementation as taught by Kathuria into the method of generating a register transfer level (RTL) representation of a circuit as taught by Drane. The modification would be obvious because of one of ordinary skill in the art would be motivated to add/incorporate the features of evaluating equivalent specifications within the set of equivalent specifications via a syntactic difference cost model to determine a syntactic difference metric between the equivalent specifications and a design implementation to provide an efficient technique to generate a comparted report for optimizing the digital circuit design as suggested by Kathuria (paragraph [0005-0008]).
Per claim 12:
Drane discloses:
12. The non-transitory machine-readable medium of claim 11, the operations further comprising:
converting RTL code for a design implementation to an implementation dataflow graph (Paragraph [0031-0032] “generate the graph representation from a further RTL representation… the graph representation of the circuit may model a data flow between the components of the circuits, i.e., the graph representation may be a data-flow graph representing the circuit”);
inserting implementation e-graph nodes generated based on the implementation dataflow graph into the specification e-graph (Paragraph [0054] “e-graphs may be modified with appropriate nodes and re-writes to reflect logic synthesis, which may improve correlation with hardware design”); and
evaluating equivalent specifications within the set of equivalent specifications based at least in part on the implementation e-graph nodes (Paragraph [0065] “bit-widths in the e-graph optimization enables to correctly evaluate the cost of implementing different operators in hardware. Using a relevant hardware cost metric that can differentiate between designs, an improved or optimal architecture can be selected from the set of designs in the e-graph”).
Per claim 13:
Drane discloses:
13. The non-transitory machine-readable medium of claim 12, wherein building the set of equivalent specifications includes:
generating the specification e-graph based on the specification dataflow graph (Paragraph [0031] “generating the graph representation of the circuit… generate the graph representation from a further RTL representation of the circuit”);
applying equivalence preserving rewrites to the specification e-graph (Paragraph [0062] “Applying re-writes to this e-graph, the space of equivalent designs can be explored, whilst maintaining a history of all the designs we have generated”);
extracting equivalent specifications from the specification e-graph that include expressions derived from the equivalence preserving rewrites (Paragraph [0061] “a transformation of a register transfer level design into a graph representation, and of an extraction of a register transfer level representation… transformed into an e-graph 320, on which re-writes 325 are applied, leading to a dense representation of equivalent design 330, which can then be used to generate an improved or optimized RTL representation 340”); and
building the set of equivalent specifications using extracted equivalent specifications (Paragraph [0031] “generating the graph representation of the circuit… generate the graph representation from a further RTL representation of the circuit”).
Per claim 14:
Drane discloses:
14. The non-transitory machine-readable medium of claim 13, the operations further comprising applying equivalence preserving rewrites to the specification e-graph until equivalence saturation of the specification e-graph is reached (Paragraph [0026] “generating 150 an RTL representation of the circuit based on one of the plurality of equivalent representations of the circuit”).
Per claim 15:
Drane discloses:
15. The non-transitory machine-readable medium of claim 13, wherein the implementation dataflow graph and the specification dataflow graph each include first nodes to represent operators and second nodes to represent operands of the operators (Paragraph [0057] “FIG. 2, where the second e-graph contains two nodes within a single equivalence class. Nodes (ellipses) represent operators/operands, and the dashed boxes represent equivalence classes”), the implementation dataflow graph and the specification dataflow graph each include edges between the first nodes and the second nodes(Paragraph [0032] “vertices representing the operands are connected to the vertices representing the operators via the edges of the graph structures”), and
the edges between the first nodes and the second nodes are associated with a bitwidth of a datapath defined in the RTL between the operands and the operators (Paragraph [0033] “a bit-width of the operands in the graph representation as edge labels of the edges between the vertices representing the operands and the vertices representing the operators accessing the operands”).
Claims 16-20 is/are the apparatus/system claim corresponding to medium claims 11-15 respectively, and rejected under the same rational set forth in connection with the rejection of claims 11-15 respectively, as noted above.
Allowable Subject Matter
Claims 9-10 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. In order for these claims to be allowed, applicants must overcome the 101 rejections above.
Response to Arguments
Applicant's arguments filed 12/22/2025 have been fully considered but they are not persuasive.
35 USC § 101 Rejection of the Claims
With respect to applicants’ argument that the claims are directed to a specific technological improvement in automated RTL code debugging and correction tools, not to an abstract idea. Claim 1 recites specific technical operations including "building an equivalence graph (e-graph) of the reference specification based on the specification dataflow graph," "applying an equivalence preserving rewrite to the e- graph of the reference specification," "inserting an e-graph node for an expression in a design implementation into the e-graph of the reference specification," and "extracting an expression having a correction to a defect within the design implementation based on the equivalence preserving rewrite to the e-graph of the reference specification." These are not mental processes that can be performed in the human mind or with pen and paper.
An e-graph is a specialized data structure where "[r]ewrites are applied constructively to the e-graph and equivalent expressions within a rewrite remain in the e-graph data structure" such that "[a]s rewrites are applied, the e-graph grows monotonically, representing more and more equivalent expressions, which naturally captures the interaction between different rewrite rules." (As-Filed Specification, paragraph [0196]) The manipulation of such data structures with constructive rewrite application cannot practically be performed mentally. The equivalence preserving rewrites include complex operations such as "bitvector arithmetic identities, bitvector logic identities, constant expansion, arithmetic logic exchange, and merging multiple operations," including "merging additions, multiplication arrays, and fusing multiplies and additions into fused multiply-add operations." (As-Filed Specification, paragraph [0197]) These technical transformations on RTL code representations are not mental processes.
The claims are analogous to those found patent-eligible in cases involving specific
improvements to computer functionality. The claims do not merely recite performing an abstract idea on a generic computer; rather, they recite a specific technical approach using e-graphs, equivalence preserving rewrites, and syntactic difference cost models to automatically correct defects in RTL code for semiconductor design.
The practical application is that "[t]he RTL generated via the conversion of the nearest specification can be implemented using RTL synthesis tools in place of the design implementation" where "the output of a circuit generated based on the nearest specification will conform with the specification." (As-Filed Specification, paragraph [0208]) The claims thus provide a specific technological improvement to the semiconductor design process.
Examiner respectfully disagrees. Applicants are indicating that “a specialized data structure,” “rewrite rules,” “bitvector arithmetic identities, bitvector logic identities, constant expansion, arithmetic logic exchange, and merging multiple operations," including "merging additions, multiplication arrays, and fusing multiplies and additions into fused multiply-add operations,” “circuit generated based on the nearest specification” etc., and pointed different sections of applicants filed specification [e.g., 196,197,208]. Applicants are reminded that the features upon which applicant relies (i.e., as indicated above) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Further, with respect to the improvement to computer functionality. The claims limitations are simply stating the steps of building e-graph for a defect in design specification. Nothing in the claims recite of any improvement to computer functionality. Applicants may want to revisit the specification and amend claims to further recite the improvement to computer functionality. As indicated above “converting register transfer level (RTL) code for a reference specification into a specification dataflow graph” and “building an equivalence graph (e-graph) of the reference specification based on the specification dataflow graph” falls within the “Mental Processes” grouping of abstract ideas under Prong 1. And “applying an equivalence preserving rewrite to the e-graph of the reference specification” is recited at a high-level of generality such that it amounts no more than mere instructions for executing/applying computer model to rewrite the specification which merely using generic computing equipment to execute/run the software tools to perform the abstract idea. See MPEP 2106.05(f). For the additional elements “inserting an e-graph node for an expression in a design implementation into the e-graph of the reference specification; and extracting an expression having a correction to a defect within the design implementation based on the equivalence preserving rewrite to the e-graph of the reference specification” do nothing more than to add insignificant extra solution activity to the judicial exception of merely storing/gathering data for automation. See MPEP § 2106.05(h). Also, the courts have recognized storing and retrieving information in memory and performing repetitive calculation as a well‐understood, routine, and conventional functions in a merely generic manner (e.g., at a high level of generality) or an insignificant extra-solution activity. See MPEP 2106.05(d). Accordingly, the claims are not patent eligible under 35 USC 101 and the rejection is maintained.
USC §103 Rejection of the Claims
With respect to applicants’ argument that claim 1 recites a specific technical approach where an expression having a correction to a defect is extracted based on equivalence preserving rewrites applied to an e-graph of a reference specification. Neither Drane's optimization-focused e-graph approach nor Kathuria's recommendation-based verification tool teaches or suggests "extracting an expression having a correction to a defect within the design implementation based on the equivalence preserving rewrite to the e-graph of the reference specification" as recited by claims 1, 11, and 16.
Examiner respectfully disagrees. As indicated in the rejection that the above argued limitations are not tuahgt by Drane, however, Kathuria discloses in an analogous computer system discloses these limitations. Kathuria discloses an improved methods for equivalence checking of digital circuit designs. Kathuria discloses during the final stages of design, the layout is refined by verifying circuit function (analysis and extraction 1126) and ensuring compliance with manufacturing, electrical, and design specifications (physical verification 1128). Finally, the layout geometry is transformed to improve manufacturability (resolution enhancement 1130). See paragraph [0082]. Kathuria discloses the recommendation tool 140 and RTL lint tool 130 enhance the chip design process by enabling early error detection and optimization. The recommendation tool 140 enables users to iteratively edit RTL designs to achieve a desired level of equivalence, identifying and fixing potential errors early to reduce overall design time, cost, and complexity. The tool 140 provides parameters to guide the downstream synthesis process within the synthesis tool 145. The RTL lint tool 130 generates reports on potentially problematic data paths, including their costs and potential abort points for equivalence checking, aiding in design quality and reliability. This approach combines early-stage linting with automated recommendations to optimize Performance, Power, and Area (PPA) before physical design. See paragraph [0040]. The motivation to combine Drane with Kathuria provide an efficient technique to correct a defect design for optimizing the digital circuit design as suggested by Kathuria (paragraph [0005-0008]). Nowhere, does the combination of Drane and Kathuria disclose the above argued limitations as recited in claims 1, 11 and 16. Accordingly, claims 1-8 and 11-20 are still stand rejected under 35 U.S.C. 103.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Satish Rampuria whose telephone number is 571-272-3732. The examiner can normally be reached on Monday-Friday from 8:30 AM to 5:00 PM.
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/Satish Rampuria/ Primary Examiner, Art Unit 2193
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