DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note by the Examiner
For clarity, references to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and examiner explanations for 102 &/or 103 rejections are provided in parenthesis.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Ito (Patent No.: US 11,955,906 B2) in view of Ishimatsu et al. (Pub. No.: US 2021/0217741 A1), hereinafter as Ishimatsu.
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Image A, Ito Fig. 6 showing a thicker insulating layer, the front and back sides of the base material, and the front side of the packaging substrate
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Image B, Ito Fig. 6 showing build-up layers, high voltage overlapping region D1, and low voltage overlapping region D2
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Image C, Ito Fig. 6 showing multiple vias in region D1
With respect to Claim 1, Ito discloses a package substrate (Ito Figs. 5&6, board main body part 10, multilayer structure 4) in which circuit elements having different operating voltages (high voltage circuits 50, where the high voltage circuits 50 are disposed in a high voltage region B (see Ito Figs. 3-5 and Ito col. 9, ln. 34-40), which in turn is located in a high voltage overlapping region D1 (see Ito Fig. 6 and Ito col. 15, ln. 50-57) and where “the high voltage circuits 50 include first high voltage circuits 51 connected to the first switching elements 31; and second high voltage circuits 52 connected to the second switching elements 32.” (Ito Figs. 1-4 and Ito col. 8, ln. 3-7);
a low voltage circuit 53 (Ito Figs. 1-4), where the low voltage circuit 53 is disposed in a low voltage region A (see Ito Figs. 3-5 and Ito col. 9, ln. 34-40), which in turn is located in a low voltage overlapping region D2 (see Ito Fig. 6 and Ito col. 15, ln. 50-57);
switching elements (3, 31, 32, Ito Figs. 1&7); an inverter 100 (Ito Fig. 1); and transformers (8, 81, 82, Ito Figs. 2&3)) exist in a mixed manner is mounted on a front surface (see above Image A) side thereof (Ito Fig. 3&6),
and in which electrical paths extending from the front surface side to a back surface side are formed for each of the different operating voltages (see Ito Fig. 6 and Ito col. 9, ln. 18-23: “In the multilayer structure 4 there are made vias 72 (e.g., filled vias) for electrically connecting different wiring layers (e.g., wiring layers adjacent to each other in the thickness direction Z). The vias 72 are made so as to penetrate through the insulating layers 40, and conductors (copper, etc.) are provided inside the vias 72,” where the wiring layers are labeled 41-46, 71 in Ito Fig. 6),
the package substrate comprising: a base material being a flat plate-shaped insulator (see Ito Fig. 6 and Image A, a thicker insulating layer 40 is shown between a third layer 43 and a fourth layer 44, all of which are part of the multilayer structure 4, which makes up the board main body part 10, where the board main body part 10 is described as “a plate-like board main body part 10.” (Ito col. 7, ln. 64));
a build-up layer (see above Image B and Ito Fig. 6; where wiring layers 41, 43, and 45 and the insulating layers 40 between said wiring layers make up one build-up layer; and where wiring layers 42, 44, and 46 and the insulating layers 40 between said wiring layers make up another build-up layer) which is formed on at least one of a front surface (see Image A) or a back surface (see Image A) of the base material (Image B and Ito Fig. 6) and in which a wiring layer (Ito Fig. 6, layers 41-46: “Each of the first layer 41, the second layer 42, the third layer 43, and the fourth layer 44 is a wiring layer.” (Ito col. 8, ln. 60-63), and “Each of the fifth layer 45 and the sixth layer 46 is a wiring layer.” (Ito col. 8, ln. 65-66)) and an insulating layer (Ito Fig. 6, insulating layers 40) covering the wiring layer are alternately laminated (Ito Fig. 6);
and vias (Ito Fig. 6, vias 72) which are formed in the base material and the insulating layer, and are each configured to electrically connect the wiring layers to each other (see Ito col. 9, ln. 18-23: “In the multilayer structure 4 there are made vias 72 (e.g., filled vias) for electrically connecting different wiring layers (e.g., wiring layers adjacent to each other in the thickness direction Z). The vias 72 are made so as to penetrate through the insulating layers 40, and conductors (copper, etc.) are provided inside the vias 72.” Although Ito Fig. 6 may not necessarily show it, multiple vias can penetrate the base material (the thicker insulating layer 40) as seen in the previous quoted material.),
wherein the wiring layers having the different operating voltages (see Ito col. 9, ln. 34-40: “As shown in FIGS. 3 and 4, on both of the first layer 41 and the second layer 42 there are formed a low voltage region A in which the low voltage circuit 53 is disposed, a high voltage region B in which the high voltage circuits 50 are disposed, and an insulating region E in which the low voltage region A is electrically isolated from the high voltage region B,” where the low voltage region A is located in a low voltage overlapping region D2 (see Ito Fig. 6 and Ito col. 15, ln. 50-57) and the high voltage region B is located in a high voltage overlapping region D1 (see Ito Fig. 6 and Ito col. 15, ln. 50-57)) are arranged so as to be spaced apart by predetermined distances in accordance with the different operating voltages, respectively (see Ito Fig. 6, region E, and Ito col. 9, ln. 38-40: “an insulating region E in which the low voltage region A is electrically isolated from the high voltage region B.”),
and wherein the wiring layers having the same operating voltage are arranged so as to overlap with each other in a plan view at least in the build-up layer (see Ito Figs. 3-6 and Ito col. 15, ln. 50-57: “Here, a region of the board main body part 10 that overlaps both of the first-layer high voltage region B1 and the second-layer high voltage region B2 as viewed from top is a high voltage overlapping region D1 (see FIG. 6). In addition, a region of the board main body part 10 that overlaps both of the first-layer low voltage region A1 and the second-layer low voltage region A2 as viewed from top is a low voltage overlapping region D2 (see FIG. 6).”).
Ito does not disclose a semiconductor chip in which circuit elements having different operating voltages exist in a mixed manner is mounted on a front surface side thereof.
However, Ishimatsu discloses a semiconductor chip (Ishimatsu Figs. 35-57, semiconductor device A2) comprising an inverter circuit (see Ishimatsu [1150]: “a three-phase inverter circuit”) in which circuit elements having different operating voltages (high-voltage region 734 (Ishimatsu Figs. 55&56), a low-voltage region 744 (Ishimatsu Figs. 53&55), transistors (semiconductor chips 4A-4D, Ishimatsu [1150] and Ishimatsu Fig. 39-41) and a transformer 690 (Ishimatsu Fig. 49)) exist in a mixed manner (Ishimatsu Fig. 39).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the device of Ito by having the semiconductor chip of Ishimatsu with the inverter circuit element formed on a front side surface of the package substrate of Ito in order to increase functional density and packaging efficiency.
With respect to Claim 2, Ito discloses the package substrate according to claim 1, wherein two or more of the vias are formed between the wiring layers having a higher one of the different operating voltages (Ito Fig. 6 and above Image C; high voltage overlapping region D1, sixth layer 46, second layer 42, and vias 72).
With respect to Claim 3, Ito discloses the package substrate according to claim 2, wherein the build-up layer (Image B and Ito Fig. 6) is formed on both of the front surface and the back surface of the base material (Image B and Ito Fig. 6), and wherein the number of the wiring layers and the number of the insulating layers on the front surface of the base material are the same as the number of the wiring layers and the number of the insulating layers on the back surface of the base material, respectively (see Ito col. 8, ln. 45-47: “As shown in FIG. 6, the board main body part 10 has a multilayer structure 4 with even-numbered layers including a first layer 41 and a second layer 42,” with three wiring layers (41, 43, 45) and two insulating layers (40) on the front side and three wiring layers (42, 44, 46) and two insulating layers (40) on the back side (Ito Fig. 6)).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Ito in view of Ishimatsu and Morikawa et al. (Patent No.: US 7,741,724 B2), hereinafter as Morikawa.
With respect to Claim 4, Ito discloses the package substrate according to claim 3, wherein, in a region of the build-up layer in which the wiring layers having the same operating voltage are arranged so as to overlap with each other (see Ito Figs. 3-6 and Ito col. 15, ln. 50-57: “Here, a region of the board main body part 10 that overlaps both of the first-layer high voltage region B1 and the second-layer high voltage region B2 as viewed from top is a high voltage overlapping region D1 (see FIG. 6). In addition, a region of the board main body part 10 that overlaps both of the first-layer low voltage region A1 and the second-layer low voltage region A2 as viewed from top is a low voltage overlapping region D2 (see FIG. 6).” This quote and Ito Fig. 6 shows that the wiring layers located in region D1 overlap and have the same operating voltage and the wiring layers located in region D2 overlap and have the same operating voltage).
Ito does not disclose a wiring width of an outer layer is smaller than a wiring width of an inner layer.
However, Morikawa discloses a wiring width of an outer layer (Morikawa Fig. 1&2, fourth wiring layer 15) is smaller than a wiring width of an inner layer (Morikawa Fig. 1&2, third wiring layer 11).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the packaging substrate of Ito to have the different wiring widths taught by Morikawa in order to suppress downward propagation of cracks (see Morikawa, col. 4, ln. 3-10: “It is preferable that the third wiring layer 11 is located so as to overlap the fourth wiring layer 15 and is larger in area than an opening (a pad opening 16 that is to be described) in a protection film 17. With the structure described above, the third wiring layer 11 serves as a stopper wiring layer to suppress downward propagation of cracks by relaxing a load imposed on the fourth wiring layer 15”).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Ito in view of Ishimatsu and Miki (Pub. No.: US 20230402431 A1), using Miki’s foreign priority date of June 9, 2022.
With respect to Claim 5, Ito and Ishimatsu disclose a semiconductor device, comprising: the package substrate of claim 1 (Ito Fig. 6); a semiconductor chip (Ishimatsu Figs. 35-57, semiconductor device A2) mounted on a front surface side of the package substrate (Ito Fig. 6).
However, the combined device of Ito and Ishimatsu does not include an encapsulating resin that encapsulates the semiconductor chip of Ishimatsu.
However, Miki discloses a semiconductor device that has an encapsulating resin (Miki Fig. 1, sealing resin 91) for encapsulating the semiconductor chip (Miki Fig. 1, semiconductor chips 20 and 30-33).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the device of Ito and Ishimatsu by adding the encapsulating resin taught by Miki in order to protect the semiconductor chip of Ishimatsu.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EKATERINA T BIRCH whose telephone number is (571)272-8676. The examiner can normally be reached Mon-Thur, 8am-6pm.
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/E.T.B./Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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