DETAILED ACTION
This Office Action is in response to Applicant’s Remarks filed on 06/17/2026.
Currently, claims 7-8 and 10-27 are pending in the application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
Applicant's arguments with respect to claim(s) 7-8 and 10-17 have been considered. Applicant argues that the rejection of canceled dependent claim 9 is in clear error because Cho’s electrical connectors 124/202 do not extend through Cho’s encapsulant 112. This argument is not found persuasive because at least a portion of Cho’s electrical connectors 124/202 at least partially extend through a portion of Cho’s encapsulant 112 (see circled regions of annotated figure below). Therefore, Cho does teach the limitations of canceled dependent claim 9 and amended claim 7.
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Annotated Cho Fig. 2
Drawings
The corrected drawings were received on 06/17/2026. The drawings are accepted.
Claim Objections
Claim 20 is objected to because of the following informality:
In claim 20, “one of more of the first portions” should read “one or more of the first portions”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 7, 10-13 and 16-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by CHO et al. (US Pub. No. 2021/0233823).
Regarding independent claim 7, Cho teaches a semiconductor device module (Fig. 2), comprising:
a core layer (Fig. 2, 102, ¶ [0034]) comprising an opening (Fig. 2110, ¶ [0035]);
a first semiconductor transistor die (Fig. 2, 108, [0034]) disposed within the opening, the first semiconductor transistor die comprising an emitter/source contact pad (Fig. 2, 118, ¶ [0037]), a drain/collector contact pad (Fig. 2, 114, ¶ [0037]), and a gate contact pad (Fig. 2, 122, ¶ [0037]), and
an encapsulant (Fig. 2, 112, ¶ [0035]) embedding the first semiconductor transistor die,
wherein at least one of the contact pads is connected with two or more electrical connectors (Figs. 2 & 4A, 124 + 202, ¶ [0047]) which are disposed in a symmetrical manner (Fig. 4A, 124 are disposed symmetrically around 108) on opposing lateral sides of the first semiconductor transistor die, and
wherein the two or more electrical connectors (Figs. 2 & 4A, 124 + 202, ¶ [0047]) extend through the encapsulant (at least a portion of Cho’s electrical connectors 124/202 at least partially extend through a portion of Cho’s encapsulant 112. See circled regions of annotated figure below) and form protruding sections (Fig. 2, portions of 124/202 above upper surface of 112) above an upper surface of the encapsulant.
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Annotated Cho Fig. 2
Regarding claim 10, Cho teaches the semiconductor device module of claim 7, and Cho teaches at least one metallic layer (Fig. 2, portion of 204 + 126 above upper surface of 112, ¶ [0046]) disposed within the semiconductor device module and connected with the two or more electrical connectors (Figs. 2 & 4A, 124 + 202, ¶ [0047]).
Regarding claim 11, Cho teaches the semiconductor device module of claim 10, and Cho teaches two or three metallic layers (Fig. 2, 204 + 126, ¶ [0046]) disposed within the semiconductor device module and each one connected with one of the two or more electrical connectors (Figs. 2 & 4A, 124 + 202, ¶ [0047]), respectively (Fig. 2, 126/204 are each respectively connected with one via 124/202).
Regarding claim 12, Cho teaches the semiconductor device module of claim 10, and Cho teaches a laminate layer (Fig. 2, 138, ¶ [0045]) disposed on an upper surface of the core layer (Fig. 2, 102, ¶ [0034]), wherein one, two or three metallic layers (Fig. 2, 204 + 126, ¶ [0046], portions of 204 and 126 are at least partially within 138) are disposed within the laminate layer.
Regarding claim 13, Cho teaches the semiconductor device module of claim 7, and Cho teaches a second semiconductor transistor die (Fig. 5, 502, ¶ [0060]) electrically connected with the first semiconductor transistor die (Fig. 5, 108, ¶ [0060]) to form a half-bridge configuration (¶ [0060] teaches that Cho’s semiconductor die 108 can be connected to another semiconductor die in a half bridge circuit).
Regarding claim 16, Cho teaches the semiconductor device module of claim 13, and Cho teaches that the second semiconductor transistor die (Fig. 5, 502, ¶ [0060]) is embedded by an encapsulant (Fig. 5, 112, ¶ [0035]).
Regarding claim 17, Cho teaches the semiconductor device module of claim 7, and Cho teaches that the core layer (Fig. 2, 102, ¶ [0034]) comprises a printed circuit board (¶ [0034] teaches that 102 can be a PCB substrate).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8 and 14-15 are rejected under 35 U.S.C. 103 as being obvious over CHO et al. (US Pub. No. 2021/0233823) in view of ST. GERMAIN et al. (US Pub. No. 2019/0385939) and further in view of HONG et al. (US Pub. No. 2023/0155509).
Regarding claim 8, Cho teaches the semiconductor device module of claim 7.
However, Cho does not explicitly teach that two or three of the contact pads are respectively connected with two or more electrical connectors which are disposed in a symmetrical manner on opposing lateral sides of the first semiconductor transistor die.
However, St. Germain is a pertinent art that teaches that leads can be placed in any number and any location depending on a desired final configuration of a semiconductor package (see St. Germain ¶ [0094]). Further, it is known in the art that symmetric connecting conductors have the effect of cancelling out magnetic fluxes and reducing mutual inductance (see Hong ¶ [0056]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the number and location of Cho’s conductive vias connected to their terminal bond pads to be arranged symmetrically around Cho’s semiconductor dies according to the teaching of Hong (¶ [0056]) in order to cancel out magnetic flux and reduce mutual inductance.
Regarding claim 14, Cho teaches the semiconductor device module of claim 13, and Cho teaches that the second semiconductor transistor die (Fig. 5, 502, ¶ [0060]) is disposed within the core layer (Fig. 5, 102, ¶ [0034]) and comprises an emitter/source contact pad (Fig. 5, 504, ¶ [0059]), a drain/collector contact pad (Fig. 5, 508, ¶ [0059]), and a gate contact pad (Fig. 5, 512, ¶ [0059]).
However, the embodiment of Cho Fig. 5 does not explicitly teach that at least one of the contact pads is connected with two or more electrical connectors which are disposed in a symmetrical manner on opposing sides of the first semiconductor transistor die.
However, St. Germain is a pertinent art that teaches that leads can be placed in any number and any location depending on a desired final configuration of a semiconductor package (see St. Germain ¶ [0094]). Further, it is known in the art that symmetric connecting conductors have the effect of cancelling out magnetic fluxes and reducing mutual inductance (see Hong ¶ [0056]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the number and location of Cho’s conductive vias connected to their terminal bond pads to be arranged symmetrically around Cho’s semiconductor dies according to the teaching of Hong (¶ [0056]) in order to cancel out magnetic flux and reduce mutual inductance.
Regarding claim 15, Cho teaches the semiconductor device module of claim 14.
However, Cho does not explicitly teach that two or three of the contact pads are respectively connected with two or more electrical connectors which are disposed in a symmetrical manner on lateral opposing sides of the first semiconductor transistor die.
However, St. Germain is a pertinent art that teaches that leads can be placed in any number and any location depending on a desired final configuration of a semiconductor package (see St. Germain ¶ [0094]). Further, it is known in the art that symmetric connecting conductors have the effect of cancelling out magnetic fluxes and reducing mutual inductance (see Hong ¶ [0056]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the number and location of Cho’s conductive vias connected to their terminal bond pads to be arranged symmetrically around Cho’s semiconductor dies according to the teaching of Hong (¶ [0056]) in order to cancel out magnetic flux and reduce mutual inductance.
Claims 18-27 are rejected under 35 U.S.C. 3 as being obvious over FAUL et al. (US Pub. No. 2020/0279785) in view of TSUYUTANI et al. (US Pub. No. 2014/0085854) and further in view of CHO et al. (US Pub. No. 2021/0233823).
Regarding independent claim 18, Faul teaches a semiconductor device module (Fig. 1), comprising:
a semiconductor transistor die (Fig. 1, 14, ¶ [0035]) comprising contact pads (Fig. 1, 16, ¶ [0035]) ;
at least two electrical connectors (Fig. 1, 32 + 34, ¶ [0051]) disposed in a symmetrical manner on opposing sides of the semiconductor transistor die (Fig. 1) and connected with at least one of the contact pads; and
an encapsulant (Fig. 1, 26, ¶ [0046]), and
wherein for each of the electrical connectors, a second portion (Fig. 1, 32, ¶ [0050] teaches a plugged via portion of 32) of the electrical connector extends upwardly (the Examiner notes that Faul’s device orientation is upside down when compared to Applicant’s device orientation) from the first portion through the opening and the encapsulant and forms a protruding section of the electrical connector (Fig. 1, portions of 32 in 12, ¶ [0033]) above an upper surface of the encapsulant;
wherein the encapsulant at least partially encapsulates the semiconductor transistor die and the first portion of each of the electrical connectors (Fig. 1).
However, Faul does not explicitly teach a core layer comprising an opening;
a semiconductor transistor die comprising an emitter/source contact pad, a drain/collector contact pad, and a gate contact pad;
wherein the semiconductor transistor die and a first portion of each of the electrical connectors are disposed in the opening,
wherein the semiconductor transistor die and a first portion of each of the electrical connectors are disposed in the opening,
wherein the encapsulant is disposed in the opening and at least partially encapsulates the semiconductor transistor die and the first portion of each of the electrical connectors;
a second portion of the electrical connector extends upwardly from the first portion through the opening and the encapsulant and forms a protruding section of the electrical connector above an upper surface of the encapsulant and an upper surface of the core layer.
However, Tsuyutani is a pertinent art that teaches a core layer (Fig. 10, 111, ¶ [0035]) comprising an opening (Fig. 10, area of 112, ¶ [0035]);
wherein the semiconductor transistor die (Fig. 10, 120, ¶ [0034] teaches a semiconductor IC 120 corresponding to Faul’s electronic device 14) and a first portion (Fig. 10, portion of 130 near an upper surface of 120, ¶ [0038]) of each of the electrical connectors are disposed in the opening,
wherein the encapsulant is disposed in the opening and at least partially encapsulates the semiconductor transistor die and the first portion of each of the electrical connectors (Fig. 10),
a second portion of the electrical connector (Fig. 10, portion of 130 near upper surface of 112) extends upwardly from the first portion through the opening and the encapsulant and forms a protruding section (Fig. 10, portion of 130 above 112 and 111) of the electrical connector above an upper surface of the encapsulant and an upper surface of the core layer.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Faul’s device to be embedded in an opening in a core layer according to the teaching of Tsuyutani (Fig. 10) in order to integrate Faul’s device into a circuit board while reducing thickness (Tsuyutani ¶¶ [0004]-[0005] & [0022]).
However, Faul modified by Tsuyutani does not explicitly teach a semiconductor transistor die comprising an emitter/source contact pad, a drain/collector contact pad, and a gate contact pad.
However, Faul does teach that their electronic device can be a semiconductor chip with multiple terminal pads (Faul Fig. 7a, ¶¶ [0031] & [0035]). It would be obvious that Faul’s terminal pads can be used as emitter/source, drain/collector, and gate connections in a similar manner to Cho (Cho Fig. 2, ¶ [0037]) depending on the type of semiconductor chip that is used.
Regarding claim 19, Faul modified by Tsuyutani in view of Cho teaches the semiconductor device module of claim 18, and Faul teaches that the first portion (Fig. 1, 34, ¶ [0051]) of each of the electrical connectors is an elongated base portion (Fig. 1, ¶ [0051]), and wherein the second portion (Fig. 1, 32, ¶ [0050] teaches that 32 can be a plugged via shape) of each of the electrical connectors is a column portion (Fig. 1, ¶ [0050] teaches that 32 can include a plugged via in addition to a metallization).
Regarding claim 20, Faul modified by Tsuyutani in view of Cho teaches the semiconductor device module of claim 18, and Faul teaches at least two clips (Fig. 1, 18, ¶ [0039]), wherein each clip electrically connects one of the contact pads (Fig. 1, 16, ¶ [0035]) of the semiconductor transistor die (Fig. 1, 14, ¶ [0035]) with one or more of the first portions (Fig. 1, 34, ¶ [0051]) of the electrical connectors.
Regarding claim 21, Faul modified by Tsuyutani in view of Cho teaches the semiconductor device module of claim 18, and Faul modified by Tsuyutani teaches a metallic substrate (Faul Fig. 1, 18, ¶ [0041]) disposed in the opening of the core layer (Faul modified by Tsuyutani conductive layer 18 is in Faul’s casting compound 16 which would correspond to an area of Tsuyutani’s housing section 112) and at least partially encapsulated by the encapsulant (Faul Fig. 1, 26, ¶ [0046]), wherein the semiconductor transistor die (Fig. 1, 14, ¶ [0035]) is disposed with one of the contact pads (Fig. 1, 16, ¶ [0035]) attached to the metallic substrate (Fig. 1, 16 is attached to 18 through 22, ¶ [0039]).
Regarding claim 22, Faul modified by Tsuyutani in view of Cho teaches the semiconductor device module of claim 21, and Faul teaches that the first portions (Fig. 1, 34, ¶ [0051]) of at least two of the electrical connectors (Fig. 1, 32 + 34, ¶ [0051]) are attached to the metallic substrate (Faul Fig. 1, 18, ¶ [0041]).
Regarding claim 23, Faul modified by Tsuyutani in view of Cho teaches the semiconductor device module of claim 18, and Faul modified by Tsuyutani teaches a lower laminate layer (Faul Fig. 1, upper 12, ¶ [0033]) applied to a lower surface of the core layer (It would be obvious that Faul modified by Tsuyutani’s upper foil substrate 12 would extend across Faul modified by Tsuyutani’s core layer and encapsulation in a similar manner to Tsuyutani’s foil 170, see Fig. 10) and forming a lower boundary of the opening (Tsuyutani Fig. 10, area of 112, ¶ [0035]) of the core layer.
Regarding claim 24, Faul modified by Tsuyutani in view of Cho teaches the semiconductor device module of claim 23, and Faul teaches that the first portions (Fig. 1, 34, ¶ [0051]) of at least two of the electrical connectors are attached (Fig. 1, 34 are attached to upper 12 through 18) to the lower laminate layer (Fig. 1, upper 12, ¶ [0033]).
Regarding claim 25, Faul modified by Tsuyutani in view of Cho teaches the semiconductor device module of claim 18, and Faul modified by Tsuyutani teaches an upper laminate layer (Faul Fig. 1, lower 12, ¶ [0033]) applied to an upper surface of the core layer (It would be obvious that Faul modified by Tsuyutani’s lower foil substrate 12 would extend across Faul modified by Tsuyutani’s core layer and encapsulation in a similar manner to Tsuyutani’s resist film 140, see Fig. 10) and forming an upper boundary of the opening (Tsuyutani Fig. 10, area of 112, ¶ [0035]) of the core layer , wherein the protruding section (Faul Fig. 1, 32 in lower 12) of each of the electrical connectors is embedded in the upper laminate layer.
Regarding claim 26, Faul modified by Tsuyutani in view of Cho teaches the semiconductor device module of claim 25, and Faul teaches one or more metallic layers (Faul Fig. 1, ¶ [0050] teaches that 32 can include a plugged via in addition to a metallization) embedded in the upper laminate layer (Fig. 1, lower 12, ¶ [0033]), wherein the protruding section of each of the electrical connectors (Faul Fig. 1, 32 in lower 12) is connected to one of the metallic layers.
Regarding claim 27, Faul modified by Tsuyutani in view of Cho teaches the semiconductor device module of claim 26, and Faul teaches that a portion of each of the metallic layers (Fig. 1, portion of 32 metallization in contact with 24, ¶ [0043]) extends upwardly through the upper laminate layer (Fig. 1, lower 12, ¶ [0033]) and is exposed at an upper surface of the upper laminate layer (Fig. 1, lower surface of 12).
Cited Prior Art
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant.
Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/R.P.S./
Examiner, Art Unit 2813
/STEVEN B GAUTHIER/ Supervisory Patent Examiner, Art Unit 2813
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