DETAILED ACTION
This Office Action is in response to the Applicant Election filed on 02/16/2026.
Currently, claims 1-17 are pending in the application. Currently, claims 1-6 are withdrawn.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention II (claims 7-17) and Species II (Fig. 2C) in the reply filed on 02/16/2026 is acknowledged. Claims 1-6 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a non-selected invention, there being no allowable generic or linking claim. Claims 7-17 are examined in this Office action.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/09/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the Examiner.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: 140, 140A, and 140B.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: 221.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the drain/collector pad must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection(s) to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 16 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 16 recites the limitation “the encapsulant”. There is insufficient antecedent basis for the limitation in this claim. For the purpose of examination, this limitation will be read as “an encapsulant”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 7, 9-13 and 16-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by CHO et al. (US Pub. No. 2021/0233823).
Regarding independent claim 7, Cho teaches a semiconductor device module (Fig. 2), comprising:
a core layer (Fig. 2, 102, ¶ [0034]) comprising an opening (Fig. 2110, ¶ [0035]);
a first semiconductor transistor die (Fig. 2, 108, [0034]) disposed within the opening, the first semiconductor transistor die comprising an emitter/source contact pad (Fig. 2, 118, ¶ [0037]), a drain/collector contact pad (Fig. 2, 114, ¶ [0037]), and a gate contact pad (Fig. 2, 122, ¶ [0037]),
wherein at least one of the contact pads is connected with two or more electrical connectors (Figs. 2 & 4A, 124 + 202, ¶ [0047]) which are disposed in a symmetrical manner (Fig. 4A, 124 are disposed symmetrically around 108) on opposing lateral sides of the first semiconductor transistor die.
Regarding claim 9, Cho teaches the semiconductor device module of claim 7, and Cho teaches an encapsulant (Fig. 2, 112, ¶ [0035]) embedding the first semiconductor transistor die (Fig. 2, 108, [0034]), wherein the two or more electrical connectors (Figs. 2 & 4A, 124 + 202, ¶ [0047]) extend through the encapsulant and form protruding sections (Fig. 2, portions of 124 above upper surface of 112) above an upper surface of the encapsulant.
Regarding claim 10, Cho teaches the semiconductor device module of claim 9, and Cho teaches at least one metallic layer (Fig. 2, 204 + 126, ¶ [0046]) disposed within the semiconductor device module and connected with the two or more electrical connectors (Figs. 2 & 4A, 124 + 202, ¶ [0047]).
Regarding claim 11, Cho teaches the semiconductor device module of claim 10, and Cho teaches two or three metallic layers (Fig. 2, 204 + 126, ¶ [0046]) disposed within the semiconductor device module and each one connected with one of the two or more electrical connectors (Figs. 2 & 4A, 124 + 202, ¶ [0047]), respectively (Fig. 2, 126/204 are each respectively connected with one via 124/202).
Regarding claim 12, Cho teaches the semiconductor device module of claim 10, and Cho teaches a laminate layer (Fig. 2, 138, ¶ [0045]) disposed on an upper surface of the core layer (Fig. 2, 102, ¶ [0034]), wherein one, two or three metallic layers (Fig. 2, 204 + 126, ¶ [0046], portions of 204 and 126 are at least partially within 138) are disposed within the laminate layer.
Regarding claim 13, Cho teaches the semiconductor device module of claim 7, and Cho teaches a second semiconductor transistor die (Fig. 5, 502, ¶ [0060]) electrically connected with the first semiconductor transistor die (Fig. 5, 108, ¶ [0060]) to form a half-bridge configuration (¶ [0060] teaches that Cho’s semiconductor die 108 can be connected to another semiconductor die in a half bridge circuit).
Regarding claim 16, Cho teaches the semiconductor device module of claim 13, and Cho teaches that the second semiconductor transistor die (Fig. 5, 502, ¶ [0060]) is embedded by an encapsulant (Fig. 5, 112, ¶ [0035]).
Regarding claim 17, Cho teaches the semiconductor device module of claim 7, and Cho teaches that the core layer (Fig. 2, 102, ¶ [0034]) comprises a printed circuit board (¶ [0034] teaches that 102 can be a PCB substrate).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8 and 14-15 are rejected under 35 U.S.C. 103 as being obvious over CHO et al. (US Pub. No. 2021/0233823) in view of ST. GERMAIN et al. (US Pub. No. 2019/0385939) and further in view of HONG et al. (US Pub. No. 2023/0155509).
Regarding claim 8, Cho teaches the semiconductor device module of claim 7.
However, Cho does not explicitly teach that two or three of the contact pads are respectively connected with two or more electrical connectors which are disposed in a symmetrical manner on opposing lateral sides of the first semiconductor transistor die.
However, St. Germain is a pertinent art that teaches that leads can be placed in any number and any location depending on a desired final configuration of a semiconductor package (see St. Germain ¶ [0094]). Further, it is known in the art that symmetric connecting conductors have the effect of cancelling out magnetic fluxes and reducing mutual inductance (see Hong ¶ [0056]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the number and location of Cho’s conductive vias connected to their terminal bond pads to be arranged symmetrically around Cho’s semiconductor dies according to the teaching of Hong (¶ [0056]) in order to cancel out magnetic flux and reduce mutual inductance.
Regarding claim 14, Cho teaches the semiconductor device module of claim 13, and Cho teaches that the second semiconductor transistor die (Fig. 5, 502, ¶ [0060]) is disposed within the core layer (Fig. 5, 102, ¶ [0034]) and comprises an emitter/source contact pad (Fig. 5, 504, ¶ [0059]), a drain/collector contact pad (Fig. 5, 508, ¶ [0059]), and a gate contact pad (Fig. 5, 512, ¶ [0059]).
However, the embodiment of Cho Fig. 5 does not explicitly teach that at least one of the contact pads is connected with two or more electrical connectors which are disposed in a symmetrical manner on opposing sides of the first semiconductor transistor die.
However, St. Germain is a pertinent art that teaches that leads can be placed in any number and any location depending on a desired final configuration of a semiconductor package (see St. Germain ¶ [0094]). Further, it is known in the art that symmetric connecting conductors have the effect of cancelling out magnetic fluxes and reducing mutual inductance (see Hong ¶ [0056]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the number and location of Cho’s conductive vias connected to their terminal bond pads to be arranged symmetrically around Cho’s semiconductor dies according to the teaching of Hong (¶ [0056]) in order to cancel out magnetic flux and reduce mutual inductance.
Regarding claim 15, Cho teaches the semiconductor device module of claim 14.
However, Cho does not explicitly teach that two or three of the contact pads are respectively connected with two or more electrical connectors which are disposed in a symmetrical manner on lateral opposing sides of the first semiconductor transistor die.
However, St. Germain is a pertinent art that teaches that leads can be placed in any number and any location depending on a desired final configuration of a semiconductor package (see St. Germain ¶ [0094]). Further, it is known in the art that symmetric connecting conductors have the effect of cancelling out magnetic fluxes and reducing mutual inductance (see Hong ¶ [0056]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the number and location of Cho’s conductive vias connected to their terminal bond pads to be arranged symmetrically around Cho’s semiconductor dies according to the teaching of Hong (¶ [0056]) in order to cancel out magnetic flux and reduce mutual inductance.
Cited Prior Art
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant.
Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub No. 2020/0279785 by Faul discloses a semiconductor device.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub No. 2020/0219846 by Ji et al discloses a semiconductor device.
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/R.P.S./
Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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