DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/11/2026 has been entered.
Claim Objections
Claims 2-5, 7-8 are objected to because of the following informalities: Claim 2, lines 11-12 recites, “a resistor coupled between the second terminal of the circuitry and the fourth transistor control terminal” which lack antecedent basis for the recited “the fourth transistor” and should be corrected to read as “a resistor coupled between the second terminal of the circuitry and the third transistor control terminal”. Claims 3-5, 7-8 depend from Claim 2. Appropriate correction is required.
Claim 2, lines 13 recites, “a capacitor coupled between the fourth transistor control terminal and a ground terminal” which should be corrected to read as, “a capacitor coupled between the third transistor control terminal and a ground terminal”. Claims 3-5, 7-8 depend from Claim 2. Appropriate correction is required.
Examiner notes that the above correction is suggested as it appears that the lack of antecedent basis of the fourth transistor is resulting from the amendments that included renaming of the transistors.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 22-23 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 22 recites the limitations "the circuitry", “the switch” in line 1, “the third transistor”, “the resistor”, “the capacitor” in line 2. There is insufficient antecedent basis for these limitations in the claim. Claim 23 depend from Claim 22, therefore rejected due to dependency to a rejected claim.
Claim 22 recites, the first transistor and the second transistor are “ part of a clamp circuit”. It is indefinite, whether the recited clamp circuit is a different one than that of the parent claim. Claim 23 depend from Claim 22, therefore rejected due to dependency to a rejected claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 6, 9, 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Takemae (US 2012/0268091) in view of Teggatz et al. (US 6,169,439).
Takemae discloses a circuit comprising:
a first driver circuit having a first driver input and a first driver output (NOR, INV1 with input PWM and output OUT1, Figure 5);
a second driver circuit having a second driver input and a second driver output, wherein the second driver input is coupled to the first driver input (NAND, INV3, INV2 with input PWM and output OUT2, Figure 5), the first and second driver circuits configurable to set, respectively, the first and second driver output at a same logic state responsive to a state of the first driver input (Figure 5. Paragraph 46, “the control signal PWM is at L level and the first node SW is at H level, so that the output N3 of the inverter INV3 is at L level, the NAND output N2 is at H level, and the output G2 of the inverter INV2 is at L level. Further, the NOR output N1 is at H level, and the output G1 of the inverter INV1 is also at L level”);
a first transistor coupled between a switching terminal and a ground terminal (Q1 coupled between SW and VSS terminals), the first transistor having a first transistor control terminal coupled to the first driver output (Q1 having gate terminal couped to OUT1);
a second transistor coupled between the switching terminal and the ground terminal (Q2 coupled between SW and VSS terminals), the second transistor having a second transistor control terminal coupled to the second driver output (Q2 having a gate terminal coupled to OUT2); and
a clamp circuit coupled to the switching terminal (INV3 coupled to SW, Figures 5-6).
Takemae does not disclose a clamp circuit coupled between the switching terminal and the second transistor control terminal, the clamp circuit configurable to, responsive to a ringing event at the switching terminal, turn on the second transistor when the first driver circuit turns off the first transistor.
Teggatz discloses a circuit (100, Figure 1) comprising:
a clamp circuit coupled between the switching terminal and a second transistor control terminal (comprising 105 coupled between ILoad node and a transistor 102 gate terminal, Figure 1), the clamp circuit configurable to, responsive to a ringing event at the switching terminal, turn on the second transistor when the first driver circuit turns off the first transistor (Figure 1, Abstract, “drain-gate clamp circuit (105)..”). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide in the circuit of Takemae, a clamp circuit as taught by Teggatz, to have controllable/adjustable clamp threshold to control the second transistor.
Regarding Claim 6, combination of Takemae and Teggatz discloses the circuit of Claim 1, wherein the first driver circuit has a lower output current driving capability than the second driver circuit (Takemae, first driver circuit controlling the first transistor G1 having lower current output than the second driver circuit driving second transistor Q2 having high current output, Figures 5-6, Paragraph 34).
Regarding Claim 9, combination of Takemae and Teggatz discloses the circuit of Claim 1, configured in step-down power supply embodiment, including a third driver circuit having a third driver output, and a third transistor having a third transistor control terminal coupled to the third driver output (Figure 8 having transistor Q3 with gate terminal coupled to a third drive signal G3). Combination of Takemae and Teggatz does not specifically disclose the step-up power supply in Figures 5-6 having the third driver circuit coupled between a power input and the switching terminal. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide in the combination, the third transistor configured as a high side transistor by coupling between the power input terminal and the switching terminal for alternative operation of the low-side/first and second (Q1, Q2 in Figures 5-6) and the high-side/third (Q3 in Figure 8 as a high side in Figures 5-6) transistors and having the flexibility to select the transistors having same characteristics (low on-resistance).
Regarding Claim 22, combination of Takemae and Teggatz discloses the circuit of Claim 1, wherein the circuitry, the switch, the first transistor, the second transistor, the third transistor, the resistor, and the capacitor are part of a clamp circuit configurable to clamp a voltage at the first terminal of the circuitry (Teggatz, 100 is a clamp circuit to clamp the voltage at the first terminal, Figure 1, Krabbenborg, part of clamp/ESD protection circuit to clamp voltage at the first ternal, VDD, Figures 6-8).
Regarding Claim 23, combination of Takemae and Teggatz discloses the circuit of Claim 22, further comprising a fourth transistor coupled between the first terminal of the circuitry and the ground terminal (Teggatz, comprising 101, Figure 1), the fourth transistor having a fourth control terminal coupled to the second driver output (second driver output of 103 coupled to the gate of 101, Figure 1), wherein the clamp circuit is enabled responsive to at least one of. the fourth transistor being enabled by the first driver circuit, or a voltage between the first and second terminals of the circuitry exceeding the threshold (Teggatz, clamp circuit is enabled in responsive to the switching state of 101, Figure 1).
Claims 15-21 are rejected under 35 U.S.C. 103 as being unpatentable over Teggatz et al. (US 6,169,439) in view of Roewe et al. (US 2015/0097613) and Krabbenborg et al. (US 8,077,440).
Regarding Claim 15, Teggatz discloses a circuit (Figure 1) comprising:
a low-side transistor coupled between a switching terminal and a ground terminal, and having a low-side control terminal (comprising 101 coupled between a switching terminal/node at ILoad and ground terminal and having control/gate terminal, Figure 1); and
circuitry having a first terminal and a second terminal, the first terminal coupled to the switching terminal, the circuitry configurable to conduct a current responsive to a voltage between the first and second terminals exceeding a threshold (comprising part of 105 having a first terminal connected at ILoad node and a second termina connected to 115, 110, Figure 1);
a switch having first and second switch terminals and a switch control terminal, wherein the first switch terminal is coupled to the switching terminal (comprising 102 having drain, source and control/gate terminals and coupled between the threshold output and the ground terminal and the first switch termina/drain terminal coupled to the switching terminal at ILoad, Figure 1);
a first driver circuit having a first driver input and a first driver output (comprising 103 having a first driver input and a first driver output coupled to the gate of 102, Figure 1), the first driver circuit having a second driver output and coupled to the low-side control terminal (a second driver output/output of 103 coupled to a gate of transistor 101, Figure 1); and
a transistor coupled between the switch control terminal and the ground terminal and having a first control terminal (comprising 113 coupled between the switching terminal via the circuitry and the ground terminal and having a first control/gate terminal, Figure 1), wherein the first control terminal is coupled to the second switch terminal (control/gate terminal of 113 is coupled to the ground/second switch terminal, Figure 1).
Teggatz also discloses additional transistors coupled to the switch, the circuitry and ground (transistors 111, 112, 108, Figure 1).
Teggatz does not specifically disclose a high-side transistor coupled between a power supply input and the switching terminal, and having a high-side control terminal, a second driver circuit having a second driver input and the second driver output, wherein the second driver input is coupled to the first driver input, and the transistor being coupled between the switching terminal and the ground terminal, wherein the first control terminal is coupled to the first driver output, in which at least one of the first driver circuit or the switch is configurable to set a state of the first control terminal.
Roewe discloses a circuit (Figures 3-4) comprising:
a high-side transistor coupled between a power supply input and a switching terminal, and having a high-side control terminal (comprising 32 coupled between power supply input at 50 and switching terminal 52, Figure 4);
a low-side transistor coupled between a switching terminal and a ground terminal, and having a low-side control terminal (comprising 30 coupled between the switching terminal 52 and ground terminal at 54 and having control/gate terminal, Figure 4);
a circuitry having a first terminal and a second terminal, the first terminal coupled to the switching terminal, the circuitry configurable to conduct a current responsive to a voltage between the first and second terminals exceeding a threshold (threshold circuit comprising 36 with a first terminal at 52 and a second terminal at 66, Figures 3-4);
a switch having first and second switch terminals and a switch control terminal, wherein the first switch terminal is coupled to switching terminal (comprising 34 having source terminal, a drain terminal and a control/gate terminal, and the drain terminal coupled to 52 via 36, Figures 3-4);
first driver circuit having a first driver input and a first driver output (driver circuit in 40 outputting drive signal 60, Figures 3-4);
a second driver circuit having a second driver input and a second driver output (driver circuit in 40 that output drive signal 64 to low-side transistor 30, Figures 3-4), wherein the second driver input is coupled to the first driver input, and the second driver output is coupled to the low-side control terminal (both drive circuit receive same driver input signal/input signal 16, output drive signal 64 to low-side transistor 30, Figures 3-4), and an additional/third driver circuit having a third driver input and a third driver output (driver circuit in 80 that output drive signal 72 to high-side transistor 32, Figure 3).
Krabbenborg discloses a circuit (Figures 6-8) comprising:
circuitry having a first terminal and a second terminal, the circuitry configurable to conduct a current responsive to a voltage between the first and second terminals exceeding a threshold (comprising Z3, Z5 having a first terminal at VDD and a second terminal at S, source of transistor MPA, Figure 6);
a switch (comprising MNA, Figure 6) having first and second switch terminals and a switch control terminal, wherein the first switch terminal is coupled to the first terminal of the circuitry (MNA having source terminal, a drain terminal and a control/gate terminal, and the drain terminal coupled to input to the first terminal at VDD, Figures 6-8);
a transistor (comprising MP, Figure 6) coupled between the first terminal of the circuitry and the ground terminal and having a first control terminal (comprising transistor MP coupled between the threshold input VDD and ground terminal VSS and a third control/gate terminal, Figures 6-8), wherein the first control terminal is coupled to the second switch terminal (control/gate terminal of MP coupled to the second switch terminal S via Z1, Z4, Figures 6-8), in which the switch is configurable to set a state of the first control terminal (the conducting/non-conducting state of the switch MNA configurable to set the state of the third control terminal, Figures 6-8).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide in the drive circuit of Teggatz, a high-side transistor and a second driver as taught by Roewe, to operate as a half-bridge drive circuit and to have dedicated drive circuit for at least two different elements of the drive circuit to increase controllability and efficiency of the drive circuit and to provide a transistor having the control terminal configured as taught by Krabbenborg.to increase the controllability and strength of the circuit.
Regarding Claim 16, combination of Teggatz, Roewe and Krabbenborg discloses the circuit of Claim 15, wherein the transistor is a first transistor, and the circuit is further comprising: a second transistor coupled between the second terminal of the circuitry and the switch control terminal, and having a second control terminal (Teggatz, comprising 111 coupled between the threshold output and the ground terminal via 112 and having a second control/gate terminal, Figure 1, Krabbenborg, MPA coupled between the second terminal at S and the control/gate terminal of MD and having switch control/gate terminal, Figure 6);
a resistor coupled between the second terminal of the circuitry and the second control terminal (Teggatz, resistor similar to resistor 107 recited in Column 5, lines 26-35 in place of the Zener diode in Figure 1); a capacitance coupled between the second control terminal and the ground terminal (Teggatz, comprising gate to source capacitance of 111 and capacitance of 112, Figure 1); and a third transistor coupled between the second control terminal and the ground terminal, and having a third control terminal (comprising 113 coupled between the gate terminal of 111 and ground terminal via 108, Figure 1, Krabbenborg, MD coupled between a drain terminal of MPA and to ground terminal, and MD having a control/gate terminal, Figures 6-8).
Regarding Claim 17, combination of Teggatz, Roewe and Krabbenborg discloses the circuit of Claim 15, further comprising a third driver circuit having a third driver input and a third driver output (Roewe, third driver in 80 with output driver output to high-side transistor 32, Figure 4).
Regarding Claim 18, combination of Teggatz, Roewe and Krabbenborg discloses the circuit of Claim 16, wherein the switch includes: a fourth transistor having first and second current terminals and a fourth control terminal (NMOS transistor 102 having first current/source and second current/drain terminal and fourth control/gate terminal, Figure 1), wherein the first current terminal is coupled to the switching terminal (Teggatz, drain terminal coupled to the threshold input, Figure 1), and the fourth control terminal is coupled to the second transistor (Teggatz, gate of 102 coupled to the gate of 111, Figure 1), and
a fifth transistor having third and fourth current terminals and a fifth control terminal (Teggatz, comprising 108 having third current/emitter terminal and fourth current/collector terminal and a fifth control/base terminal, Figure 1), wherein the third current terminal is coupled to the second current terminal (Teggatz, third current/emitter terminal of 108 is coupled to the second current/source terminal of 102, Figure 1), the fourth current terminal is coupled to the third control terminal (Teggatz, collector/fourth current terminal of 108 coupled to the third control/gate terminal of 113 via its connection to the drain terminal of 113, Figure 1), and the fifth control terminal is coupled to the fourth control terminal (Teggatz, the fifth control/base terminal of 108 is coupled to the fourth control/gate terminal of 102 via it connection to the source terminal of 102, Figure 1).
Regarding Claim 19, combination of Teggatz, Roewe and Krabbenborg discloses the circuit of Claim 18, wherein the resistor is a first resistor (resistor similar to resistor 107 recited in Column 5, lines 26-35 in place of the Zener diode in Figure 1), and the circuit is further comprising a second resistor coupled between the fifth control terminal and the ground terminal (Teggatz, comprising 107, Figure 1). Combination of Teggatz, Roewe and Krabbenborg does not specifically disclose a second resistor coupled between the fourth control terminal and the ground terminal. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide in the combination additional resistor/a second resistor coupled between the fourth control terminal and the ground terminal to have a current limiting gate discharge path for the fourth transistor.
Regarding Claim 20, combination of Teggatz, Roewe and Krabbenborg discloses the circuit of Claim 15, wherein the circuitry includes a zener diode (Zener diode/s in 105, Figure 1).
Regarding Claim 21, combination of Teggatz, Roewe and Krabbenborg discloses the circuit of Claim 17, wherein the first driver circuit has a lower output current driving capability than the second driver circuit (Roewe, first driver circuit controlling a switch/transistor in the clamp circuit having/requiring lower output driving capability than the second driver circuit driving low-ide switching transistor 30 in the load path, Figures 3-4).
Allowable Subject Matter
Claims 2-5, 7-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Regarding Claim 2, combination of Takemae and Teggatz discloses the circuit of Claim 1,
a circuitry having a first terminal and a second terminal, the firs terminal coupled to the switching terminal, the circuitry configurable to conduct a current responsive to a voltage between the first and second terminals exceeding a threshold (comprising part of 105 having a first terminal connected at ILoad node and a second termina connected to 115, 110, Figure 1, Abstract, “drain-gate clamp circuit ...”));
a switch having first and second switch terminals and a switch control terminal, wherein the second switch terminal coupled to the second transistor control terminal (comprising 113 having source and drain terminal and gate/control terminal, wherein the source terminal is coupled to the second transistor control terminal, Figure 1);
a third transistor coupled between the second terminal of the circuitry and the switch control terminal, and having a third transistor control terminal coupled to the second transistor control terminal (comprising 111 coupled between the threshold output in 105 and the switch 113 gate terminal and third transistor 111 control/gate terminal coupled to second transistor 102 control terminal, Figure 1);
a resistor coupled between the second terminal of the circuitry and the first control terminal (resistor similar to resistor 107 recited in Column 5, lines 26-35 in place of the Zener diode coupled to the gate of 111 in Figure 1);
a fourth transistor (comprising 112, Figure 1) coupled between the third transistor and the ground terminal, and having a fourth transistor control terminal (112 coupled between 111 and ground terminal, and 112 having a control/gate terminal coupled to the second transistor control terminal via 113, Figure 1);
Combination of Takemae and Teggatz does not disclose the first switch terminal is coupled to the first terminal of the circuitry, a capacitor coupled between the third transistor control terminal and a ground terminal, and the fourth transistor control terminal (directly) coupled to the second transistor control terminal.
Gao et al. (US 10,298,215) discloses a voltage clamping circuit (Figures 1-4) comprising: a circuitry having an input coupled to a switching terminal and having an output (comprising 102, 108 having a threshold input at 22 and threshold output at 112, Figures 3-4),
a third transistor coupled between the output of the circuitry and a second transistor control terminal and having a third transistor control terminal (comprising 106 coupled between 112 and 38 and having switch control terminal 114, Figures 3-4);
a resistor coupled between the output of the circuitry and the third transistor control terminal (comprising 116 coupled between 112 and 114, Figures 3-4);
a capacitance coupled between the third transistor control terminal and a ground terminal (capacitance of Zener diode 118 coupled between 114 and 24, Figure 4); and a fourth transistor coupled to the ground terminal and having a third control terminal (comprising 204, Figure 4).
Combination of Takemae, Teggatz and Gao does not disclose the first switch terminal is coupled to the first terminal of the circuitry, a capacitor coupled between the third transistor control terminal and a ground terminal, and the fourth transistor control terminal coupled to the second transistor control terminal, in combination with the other recited elements of Claim 2, and would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and upon overcoming the claim objections above. Claims 3-5, 7-8 depend from Claim 2 and are objected due to dependency to an objected claim.
Response to Arguments
Applicant's arguments filed on 1/02/2026 have been fully considered but they are not persuasive and/or rendered moot in view of new grounds of rejection addressing the amended and/or new limitations.
Applicant's arguments, on Page 7 of the Remarks toward Claim 1 and the combination of Teggatz, Krabbenborg and Roewe and dependent Claims 6, 9, 22-23 are rendered moot in view of new grounds of rejection (newly found reference Takemae is used as the primary reference in combination with Teggatz to reject independent claim 1).
Applicant's arguments, toward dependent Claims 2-5, 7-8 are rendered moot as the claims are objected in the current rejection.
Regarding Applicant’s arguments, on Page 8 of the Remarks that Claim 15 and the primary reference Teggatz and element 113 relied upon for the claimed switch, examiner respectfully notes that Claim 15 is rejected using the combination of Teggatz, Roewe and Krabbenborg, for the teaching of the missing limitations in Teggatz including the argued upon limitations.
Regarding Applicant’s arguments, on Page 8 of the Remarks toward the limitation of the at least one of the first driver circuit or the switch is configurable to set a state of the first control terminal, examiner respectfully notes that Krabbenborg discloses transistor MP and switch MNA in Figure 6 wherein the conducting/non-conducting state of the switch MNA is configurable to set the state of the third control terminal in the combination.
It is further respectfully notes that Teggatz discloses in Column 5, lines 55-64, the switch 113 being turned off to disable the current limit circuit 108, thereby setting a state of the first control terminal.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Hoya (US 11,606,090) discloses a voltage clamping circuit (Figures 1-8B) comprising: a threshold-setting circuit having a threshold input and a threshold output (comprising 60a, Figure 1B, comprising Zener diode in 60, Figures 3A-3D, 4A-4B); a first driver circuit having a first driver input and a first driver output (comprising 10a having a first driver input IN(HU) and a first driver output OUT, Figure 1B); a second driver circuit having a second driver input and a second driver output (comprising 10b having a second driver input IN(LU)) and second driver output UOUT, Figure 1B), wherein the second driver input is coupled to the first driver input (IN(HU) and IN(LU) coupled via MPU 110, Figure 1B);
Adams (US 2005/0140420) discloses a voltage clamping circuit (Figures 1-3) comprising: a threshold-setting circuit having a threshold input and a threshold output (comprising 212-228 having a threshold input at 210 and threshold output at 230, Figure 2); a switch having first and second switch terminals and a switch control terminal, wherein the first switch terminal is coupled to the threshold input (comprising 206 having source and drain terminal and control terminal coupled to 246, Figure 2); a first transistor coupled between the threshold output and the switch control terminal , and having a first control terminal (comprising 240 coupled between 230 and 246 and a first control terminal 238, Figure 2); a resistor coupled between the threshold output and the first control terminal (comprising 236 coupled between 230 and 238, Figure 2); a second transistor (comprising 293, 296, Figure 2) coupled between the first control terminal and the ground terminal, and having a second control terminal (293, 296 coupled between 246 and PGND, 208 and having a control/gate terminal 297, Figure 2); .
Parthasarathy et al. (US 10,581,423) discloses a voltage clamping circuit (Figures 1-14, 100, Figure 3) comprising: a threshold-setting circuit having a threshold input and a threshold output (comprising 31, 32, Figure 3); a switch having first and second switch terminals and a switch control terminal, wherein the first switch terminal is coupled to the threshold input (comprising 33, 34 having source terminal, a drain terminal and a control/gate terminal, and the drain terminal coupled to input to an output of 31,32, Figure 3); a first transistor coupled between the threshold output and a switch terminal and having a first switch control terminal (comprising 34 coupled between the threshold output and a switch terminal of transistor 81,46, Figure 3); a resistor coupled between the threshold output and the first control terminal (comprising resistor 88 coupled to the threshold output and the first control/gate terminal of 34, Figure 3); a capacitor coupled to the first control terminal and a ground terminal (comprising 74 coupled to the gate terminal of 34 and ground, Figure 3).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LUCY M THOMAS whose telephone number is (571)272-6002. The examiner can normally be reached Mon-Fri 9:30 am - 5:30 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal L Hammond can be reached at (571)270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LUCY M THOMAS/ Examiner, Art Unit 2838, 5/21/2026
/CRYSTAL L HAMMOND/ Supervisory Primary Examiner, Art Unit 2838
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