DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-9, 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Teggatz et al. (US 6,169,439) in view of Krabbenborg et al. (US 8,077,440) and Roewe et al. (US 2015/0097613).
Regarding Claim 1, Teggatz discloses a circuit (100, Figure 1) comprising:
a circuitry having a first terminal and a second terminal, the circuitry configurable to conduct a current responsive to a voltage between the first and second terminals exceeding a threshold (comprising part of 105 having a first terminal connected at ILoad node and a second termina connected to 115, 110, Figure 1);
a switch having first and second switch terminals and a switch control terminal, wherein the first switch terminal is coupled to the first terminal of the circuitry (comprising 102 having source and drain terminal and control terminal, wherein the drain/first switch terminal is coupled to the first terminal of the circuitry, Figure 1);
a first transistor coupled between the second terminal of the circuitry and the switch control terminal, and having a first control terminal (comprising 111 coupled between the threshold output and the switch control/gate terminal, and a first control/gate terminal, Figure 1);
a resistor coupled between the second terminal of the circuitry and the first control terminal (resistor similar to resistor 107 recited in Column 5, lines 26-35 in place of the Zener diode coupled to the gate of 111 in Figure 1);
a capacitance coupled between the first control terminal and a ground terminal (comprising gate to source capacitance of 111 and capacitance of 112, Figure 1);
a second transistor (comprising 113, Figure 1) coupled between the first control terminal and the ground terminal, and having a second control terminal (113 coupled between the gate/first control terminal of 111 and ground terminal, and 113 having a control/gate terminal, Figure 1);
a first driver circuit having a first driver input and a first driver output (comprising 103 having a first driver input and a first driver output coupled to the gate of 102, Figure 1), the first driver circuit having a second driver output (a second driver output/output of 103 coupled to a gate of the switch 102, Figure 1).
Teggatz also discloses additional transistors and an additional resistor coupled to the switch, first and second transistors and ground, and resistor (transistors 112, 108 and resistor 107, Figure 1).
Teggatz does not disclose a capacitor coupled between the first control terminal and a ground terminal, a second driver circuit having a second driver input and the second driver output, wherein the second driver input is coupled to the first driver input, and a third transistor coupled between the first terminal of the circuitry and the ground terminal and having a third control terminal, wherein the third control terminal is coupled to the first driver output in which at least one of the first driver circuit or the switch is configurable to set a state of the third control terminal.
Krabbenborg discloses the missing limitation of the third control terminal being coupled to the second control terminal and the second switch terminal as discussed in detail below.
Krabbenborg discloses a circuit (Figures 6-8) comprising:
circuitry having a first terminal and a second terminal, the circuitry configurable to conduct a current responsive to a voltage between the first and second terminals exceeding a threshold (comprising Z3, Z5 having a first terminal at VDD and a second terminal at S, source of transistor MPA, Figure 6);
a switch (comprising MNA, Figure 6) having first and second switch terminals and a switch control terminal, wherein the first switch terminal is coupled to the first terminal of the circuitry (MNA having source terminal, a drain terminal and a control/gate terminal, and the drain terminal coupled to input to the first terminal at VDD, Figures 6-8);
a first transistor (comprising MPA, Figure 6) coupled between the second terminal and the switch control terminal and having a first switch control terminal of the circuitry (MPA coupled between the second terminal at S and the control/gate terminal of MD and having switch control/gate terminal, Figure 6);
a capacitance coupled between the first control terminal and a ground terminal (capacitance of diode D2 between gate of MPA and ground/VSS, Figure 6);
a second transistor (comprising MD, Figures 6-8) coupled to a terminal of the first transistor and the ground terminal, and having a second control terminal (MD coupled between a drain terminal of MPA and to ground terminal, and MD having a control/gate terminal, Figures 6-8); and
a third transistor (comprising MP, Figure 6) coupled between the first terminal of the circuitry and the ground terminal and having a third control terminal (comprising transistor MP coupled between the threshold input VDD and ground terminal VSS and a third control/gate terminal, Figures 6-8), wherein the third control terminal is coupled to the second control terminal and the second switch terminal (second control/gate terminal of MPA is coupled to the third control/gate terminal of MP and the second switch terminal S via Z1, Z4, Figures 6-8), in which the switch is configurable to set a state of the third control terminal (the conducting/non-conducting state of the switch MNA configurable to set the state of the third control terminal, Figures 6-8).
Roewe discloses a circuit (Figures 3-4) comprising:
a switch having first and second switch terminals and a switch control terminal, wherein the first switch terminal is coupled to a threshold input (comprising 34 having source terminal, a drain terminal and a control/gate terminal, and the drain terminal coupled to input to a threshold input 52, Figures 3-4);
first driver circuit having a first driver input and a first driver output (driver circuit in 40 outputting drive signal 60, Figures 3-4); a second driver circuit having a second driver input and a second driver output (driver circuit in 40 that output drive signal 64 to low-side transistor 30, Figures 3-4), wherein the second driver input is coupled to the first driver input (both drive circuit receive same driver input signal/input signal 16, Figures 3-4), and an additional/third driver circuit having a third driver input and a third driver output (driver circuit in 80 that output drive signal 72 to high-side transistor 32, Figure 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide in the circuit of Teggatz, a third transistor having the third control terminal configured as taught Krabbenborg, to increase the controllability and strength of the circuitry, to provide a capacitor to form a trigger circuit with the resistor to enhance switching/turn-on speed of the first transistor, and to provide a second driver circuit as taught by Roewe, to have dedicated drive circuit for at least two different elements of the drive circuit to increase controllability of the drive circuit.
Regarding Claim 2, combination of Teggatz, Krabbenborg, and Roewe discloses the voltage clamping circuit of Claim 1, further comprising a third driver circuit having a third driver input and a third driver output (Roewe, third driver in 80 with output driver output to high-side transistor 32, Figure 4).
Regarding Claim 3, combination of Teggatz, Krabbenborg, and Roewe discloses the circuit of Claim 1, wherein the switch includes: a fourth transistor having first and second current terminals and a fourth control terminal (NMOS transistor 102 having first current/source and second current/drain terminal and fourth control/gate terminal, Figure 1), wherein the first current terminal is coupled to the threshold input (Teggatz, drain terminal of 101 coupled to the first terminal, Figure 1), and the fourth control terminal is coupled to the first transistor (Teggatz, gate of 102 coupled to the gate of 111, Figure 1), and
a fifth transistor having third and fourth current terminals and a fifth control terminal (Teggatz, comprising 108 having third current/emitter terminal and fourth current/collector terminal and a fifth control/base terminal, Figure 1), wherein the third current terminal is coupled to the second current terminal (Teggatz, third current/emitter terminal of 108 is coupled to the second current/source terminal of 102, Figure 1), the fourth current terminal is coupled to the third control terminal (Teggatz, collector/fourth current terminal of 108 coupled to the third control/gate terminal of 113 via its connection to the drain terminal of 113, Figure 1), and the fifth control terminal is coupled to the fourth control terminal (Teggatz, the fifth control/base terminal of 108 is coupled to the fourth control/gate terminal of 102 via it connection to the source terminal of 101, Figure 1).
Regarding Claim 4, combination of Teggatz, Krabbenborg, and Roewe discloses the voltage clamping circuit of Claim 3, wherein the resistor is a first resistor (resistor similar to resistor 107 in place of the Zener diode in Figure 1, Column 5, lines 26-35), and the voltage clamping circuit is further comprising a second resistor coupled between the fifth control terminal and the ground terminal (Teggatz, comprising 107, Figure 1). Combination of Teggatz, Krabbenborg, and Roewe does not specifically disclose a second resistor coupled between the fourth control terminal and the ground terminal. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide in the combination additional resistor/a second resistor coupled between the fourth control terminal and the ground terminal to have a current limiting gate discharge path for the fourth transistor.
Regarding Claim 5, combination of Teggatz, Krabbenborg, and Roewe discloses the circuit of Claim 1, wherein the threshold-setting circuit includes a zener diode (Teggatz, Zener diode in 105 in Figure 1, Krabbenborg, Z3, Z5 in Figures 6-8).
Regarding Claim 6, combination of Teggatz, Krabbenborg, and Roewe discloses the circuit of Claim 1, wherein the first driver circuit has a lower output current driving capability than the second driver circuit (Roewe, first driver circuit controlling a switch/transistor in the clamp circuit having/requiring lower output driving capability than the second driver circuit driving low-ide switching transistor 30 in the load path, Figures 3-4).
Regarding Claim 7, combination of Teggatz, Krabbenborg, and Roewe discloses the circuit of Claim 2, wherein the first driver circuit has a lower output current driving capability than the second driver circuit and the third driver circuit (Roewe, first driver circuit controlling a switch/transistor in the clamp circuit having/requiring lower output driving capability than the second driver circuit and third driver circuit driving switching transistors 30, 32 in the load path, Figure 4).
Regarding Claim 8, combination of Teggatz, Krabbenborg, and Roewe discloses the circuit of Claim 1, wherein the first transistor is a p-channel field effect transistor (PFET), and the second and third transistors are each n-channel field effect transistors (NFETs) (Krabbenborg, PFET MPA and NFETs MD and MP in Figures 6-8).
Regarding Claim 9, combination of Teggatz, Krabbenborg, and Roewe discloses the circuit of Claim 1, wherein a signal at the threshold input includes a ringing voltage (signal at the threshold input being the voltage at the drain terminal of load driving/switching MOSFET transistor 101in Figure 1 includes ringing due to voltage stress).
Claims 15-21 are rejected under 35 U.S.C. 103 as being unpatentable over Teggatz et al. (US 6,169,439) in view of Roewe et al. (US 2015/0097613) and Krabbenborg et al. (US 8,077,440).
Regarding Claim 15, Teggatz discloses a circuit (Figure 1) comprising:
a low-side transistor coupled between a switching terminal and a ground terminal, and having a low-side control terminal (comprising 101 coupled between a switching terminal/node at ILoad and ground terminal and having control/gate terminal, Figure 1); and
circuitry having a first terminal and a second terminal, the first terminal coupled to the switching terminal, the circuitry configurable to conduct a current responsive to a voltage between the first and second terminals exceeding a threshold (comprising part of 105 having a first terminal connected at ILoad node and a second termina connected to 115, 110, Figure 1);
a switch having first and second switch terminals and a switch control terminal, wherein the first switch terminal is coupled to the switching terminal (comprising 102 having drain, source and control/gate terminals and coupled between the threshold output and the ground terminal and the first switch termina/drain terminal coupled to the switching terminal at ILoad, Figure 1);
a first driver circuit having a first driver input and a first driver output (comprising 103 having a first driver input and a first driver output coupled to the gate of 102, Figure 1), the first driver circuit having a second driver output and coupled to the low-side control terminal (a second driver output/output of 103 coupled to a gate of transistor 101, Figure 1); and
a transistor coupled between the switch control terminal and the ground terminal and having a first control terminal (comprising 113 coupled between the switching terminal via the circuitry and the ground terminal and having a first control/gate terminal, Figure 1), wherein the first control terminal is coupled to the second switch terminal (control/gate terminal of 113 is coupled to the ground/second switch terminal, Figure 1).
Teggatz also discloses additional transistors coupled to the switch, the circuitry and ground (transistors 111, 112, 108, Figure 1).
Teggatz does not specifically disclose a high-side transistor coupled between a power supply input and the switching terminal, and having a high-side control terminal, a second driver circuit having a second driver input and the second driver output, wherein the second driver input is coupled to the first driver input, and the transistor being coupled between the switching terminal and the ground terminal, wherein the first control terminal is coupled to the first driver output, in which at least one of the first driver circuit or the switch is configurable to set a state of the first control terminal.
Roewe discloses a circuit (Figures 3-4) comprising:
a high-side transistor coupled between a power supply input and a switching terminal, and having a high-side control terminal (comprising 32 coupled between power supply input at 50 and switching terminal 52, Figure 4);
a low-side transistor coupled between a switching terminal and a ground terminal, and having a low-side control terminal (comprising 30 coupled between the switching terminal 52 and ground terminal at 54 and having control/gate terminal, Figure 4);
a circuitry having a first terminal and a second terminal, the first terminal coupled to the switching terminal, the circuitry configurable to conduct a current responsive to a voltage between the first and second terminals exceeding a threshold (threshold circuit comprising 36 with a first terminal at 52 and a second terminal at 66, Figures 3-4);
a switch having first and second switch terminals and a switch control terminal, wherein the first switch terminal is coupled to switching terminal (comprising 34 having source terminal, a drain terminal and a control/gate terminal, and the drain terminal coupled to 52 via 36, Figures 3-4);
first driver circuit having a first driver input and a first driver output (driver circuit in 40 outputting drive signal 60, Figures 3-4);
a second driver circuit having a second driver input and a second driver output (driver circuit in 40 that output drive signal 64 to low-side transistor 30, Figures 3-4), wherein the second driver input is coupled to the first driver input, and the second driver output is coupled to the low-side control terminal (both drive circuit receive same driver input signal/input signal 16, output drive signal 64 to low-side transistor 30, Figures 3-4), and an additional/third driver circuit having a third driver input and a third driver output (driver circuit in 80 that output drive signal 72 to high-side transistor 32, Figure 3).
Krabbenborg discloses a circuit (Figures 6-8) comprising:
circuitry having a first terminal and a second terminal, the circuitry configurable to conduct a current responsive to a voltage between the first and second terminals exceeding a threshold (comprising Z3, Z5 having a first terminal at VDD and a second terminal at S, source of transistor MPA, Figure 6);
a switch (comprising MNA, Figure 6) having first and second switch terminals and a switch control terminal, wherein the first switch terminal is coupled to the first terminal of the circuitry (MNA having source terminal, a drain terminal and a control/gate terminal, and the drain terminal coupled to input to the first terminal at VDD, Figures 6-8);
a transistor (comprising MP, Figure 6) coupled between the first terminal of the circuitry and the ground terminal and having a first control terminal (comprising transistor MP coupled between the threshold input VDD and ground terminal VSS and a third control/gate terminal, Figures 6-8), wherein the first control terminal is coupled to the second switch terminal (control/gate terminal of MP coupled to the second switch terminal S via Z1, Z4, Figures 6-8), in which the switch is configurable to set a state of the first control terminal (the conducting/non-conducting state of the switch MNA configurable to set the state of the third control terminal, Figures 6-8).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide in the drive circuit of Teggatz, a high-side transistor and a second driver as taught by Roewe, to operate as a half-bridge drive circuit and to have dedicated drive circuit for at least two different elements of the drive circuit to increase controllability and efficiency of the drive circuit and to provide a transistor having the control terminal configured as taught by Krabbenborg.to increase the controllability and strength of the circuit.
Regarding Claim 16, combination of Teggatz, Roewe and Krabbenborg discloses the circuit of Claim 15, wherein the transistor is a first transistor, and the circuit is further comprising: a second transistor coupled between the second terminal of the circuitry and the switch control terminal, and having a second control terminal (Teggatz, comprising 111 coupled between the threshold output and the ground terminal via 112 and having a second control/gate terminal, Figure 1, Krabbenborg, MPA coupled between the second terminal at S and the control/gate terminal of MD and having switch control/gate terminal, Figure 6);
a resistor coupled between the second terminal of the circuitry and the second control terminal (Teggatz, resistor similar to resistor 107 recited in Column 5, lines 26-35 in place of the Zener diode in Figure 1); a capacitance coupled between the second control terminal and the ground terminal (Teggatz, comprising gate to source capacitance of 111 and capacitance of 112, Figure 1); and a third transistor coupled between the second control terminal and the ground terminal, and having a third control terminal (comprising 113 coupled between the gate terminal of 111 and ground terminal via 108, Figure 1, Krabbenborg, MD coupled between a drain terminal of MPA and to ground terminal, and MD having a control/gate terminal, Figures 6-8).
Regarding Claim 17, combination of Teggatz, Roewe and Krabbenborg discloses the circuit of Claim 15, further comprising a third driver circuit having a third driver input and a third driver output (Roewe, third driver in 80 with output driver output to high-side transistor 32, Figure 4).
Regarding Claim 18, combination of Teggatz, Roewe and Krabbenborg discloses the circuit of Claim 16, wherein the switch includes: a fourth transistor having first and second current terminals and a fourth control terminal (NMOS transistor 102 having first current/source and second current/drain terminal and fourth control/gate terminal, Figure 1), wherein the first current terminal is coupled to the switching terminal (Teggatz, drain terminal coupled to the threshold input, Figure 1), and the fourth control terminal is coupled to the second transistor (Teggatz, gate of 102 coupled to the gate of 111, Figure 1), and
a fifth transistor having third and fourth current terminals and a fifth control terminal (Teggatz, comprising 108 having third current/emitter terminal and fourth current/collector terminal and a fifth control/base terminal, Figure 1), wherein the third current terminal is coupled to the second current terminal (Teggatz, third current/emitter terminal of 108 is coupled to the second current/source terminal of 102, Figure 1), the fourth current terminal is coupled to the third control terminal (Teggatz, collector/fourth current terminal of 108 coupled to the third control/gate terminal of 113 via its connection to the drain terminal of 113, Figure 1), and the fifth control terminal is coupled to the fourth control terminal (Teggatz, the fifth control/base terminal of 108 is coupled to the fourth control/gate terminal of 102 via it connection to the source terminal of 102, Figure 1).
Regarding Claim 19, combination of Teggatz, Roewe and Krabbenborg discloses the circuit of Claim 18, wherein the resistor is a first resistor (resistor similar to resistor 107 recited in Column 5, lines 26-35 in place of the Zener diode in Figure 1), and the circuit is further comprising a second resistor coupled between the fifth control terminal and the ground terminal (Teggatz, comprising 107, Figure 1). Combination of Teggatz, Roewe and Krabbenborg does not specifically disclose a second resistor coupled between the fourth control terminal and the ground terminal. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide in the combination additional resistor/a second resistor coupled between the fourth control terminal and the ground terminal to have a current limiting gate discharge path for the fourth transistor.
Regarding Claim 20, combination of Teggatz, Roewe and Krabbenborg discloses the circuit of Claim 15, wherein the circuitry includes a zener diode (Zener diode/s in 105, Figure 1).
Regarding Claim 21, combination of Teggatz, Roewe and Krabbenborg discloses the circuit of Claim 17, wherein the first driver circuit has a lower output current driving capability than the second driver circuit (Roewe, first driver circuit controlling a switch/transistor in the clamp circuit having/requiring lower output driving capability than the second driver circuit driving low-ide switching transistor 30 in the load path, Figures 3-4).
Regarding Claim 22, combination of Teggatz, Roewe and Krabbenborg discloses the circuit of Claim 1, wherein the circuitry, the switch, the first transistor, the second transistor, the third transistor, the resistor, and the capacitor are part of a clamp circuit configurable to clamp a voltage at the first terminal of the circuitry (Teggatz, 100 is a clamp circuit to clamp the voltage at the first terminal, Figure 1, Krabbenborg, part of clamp/ESD protection circuit to clamp voltage at the first ternal, VDD, Figures 6-8).
Regarding Claim 23, combination of Teggatz, Roewe and Krabbenborg discloses the circuit of Claim 22, further comprising a fourth transistor coupled between the first terminal of the circuitry and the ground terminal (Teggatz, comprising 101, Figure 1), the fourth transistor having a fourth control terminal coupled to the second driver output (second driver output of 103 coupled to the gate of 101, Figure 1), wherein the clamp circuit is enabled responsive to at least one of. the fourth transistor being enabled by the first driver circuit, or a voltage between the first and second terminals of the circuitry exceeding the threshold (Teggatz, clamp circuit is enabled in responsive to the switching state of 101, Figure 1).
Response to Arguments
Applicant's arguments filed on 1/02/2026 have been fully considered but they are not persuasive and/or rendered moot in view of new grounds of rejection addressing the amended and/or new limitations.
Regarding Applicant’s arguments, on Page 7 of the Remarks toward new claims 22-23 directed toward the limitations of Claim 1, examiner respectfully notes that Applicant has not presented any arguments toward Claim 1 and notes that Claims 1-9 and new claims 22-23 are rejected using the same combination of references Teggatz, Krabbenborg, and Roewe.
Regarding Applicant’s arguments, on Page 6 of the Remarks that Claim 15 has been amended to overcome the claim objections, examiner respectfully notes that Claim 15 has been amended to broaden the claim by excluding the voltage clamping circuit, and amending threshold circuit to a circuitry, and further limiting the first control terminal coupled to the second switch terminal, in at least one of first driver circuit and or the switch is configurable to set a state of the first control termina, and thus amendments are more than just to overcome the claim objections.
Applicant’s arguments, on Page 6 of the Remarks toward Claim 15 and the new limitation of the at least one of the first driver circuit or the switch is configurable to set a state of the first control terminal, are rendered moot in view of the new grounds of rejection for Claim 15 including Krabbenborg reference as an additional secondary reference with primary reference Teggatz and secondary reference Roewe. Krabbenborg discloses transistor MP and switch MNA in Figure 6 wherein the conducting/non-conducting state of the switch MNA is configurable to set the state of the third control terminal in the combination.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Hoya (US 11,606,090) discloses a voltage clamping circuit (Figures 1-8B) comprising: a threshold-setting circuit having a threshold input and a threshold output (comprising 60a, Figure 1B, comprising Zener diode in 60, Figures 3A-3D, 4A-4B); a first driver circuit having a first driver input and a first driver output (comprising 10a having a first driver input IN(HU) and a first driver output OUT, Figure 1B); a second driver circuit having a second driver input and a second driver output (comprising 10b having a second driver input IN(LU)) and second driver output UOUT, Figure 1B), wherein the second driver input is coupled to the first driver input (IN(HU) and IN(LU) coupled via MPU 110, Figure 1B);
Adams (US 2005/0140420) discloses a voltage clamping circuit (Figures 1-3) comprising: a threshold-setting circuit having a threshold input and a threshold output (comprising 212-228 having a threshold input at 210 and threshold output at 230, Figure 2); a switch having first and second switch terminals and a switch control terminal, wherein the first switch terminal is coupled to the threshold input (comprising 206 having source and drain terminal and control terminal coupled to 246, Figure 2); a first transistor coupled between the threshold output and the switch control terminal , and having a first control terminal (comprising 240 coupled between 230 and 246 and a first control terminal 238, Figure 2); a resistor coupled between the threshold output and the first control terminal (comprising 236 coupled between 230 and 238, Figure 2); a second transistor (comprising 293, 296, Figure 2) coupled between the first control terminal and the ground terminal, and having a second control terminal (293, 296 coupled between 246 and PGND, 208 and having a control/gate terminal 297, Figure 2); .
Gao et al. (US 10,298,215) discloses a voltage clamping circuit (Figures 1-4) comprising: a threshold-setting circuit having a threshold input and a threshold output (comprising 102, 108 having a threshold input at 22 and threshold output at 112, Figures 3-4); a switch having first and second switch terminals and a switch control terminal, wherein the first switch terminal is coupled to the threshold input (comprising 36 having source terminal 42 coupled to ground 24, a drain terminal 40 coupled to 22 and a control terminal 38, and the drain terminal 40 coupled to input to 108 at 22, Figures 3-4); a first transistor coupled between the threshold output and the switch control terminal and having a first switch control terminal (comprising 106 coupled between 112 and 38 and having switch control terminal 114, Figures 3-4); a resistor coupled between the threshold output and the first control terminal (comprising 116 coupled between 112 and 114, Figures 3-4); a second transistor (comprising 204, Figure 4) coupled between the switch control terminal and the ground terminal, and having a second control terminal (204 coupled between 38 and 24, 208 and having a second control terminal 206, Figure 206, Figure 4); a capacitance coupled between the first control terminal and a ground terminal (capacitance of Zener diode 118 coupled between 114 and 24, Figure 4); and a third transistor coupled to the ground terminal and having a third control terminal (comprising 204, Figure 4);
Parthasarathy et al. (US 10,581,423) discloses a voltage clamping circuit (Figures 1-14, 100, Figure 3) comprising: a threshold-setting circuit having a threshold input and a threshold output (comprising 31, 32, Figure 3); a switch having first and second switch terminals and a switch control terminal, wherein the first switch terminal is coupled to the threshold input (comprising 33, 34 having source terminal, a drain terminal and a control/gate terminal, and the drain terminal coupled to input to an output of 31,32, Figure 3); a first transistor coupled between the threshold output and a switch terminal and having a first switch control terminal (comprising 34 coupled between the threshold output and a switch terminal of transistor 81,46, Figure 3); a resistor coupled between the threshold output and the first control terminal (comprising resistor 88 coupled to the threshold output and the first control/gate terminal of 34, Figure 3); a capacitor coupled to the first control terminal and a ground terminal (comprising 74 coupled to the gate terminal of 34 and ground, Figure 3).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LUCY M THOMAS whose telephone number is (571)272-6002. The examiner can normally be reached Mon-Fri 9:30 am - 5:30 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal L Hammond can be reached at (571)270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LUCY M THOMAS/ Examiner, Art Unit 2838, 2/02/2026
/CRYSTAL L HAMMOND/Supervisory Primary Examiner, Art Unit 2838