DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 14-15, 18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Toumiya (US 6751767).
As to claim 14, Toumiya discloses a data storage device (fig. 1), comprising:
a memory device (“circuit information”, “pattern information”); and
a controller (“local CPU”) coupled to the memory device, wherein the controller is configured to:
generate one or more dummy packets for a first function (fig. 3 s1, S6, S9);
transmit the one or more dummy packets (s2, s5, s7) over an interface (col 11 ln 25-30) to a host device (fig. 4, remote CPU#1);
reroute the one or more dummy packets to a second function (fig. 4, to remote CPU#2); and
measure attributes of the one or more dummy packets (fig. 3 S15 “determines whether the merged pattern information satisfies”).
As to claim 15, Toumiya discloses the data storage device of claim 14, wherein the attributes are selected from the group consisting of latency, performance (col 14 ln 1-5 “fault detection performance”), and combinations thereof.
As to claim 18, Toumiya discloses a data storage device (fig. 1), comprising:
means to store data (“circuit information”, “pattern information”); and
a controller (“local CPU”) coupled to the means to store data, wherein the controller is configured to:
generate regular host traffic and internal events for a first function (fig. 3 s1, S6, S9);
transmit the regular host traffic and internal events (s2, s5, s7) over an interface (col 11 ln 25-30) to a host device (fig. 4, remote CPU#1); and
route the internal events to a second function (to remote CPU#2).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6, 7, 9, 13 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 20230189519, Kim) in view of Pico (US 20180188960).
As to claim 1, Kim discloses a data storage device (fig. 1, 2), comprising:
a memory device (NVM, memory 140); and
a controller coupled to the memory device (par. 47, controller 170), wherein the controller is configured to:
generate traffic towards a host device (par. 158 “perform a read operation on data stored in 140”);
active a direct memory access (DMA) module (par. 62 “execute flash translation layer 173 to control”);
determine that a packet should be drained (fig. 16, s230);
route a packet to a drain buffer (s262); and
drain the modified packet (s264-266).
Kim does not disclose the step of replace host address with a drain buffer address to create a modified packet. In the same field of art (data storage), Pico discloses an apparatus comprises a plurality of memory partitions (fig. 1). In one embodiment, Pico further discloses the step of replacing the address of the first partition with the address of the second partition which create a modified packet to route data to the second partition (par 75). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kim and Pico, by replacing host address with a drain buffer address to create a modified packet. The motivation is to improve the reliability of the system.
As to claim 2, Kim/Pico discloses the data storage device of claim 1, wherein the controller is configured to send the modified packet to the host device prior to the routing (Kim, fig. 16. Note: The modified packet is sent to host device prior to routing because it is a result of a read command from host).
As to claim 3, Kim/Pico discloses the data storage device of claim 2, wherein the sending occurs over a peripheral component interconnect express (PCle) bus (Kim, par. 58; Pico, par. 20).
As to claim 6, Kim/Pico discloses the data storage device of claim 1, wherein the controller includes at least one of the following:
one or more virtual functions disposed in a host interface module (HIM); or
one or more physical functions (Kim, fig. 2 buffer memory 175).
As to claim 7, Kim/Pico discloses the data storage device of claim 6, wherein each virtual function or physical function includes a corresponding drain buffer (Kim, par. 67).
As to claim 9, Kim/Pico discloses the data storage device of claim 1, wherein the controller is configured to ignore the modified packet for write access (Kim, fig. 14, s140).
As to claim 13, Kim/Pico discloses the data storage device of claim 1, wherein the controller is further configured to:
generate both regular host traffic and internal events (Kim, fig. 16 s220 generate “data stored in memory cell” for read events); and
transmit the regular host traffic and internal events over an interface to the host device (s270).
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over in view of Pico and further in view of Choi (US 20220004418).
As to claim 4, Kim/Pico discloses the data storage device of claim 1, but does not disclose the limitations in claim 4. In the same field of art (data storage), Choi discloses a memory system that supports a plurality of virtual functions (par. 5). In one embodiment, Choi further discloses a packet is from a first virtual function (par. 93, VF controller 312). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kim/Pico and Choi, by comprising the packet from a first virtual function. The motivation is to improve the performance of the system (par. 5).
As to claim 5, Kim/Pico/Choi discloses the data storage device of claim 4, wherein the modified packet is routed to a second virtual function different from the first virtual function (Choi, par. 61).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Pico and further in view of Arai et al (US 20160342545, Arai).
As to claim 8, Kim/Pico discloses the data storage device of claim 7, but does not disclose the limitations in claim 8. In the same field of art (data storage), Arai discloses a data memory device that has a command transfer direct memory access (DMA) engine configured to obtain a command that is generated by an external apparatus to give a data transfer instruction from a memory of the external apparatus (abstract). In one embodiment, Arai further discloses a HIM (fig. 1 module 10) further includes the DMA module (DMA 190), and wherein the DMA module includes a multiplexer (fig. 11, mux 1960). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kim/Pico and Arai, by configuring the HIM further to include the DMA module, and wherein the DMA module includes a multiplexer. The motivation is to improve the efficiency and the performance of the system (par. 18).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Pico and further in view of Liu (US 20170068811).
As to claim 10, Kim/Pico discloses the data storage device of claim 1, but does not disclose the limitations in claim 10. In the same field of art (peripheral configuration), Liu discloses a method for secure access control based on an on-chip bus AXI protocol (abstract). In one embodiment, Liu further discloses a controller is configured to return all zeros for read access (par. 4). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kim/Pico and Liu, by configuring the controller to return all zeros for the modified packet for read access. The motivation is to improve the data security of the system (par. 4).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Pico and further in view of Warkentin (US 20230325203).
As to claim 11, Kim/Pico discloses the data storage device of claim 1, but does not disclose the limitations in claim 11. In the same field of art (peripheral configuration), Warkentin discloses a management operating systems using boot coordination agents (par. 9). In one embodiment, Warkentin discloses a packet is used for a special flow and wherein the special flow is selected from the group consisting of exception flows, abort flows, and reset flows (par. 52). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kim/Pico and Warkentin, by configuring the packet for a special flow and wherein the special flow is selected from the group consisting of exception flows, abort flows, and reset flows. The motivation is to x of the system (Background).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Pico and further in view of Toumiya.
As to claim 12, Kim/Pico discloses the data storage device of claim 1, but does not disclose the limitations in claim 12. In the same field of art (peripheral configuration), Toumiya discloses a test pattern compression apparatus (fig. 1). In one embodiment, Toumiya further discloses a controller (local CPU) further to measure attributes (fig. 3 S15) of the modified packets (fig. 4, pattern#1 for example). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kim/Pico and Toumiya, by configuring the controller further to measure attributes of the modified packets. The motivation is to the efficiency of the system (due to better data compression).
Claims 16-17, 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Toumiya in view of Kim.
As to claim 16, Toumiya discloses the data storage device of claim 14, but does not disclose the limitations in claim 16 (instead discloses the functions are processing units). In the same field of art (peripheral configuration), Kim discloses a method of sending data to a function (fig. 1 host 10 functions as a processing unit) wherein the function contains a drain buffer (buffer 160). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Toumiya and Kim, by configuring the first function and the second function each with a drain buffer. The motivation is to improve the performance of the system (par. 4).
As to claim 17, Toumiya/Kim discloses the data storage device of claim 16, wherein the rerouting is to the drain buffer of the second function (Kim, fig. 14 s150).
As to claim 19, Toumiya/Kim discloses the data storage device of claim 18, but does not disclose the limitations in claim 19 (instead discloses the functions are processing units). In the same field of art (peripheral configuration), Kim discloses a method of sending data to a function (fig. 1 host 10 functions as a processing unit) wherein the function contains a drain buffer (buffer 160). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Toumiya and Kim, by configuring the routing to a drain buffer of the second function. The motivation is to improve the performance of the system (par. 4).
As to claim 20, Toumiya/Kim discloses the data storage device of claim 19, wherein the generating, transmitting, and routing are transparent to a remainder of the data storage device (Toumiya, fig. 7. Note: Output unit is transparent to generating, transmitting, routing steps).
Conclusion
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/D.P/Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184