DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to the claim have been considered but are moot because the newly added subject matters do not teach in any reference applied in the prior rejection of record.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 6, 7, 9, 13-19 are rejected under 35 U.S.C. 103 as being unpatentable over Benisty et al (US 20210240641) in view of Shahar et al (US 20190171612, Shahar).
As to claim 1, Benisty discloses a data storage device (fig.1 device 100), comprising:
a memory device (NVM 106); and
a controller coupled to the memory device (controller 110), wherein the controller is configured to:
generate a packet for a host device (par. 44 “transfer request”);
activate a direct memory access (DMA) module (par. 32 “activating the DMAs”);
determine that the packet should be drained (fig. 5 S530);
replace host address with a drain buffer address to create a modified packet (par. 63 “modified TLP”);
send the modified packet to the host device (par. 49 “transfers the one or more modified TLPs generated from block 550 to the host 150”);
drain the modified packet (par. 49 “the host 150 ignores the data payload”).
Benisty does not disclose the step of after the sending, route the modified packet from the host device to a drain buffer (par. 63, instead discloses the step of routing the modified packet to a drain buffer 164”). In the same field of art (data storage), Shahar discloses a system comprising a network adapter, including a network interface, a host interface, and processing circuitry (fig. 1 host 24). In one embodiment, Shahar further discloses the step of after the sending (par. 35 “transmitting processed data” by NIC 32), routing a modified packet (by NIC 42) from a host device (host 24) to a buffer (Note: NIC 42 receives and transfers payload data to target 48). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Benisty and Shahar, by after the sending, routing the modified packet from the host device to a drain buffer. The motivation is to improve the performance of the system.
As to claim 3, Benisty/Shahar discloses the data storage device of claim 1, wherein the sending occurs over a peripheral component interconnect express (PCle) bus (par. 25).
As to claim 6, Benisty/Shahar discloses the data storage device of claim 1, wherein the controller includes at least one of the following:
one or more virtual functions disposed in a host interface module (HIM) (Benisty, par. 26); or
one or more physical functions (par. 28).
As to claim 7, Benisty/Shahar discloses the data storage device of claim 6, wherein each virtual function or physical function includes a corresponding drain buffer (Benisty, par. 49).
As to claim 9, Benisty/Shahar discloses the data storage device of claim 1, wherein the controller is configured to ignore the modified packet for write access (Benisty, par. 62 “write request TLP”. Note: The controller sends the modified packet it to host 150 to ignore).
As to claim 13, Benisty/Shahar discloses the data storage device of claim 1, wherein the controller is further configured to:
generate both regular host traffic and internal events (Benisty, par. 49); and
transmit the regular host traffic and internal events over an interface to the host device (“via host interface 101”).
As to claim 14, Benisty discloses a data storage device (fig. 1, device 102), comprising:
a memory device (memory 122, 106); and
a controller coupled to the memory device (controller 110), wherein the controller is configured to:
generate one or more dummy packets (par. 44 “transfer request”) for a first function (“device-to-host transfer”);
transmit the one or more dummy packets over an interface (par. 49 host interface 101) to a host device (host 150);
measure attributes of the one or more dummy packets (fig. 5 S570).
Benisty does not disclose the step of rerouting the one or more dummy packets from the host device to a second function after the transmitting (par. 63, instead discloses the step of rerouting the modified packet to a drain buffer 164”). In the same field of art (data storage), Shahar discloses a system comprising a network adapter, including a network interface, a host interface, and processing circuitry (fig. 1 host 24). In one embodiment, Shahar further discloses the step of after the sending (par. 35 “transmitting processed data” by NIC 32), routing one or more packets (by NIC 42) from a host device (host 24) to a buffer (Note: NIC 42 receives and transfers payload data to target 48). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Benisty and Shahar, by rerouting the one or more dummy packets from the host device to a second function after the transmitting. The motivation is to improve the performance of the system.
As to claim 15, Benisty/Shahar discloses the data storage device of claim 14, wherein the attributes are selected from the group consisting of latency, performance (fig. 5 S570. Note: “determining whether device-to-host request has been complete” is performance attributes), and combinations thereof.
As to claim 16, Benisty/Shahar discloses the data storage device of claim 14, wherein the first function and the second function each contain a drain buffer (Benisty, fig. 1CMB 124 and HMB 164)
As to claim 17, Benisty/Shahar discloses the data storage device of claim 16, wherein the rerouting is to the drain buffer of the second function (Benisty, par. 63).
As to claim 18, Benisty discloses a data storage device (fig. 1), comprising:
means to store data (memory 122, 106); and
a controller coupled to the means to store data (controller 110), wherein the controller is configured to:
generate regular host traffic and internal events for a first function (par. 48 “generates one or more modified TLPs”);
transmit the regular host traffic and internal events over an interface (par. 49, interface 101) to a host device (host 150).
Benisty does not disclose the step of routing the internal events from the host device to a second function after the transmitting (par. 63, instead discloses the step of rerouting the modified packet to a drain buffer 164”). In the same field of art (data storage), Shahar discloses a system comprising a network adapter, including a network interface, a host interface, and processing circuitry (fig. 1 host 24). In one embodiment, Shahar further discloses the step of after the sending (par. 35 “transmitting processed data” by NIC 32), routing one or more packets (by NIC 42) from a host device (host 24) to a buffer (Note: NIC 42 receives and transfers payload data to target 48). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Benisty and Shahar, by routing the internal events from the host device to a second function after the transmitting. The motivation is to improve the performance of the system.
As to claim 19, Benisty/Shahar discloses the data storage device of claim 18, wherein the routing to a drain buffer of the second function (Benistypar. 63).
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Benisty in view of Shahar and further in view of Groves (US 20250028611).
As to claim 4, Benisty/Shahar discloses the data storage device of claim 1, but does not disclose the limitations in claim 4. In the same field of art (data storage), Groves discloses the method of managing copies of program states using shared memory snapshots on memory devices (par. 15). In one embodiment, Groves further discloses a packet is transferred from a first virtual function (fig. 1B, memory sub-system 110B, par. 154) to a second virtual function (host system 126b, par. 70). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Benisty/Shahar and Groves, by comprising the packet from a first virtual function. The motivation is to improve the efficiency of the system.
As to claim 5, Benisty/Shahar/Groves discloses the data storage device of claim 4, wherein the modified packet is routed to a second virtual function different from the first virtual function (Groves, par. 70. Host 126B is a second virtual function).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Benisty in view of Shahar and further in view of Arai et al (US 20160342545, Arai).
As to claim 8, Benisty/Shahar discloses the data storage device of claim 7, but does not disclose the limitations in claim 8. In the same field of art (data storage), Arai discloses a data memory device that has a command transfer direct memory access (DMA) engine configured to obtain a command that is generated by an external apparatus to give a data transfer instruction from a memory of the external apparatus (abstract). In one embodiment, Arai further discloses a HIM (fig. 1 module 10) further includes the DMA module (DMA 190), and wherein the DMA module includes a multiplexer (fig. 11, mux 1960). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Benisty/Shahar and Arai, by configuring the HIM further to include the DMA module, and wherein the DMA module includes a multiplexer. The motivation is to improve the efficiency and the performance of the system (par. 18).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Benisty in view of Shahar and further in view of Liu (US 20170068811).
As to claim 10, Benisty/Shahar discloses the data storage device of claim 1, but does not disclose the limitations in claim 10. In the same field of art (peripheral configuration), Liu discloses a method for secure access control based on an on-chip bus AXI protocol (abstract). In one embodiment, Liu further discloses a controller is configured to return all zeros for read access (par. 4). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Benisty/Shahar and Liu, by configuring the controller to return all zeros for the modified packet for read access. The motivation is to improve the data security of the system (par. 4).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Benisty in view of Shahar and further in view of Warkentin (US 20230325203).
As to claim 11, Benisty/Shahar discloses the data storage device of claim 1, but does not disclose the limitations in claim 11. In the same field of art (peripheral configuration), Warkentin discloses a management operating systems using boot coordination agents (par. 9). In one embodiment, Warkentin discloses a packet is used for a special flow and wherein the special flow is selected from the group consisting of exception flows, abort flows, and reset flows (par. 52). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Benisty/Shahar and Warkentin, by configuring the packet for a special flow and wherein the special flow is selected from the group consisting of exception flows, abort flows, and reset flows. The motivation is to x of the system (Background).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Benisty in view of Shahar and further in view of Toumiya.
As to claim 12, Benisty/Shahar discloses the data storage device of claim 1, but does not disclose the limitations in claim 12. In the same field of art (peripheral configuration), Toumiya discloses a test pattern compression apparatus (fig. 1). In one embodiment, Toumiya further discloses a controller (local CPU) further to measure attributes (fig. 3 S15) of the modified packets (fig. 4, pattern#1 for example). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Benisty/Shahar and Toumiya, by configuring the controller further to measure attributes of the modified packets. The motivation is to the efficiency of the system (due to better data compression).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Benisty in view of Shahar and further in view of Benisty et al (US 20190354300, Benisty2).
As to claim 20, Benisty/Shahar discloses the data storage device of claim 19, but does not disclose the limitations in claim 20 (instead discloses the generating, transmitting, and routing are performed by the storage controller 110). In the same field of art (peripheral configuration), Benisty2 discloses a storage controller (fig. 1 controller 102) is transparent to a remainder of the data storage device (fig. 4, storage device 104, par. 33). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Benisty/Shahar and Benisty2, by configuring the generating, transmitting, and routing to be transparent to a remainder of the data storage device. The motivation is to reduce the power consumption of the system (par. 4).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.P/Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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