DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
The amendment filed March 26, 2026 has been entered. Claims 21-26 are newly filed, leaving claims 1-4, 7-11, 14-18, and 21-26 pending in this application.
The amendment to the claims overcome the rejection to the claims under 35 U.S.C. 112, as presented in the prior office action mailed January 7, 2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on March 26, 2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 7-9, 14-16, 22, 24, and 25 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Earhart et al. (US 2018/0275923, as presented in applicant’s IDS).
Regarding claim 1, Earhart teaches a method, comprising:
receiving, by a processing device, a request to perform a memory operation using a hardware resource associated with a memory device (Fig. 2, storage controller receives data streams from host systems; see also [0039], where each data stream has a different service level agreement and Quality of Service requirement, as well as Fig. 4 and [0077], where data streams from a host are able to be recognized as either write or read commands for the storage media of Fig. 2);
determining a type of the memory operation (Fig. 4 and [0077], where data streams from a host are able to be recognized as either write or read commands for the storage media of Fig. 2);
identifying a traffic class corresponding to the memory operation (in the context of Fig. 4 discussing a quality of service controller within storage controller, see [0074], memory operations are able to be identified based on whether the write/read commands originate from a user, see [0077-0078], or background processes such as read and writes and erases, see [0052,0075,0079,0082]);
determining, based on the traffic class and the type of the memory operation, whether the memory operation is to be processed during a current scheduling time frame (“Arbiter 408 takes requests from these queues and forwards them to storage array 410 for execution. The arbitration algorithm in the stream router enforces the QoS,” [0082], where the arbiter measures performances to ensure that a QoS policy is being met, see [0083-0085]; see also where each read/write queue utilizes token buckets, see [0017], see also “In general, tokens are defined to represent some constrained resource, such as time or bytes… When the owner of a bucket performs an operation the appropriate number of tokens for the operation are removed from the bucket. When the bucket owner makes a request to perform an operation and it has sufficient tokens in its bucket, the request is deemed conforming. When it lacks sufficient tokens, its request is deemed nonconforming,” [0065], teaching that the determination of when to route requests for execution is dependent on the appropriate bucket and queue having sufficient tokens for execution; as seen in Fig. 4 and already cited in [0077,0082], the write and read queues are associated with originating from a user or background process, and therefore the read vs, write nature of the queue reads upon the memory type being accounted for, and the user vs. process nature of the queue reads upon the traffic class being accounted for);
predicting, based on a type of memory operation of the previous request and a time when the memory operation of the previous request is submitted, that the hardware resource is available (“In general, tokens are defined to represent some constrained resource, such as time or bytes… When the owner of a bucket performs an operation the appropriate number of tokens for the operation are removed from the bucket. When the bucket owner makes a request to perform an operation and it has sufficient tokens in its bucket, the request is deemed conforming. When it lacks sufficient tokens, its request is deemed nonconforming,” [0065] teaches the determination that the hardware resource is available for performing operations; Earhart discloses that tokens are added to token buckets at a rate based on SLA’s and measured QOS’ metrics for workloads, where the QOS levels are measured by a QOS measurement module, see [0018, 0020, 0106]; Earhart utilizes creation and completion timestamps to monitor read bandwidth, read latency, write bandwidth, write latency, and IOPS, see [0081,0083]; this teaches that the QOS modules make determinations of QOS metrics and allocate tokens based on measurements of the QOS of previous requests, including the type of operation (where the QOS metrics include read bandwidth vs. write bandwidth and read latency vs. write latency), as well as the time when the previous requests are submitted (where the QOS metrics utilize the creation timestamps of requests) where the tokens provide a prediction that the resource is available for operation); and
submitting the memory operation to the memory device (“Arbiter 408 takes requests from these queues and forwards them to storage array 410 for execution. The arbitration algorithm in the stream router enforces the QoS,” [0082]).
Regarding claim 2, Earhart teaches the method of claim 1, further comprising:
responsive to receiving the request, queueing the request in a scheduling pool of a plurality of scheduling pools (“Each media access command type and stream is assigned a request queue 430-452. This includes writes, reads, and erases in the case of flash”, [0082], where Fig. 4 shows these request queues for different commands and streams), wherein the scheduling pool is associated with the traffic class and the hardware resource (as seen in Fig. 4, the different queues 430-452 are assigned to different command types (i.e. write vs. read) as well as source process (i.e. from a user versus internal process), teaching that each scheduling pool is associated with a particular traffic class; further, all the queues are shown in Figs. 3 and 4 to route the queues to the storage array, teaching that the scheduling pool is associated with the hardware resource as well).
Regarding claim 7, Earhart teaches the method of claim 1, wherein the traffic class is one of: host read, host write, and background operation (Fig. 4 shows user based read/write queues, internal process read and write queues, and internal process erase queues).
Regarding claim 8, Earhart teaches a system (Fig. 1, storage system 160) comprising:
a memory device (Fig. 1, storage media 130); and
a processing device, operatively coupled with the memory device, the processing device configured to perform the method of claim 1 and rejected according to the same rationale (Fig. 1, storage controller 120, where Fig. 6 shows storage controller 600 containing processing circuitry, which is configured to perform the tasks of the storage controller described in Earhart’s disclosure, see [0109]).
Claim 9 is rejected according to the same rationale of claim 2.
Regarding claim 15, Earhart teaches a non-transitory machine-readable storage medium comprising executable instructions that, when executed by a processing device, cause the processing device to perform the method of claim 1 and can be rejected according to the same rationale (Fig. 6 , internal storage system 640, which stores software, see also [0110] describing storage system 640 as non-transitory, and [0112] describing software which when executed by processing circuitry, operates the functions of the storage controller)).
Claim 16 is rejected according to the same rationale of claim 2.
Regarding claim 22, Earhart teaches the method of claim 1, and further teaches wherein predicting that the hardware resource is available further comprises: comparing the hardware resource against hardware resources of previously submitted memory operations that have not yet completed (part of the factor of the arbiter’s scheduling is to account or issuing commands to interfaces that are not yet finished processing commands as well as a request’s estimated time required and other concurrent requests, see [0072,0073], i.e. requests that have not yet completed, reading upon the limitation of the claim. ).
Regarding claim 24, Earhart teaches the method of claim 1, and further teaches wherein the previous request is a last submitted request (as discussed in the claim 1 rationale, Earhart [0065] determines whether hardware resources are available for performing operations utilizing token counts, where token counts are added based on SLA/QOS metrics, see [0018,0020,0106]; as submitted requests that are conforming decrease the number of tokens in a bucket, see [0065], then necessarily, part of the determination of whether hardware resources is available is based on the tokens taken out for the last submitted request, and the QOS metrics for workloads are affected by the last submitted request, reading on the limitation of the claim).
Regarding claim 25, Earhart teaches the method of claim 1, further comprising:
Receiving, from the memory device, an operation completion response for the memory operation; and routing the operation completion response to a backend resource manager to update availability of the hardware resource (“These response queues store responses 454 received from storage array 410 for transfer to QoS measurement module 402,” [0075] and “The storage array 410 completes the requests and returns a response 454 for each request to the requesting process,” [0080], where “Each media command is given a creation timestamp 428 when it is generated by a process. When the request is returned to the process's response queue, a completion timestamp 428 is generated. These timestamps are used by QoS measurement module 402 to monitor QoS and detect violations,” [0081]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 3, 10, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Earhart in view of Benisty (US 2020/0326890, as presented in applicant’s IDS).
Regarding claim 3, Earhart teaches the method of claim 2, but fails to teach the method further comprising:
dequeuing the request from the scheduling pool using a round robin algorithm.
As disclosed above, Earhart only discloses utilizing the QOS/SLA monitoring to determine which bucket to dequeue from, with no discussion of the usage of a round robin algorithm.
Benisty’s disclosure is related to managing storage queues and as such comprises analogous art in the same field of endeavor of storage management.
As part of this disclosure, Benisty discloses a system utilizing different command queues, see Figs. 1 and 2, where the commands may have different priorities and command types, see [0037]. When dequeuing the commands, Benisty discloses the use of round-robin and weighted round-robin algorithms, see [0038], see also [0039, 0040] for more details on the round robin algorithm.
An obvious modification can be identified: incorporating Benisty’s round-robin or weighted round-robin algorithm into Earhart’s memory queue system. Such a modification reads upon the limitation of the claim.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate Benisty’s round-robin/weighted round-robin algorithms for dequeuing commands from command queue into Earhart’s memory system, as this ensures that all queues will be able to process commands in a reasonably timely manner, instead of one queue being pre-empted forever.
Claims 10 and 17 are rejected according to the same rationale of claim 3.
Claims 4, 11, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Earhart in view of Wells et al. (US 2019/0278515, as presented in applicant’s IDS).
Regarding claim 4, Earhart teaches the method of claim 1, but fails to teach wherein submitting the memory operation is performed responsive to determining that a count of outstanding requests for the hardware resource is below a predetermined threshold.
Wells’ disclosure relates to managing command queues for storage devices, and as such comprises analogous art.
As part of this disclosure, Wells provides for a flowchart in Fig. 3A showing how to manage issuing commands from a queue. As seen, Wells maintains a count of active commands Nc, where [0032] defines active command as “a command that has been issued to NAND array 130 and has not yet completed”. As seen in Fig 3A, in order to issue a command, step 316, the number of active commands must be less than Cmax in decision block 312, where “In a step 312, active command limiter 220 compares the number of active SSD commands to a maximum number of allowed active SSD commands (Cmax)… If the number of active SSD commands is not greater than or equal to the maximum allowed number, the method continues,” [0037].
An obvious modification can be identified: incorporating Wells’ tracking of active command, as well as maintaining a threshold under which commands can be issued, but above which the system will hang and wait. Such a modification reads upon the limitation of the claim, as the active commands in the SSD read upon the outstanding requests for the hardware resource, and the Cmax utilized reads upon the predetermined threshold, and the Fig. 3A flowchart reading upon the conditional submission of the memory operation.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate Well’s tracking of active commands and utilizing a maximum threshold of active commands into Earhart’s system, as “By limiting the number of SSD commands that are concurrently active, the probability of a collision between an SSD command and a host command is reduced and thus latency variations in the performance of the SSD are minimized,” [0032].
Claims 11 and 18 are rejected according to the same rationale of claim 4.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Earhart in view of Canion et al. (US 8,000,244).
Earhart teaches the method of claim 2, but fails to teach the method further comprising:
Responsive to determining the hardware resource is unavailable, re-queueing the request in the scheduling pool.
Canion’s disclosure is related to traffic routing via the use of token buckets, and as such comprises analogous art in the same field of endeavor of resource allocation/routing, and even given the broader context of network traffic packets instead of a storage system, the discussion concerning how to handle token buckets would be reasonably pertinent to one of ordinary skill in the art looking at how to process requests in scheduling pools.
As part of this disclosure, Canion provides that “If the rate limiter does not have a sufficient number of tokens to transmit the packet 176, then the packet 176 is not transmitted (step 260). The packet 176 may, for example, be dropped. As another example, the packet 176 may be re-queued onto the output queue 174, so that another attempt may be made to transmit the packet 176 at a future time,” Col. 9, Lines 4-10.
An obvious modification can be identified: incorporating Canion’s disclosure of re-queuing packets that do not have sufficient tokens at a given moment in time into Earhart’s token bucket system. Such a modification reads upon the limitation of the claim.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate Canion’s disclosure of re-queueing packets with insufficient tokens into Earhart’s token bucket system, as this provides a mechanism to recover from a momentary lack of available resources without having to go back to the requesting host/user to re-submit the request again.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Earhart in view of Gries et al. (“Modeling a shared medium access node with QoS distinction,” as provided in applicant’s November 2023 IDS).
Earhart teaches the method of claim 1, and teaches the method further comprising:
Queueing the request in a scheduling pool of a plurality of scheduling pools (“Each media access command type and stream is assigned a request queue 430-452. This includes writes, reads, and erases in the case of flash”, [0082], where Fig. 4 shows these request queues for different commands and streams), wherein each scheduling pool corresponds to a particular traffic class and a particular hardware resource (as seen in Fig. 4, the different queues 430-452 are assigned to different command types (i.e. write vs. read) as well as source process (i.e. from a user versus internal process), teaching that each scheduling pool is associated with a particular traffic class; further, all the queues are shown in Figs. 3 and 4 to route the queues to the storage array, teaching that the scheduling pool is associated with the hardware resource as well).
Earhart fails to teach where the plurality of scheduling pools is a two dimensional array of scheduling pools.
Gries’ disclosure is related to handling scheduling for memory based on QoS information and as such comprises analogous art in the same field of endeavor of queue management.
As part of this disclosure, Gries’ disclosure looks at how different QoS requirements affects packet handling and system behavior, see Section 6, Paragraph 1. One class of schedulers that Gries looks at is a Fixed Priority Scheduler, see Section 6.1, where in order to enqueue the packet, Gries utilizes a lookup implemented as a 2D-array, see Section 6.1.1, Paragraph 1, where “the lookup table is organized as a 2D-array of pointers using the destination node and the priority class as indices. The pointers direct to the end of the corresponding FIFO queue”. In addition, Gries discloses that the FIFO queues for the different priority classes are implemented as linked lists, see Section 6.1.1, Paragraph 1.
An obvious modification can be identified: incorporating Gries’ 2D lookup table for the queues. Such a modifications upon the limitation of the claim, as Gries provides for a 2D array for providing for the queues, and Gries provides for indices for the particular destination node and priority class, where this can modify Earhart’s queues to include a dimension of write/read/internal process queues and the destination flash interface, see Earhart Figs. 3 and 4, reading upon particular traffic class/hardware resource associated with each scheduling pool.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate Gries’ 2D look up table and queue/linked list implementations, as the ability to include additional queues to store requests not just by QoS class but by the destination location would allow for greater versatility in scheduling by being able to select by QoS and destination, not just QoS class.
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Earhart in view of Benisty et al. (US 2017/0090753).
Earhart teaches the method of claim 1, further comprising:
Receiving, from the memory device, an operation completion response for the memory operation (“The storage array 410 completes the requests and returns a response 454 for each request to the requesting process,” [0080]).
Earhart fails to teach routing the operation completion response to a frontend to acknowledge completion of the memory operation.
Benisty’s disclosure relates to managing queues for storage devices and as such comprises analogous art in the same filed of endeavor of storage management.
As part of this disclosure, Benisty provides for an NVMe system, where commands and command completions are stored in submission queues/completion queues on host side (see Fig. 1, CQ/SQ’s being stored in the host DRAM) for submission to a storage device. Benisty discloses that “The nonvolatile storage device fetches the commands from the submission queues, executes the commands, and places entries in completion queues, which are also implemented in host memory, to notify the host of completion of the commands,” [0002].
An obvious modification can be identified: incorporating Benisty’s use of NVMe’s submission and completion queues into the host side devices. Such a modification reads upon the limitation of the claim, as Benisty provides that completion response are submitted to the host explicitly to notify the host of completion of commands.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate Benisty’s use of NVMe’s host-side completion queues into Earhart’s storage system, as this provides a mechanism by which a host can recognize whether a storage command has been completed or not, giving more versatility, transparency, and more detailed information to the host.
Response to Arguments
Applicant's arguments filed October 20, 2025 have been fully considered but are moot in part and unpersuasive in part.
Regarding dependent claims 21-26 that are newly filed, the subject matter has not been examined in the instant application before, and as such, requires new citation/rationale from Earhart, as well as new references Canion, Gries, and Benisty. As such, the arguments are moot in part for lack of opportunity to address the new rationale.
The arguments focus on Earhart’s discussion of tokens, arguing that Earhart’s discussion of conformity/noncomformity does not teach the availability of a hardware resource. However, this is unpersuasive, as Earhart plainly associates the tokens with a hardware constrained resource of timing/bytes, see [0065], which provides the context in which conforming or noncomforming commands are processed to be the bandwidth/throughput of the storage device, i.e. the availability of the resource. This argument is unpersuasive.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chen et al. (US 2008/0095053) discloses re-queueing requests,
Oelke (US 2015/0373017) discloses managing I/O requests based on a token bucket scheme, including consideration of prior I/O requests,
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. The subject matter of claims 21-26 are newly recited, requiring additional citations/references. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/A.D.H./Examiner, Art Unit 2139
/REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139
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