DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102
and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same
under either status.
Response to Arguments
Applicant's arguments filed 05/01/2026 regarding the prior art rejections of Claims 1, 14, and 20 have been fully considered, but they are not persuasive. Applicant’s arguments with respect to claim(s) 1, 14, and 20 have been considered but are moot in view of the new ground of rejection introduced because of the added limitations.
The Remarks argue that:
During the interview, Applicant's representatives discussed the claimed features of "refresh, for a first duration, a first block of non-volatile memory cells of the memory device ... wherein the first block comprises a production state awareness (PSA) block." The claimed features were contrasted with those of the references cited in the standing rejection of the claims. Examiner Perry acknowledged that the cited references do not teach all of the features of the amended claims, and agreed to reconsider the claims in view of the discussion.
The Examiner agrees during the interview the agreement was made Hsu’s teaching of PSA was different from the PSA taught in the presented application. However, with the new prior art, Otterstedt, in combination with Xie and Jayaraman the features recited in the amended independent claims 1, 14, and 20 can be deduced. The previous prior art rejection is maintained.
Claims 2 – 13 which depend from amended claim 1, have been considered and rejected.
Claims 15 – 19 which depend from amended claim 14, have been considered and rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 11 & 13 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Xie (US 2021/0019084 A1) in view of Jayaraman (US 2016/0162215 A1) in view of Otterstedt (US 2017/0308431 A1). Claim 12 has been canceled.
With regards to claim 1, Xie teaches:
An apparatus, comprising: a controller associated with a memory device (0019, The memory system controller), wherein the controller is configured to cause the apparatus to: transition from a first power state to a second power state after a reflow operation (0011, a read voltage can be applied to memory cells to determine whether the memory cell is in a high voltage state representing a bit value of ‘1’ or a low voltage state representing a bit value of ‘0’ (or vice versa). For certain types of memory components, a read operation can change the threshold voltage distribution of the memory cells); refreshing, for a first duration, a first block of non-volatile memory cells of the memory device based at least in part on transitioning from the first power state to the second power state (0028, the refresh operation is consecutive write operations that are to write alternating states at the memory cells), wherein the first block has a first bit error rate that is within a first range of bit error rates (0037, the refresh operation is performed responsive to the difference satisfying the threshold difference.); determine whether a second block of non-volatile memory cells of the memory device has a second bit error rate that is within a second range of bit error rates based at least in part on refreshing the first block (Fig. 3 & 0031, the bit error rate can become larger as shown at point 313. At this point, the memory sub-system can utilize a different read voltage than the read voltage that is represented by the curve 320); and refresh, during a second duration that corresponds to the second range of bit error rates (Fig. 3 & 0030, if a read operation is performed at a time during the specified time period 310, then the refresh operation can be performed to re-write the data at the write unit), the second block of non-volatile memory cells based at least in part on determining that the second bit error rate is within the second range of bit error rates, (Fig. 3 & 0031, the bit error rate can become larger as shown at point 313. At this point, the memory sub-system can utilize a different read voltage than the read voltage that is represented by the curve 320).
Xie fails to teach:
wherein the second duration is associated with an idle duration of the memory device. However, Jayaraman teaches:
wherein the second duration is associated with an idle duration of the memory device. (0004 & 0014, Depending on how fast data is being received from a host device and what types of operations are being performed at the memory, different memory dies may have “idle” time periods and “busy” time periods. The controller 120 may schedule operations to be performed during the idle time periods, such as a write operation, a maintenance operation, an error-checking operation, or a combination thereof, as illustrative, non-limiting examples.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of an apparatus, comprising: a controller associated with a memory device, wherein the controller is configured to cause the apparatus of Xie with the teaching of Jayaraman, which teaches an idle duration of the memory device in order to increase the overall data rate.
Xie in view of fails to teach:
and wherein the first block comprises a production state awareness (PSA) block;
However, Otterstedt teaches:
and wherein the first block comprises a production state awareness (PSA) block; (0039, before the memory device 100 is subjected to the data hazardous process or situation, for example before a soldering, or more generally, an attachment of the memory device, is performed, the to be protected data 102 and the extra ECC data 106 used for this protection may be written into the memory device 100, i.e. into memory cells of the memory device 100, e.g. a memory array: This may be done in one combined process, or in two steps, wherein the preloaded data 102 may be extended in the second step with the extra ECC data 106.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of an apparatus, comprising: a controller associated with a memory device, wherein the controller is configured to cause the apparatus of Xie with the teaching of Otterstedt, which teaches preloaded memory cells in order to configure.
With regards to claim 2, Xie teaches the apparatus of claim 1:
wherein the controller is further configured to cause the apparatus to: associate the first block of non-volatile memory cells with the first range of bit error rates (0029, FIG. 3 illustrates bit error rates relative to write to read time differences;) based at least in part on transitioning from the first power state to the second power state (0011, in a high voltage state representing a bit value of ‘1’ or a low voltage state representing a bit value of ‘0’), wherein refreshing the first block of non-volatile memory cells (0037, In the same or alternative embodiments, the data of the write unit is written to a different group of memory cells.) for the first duration is based at least in part on associating the first block of non-volatile memory cells with the first range of bit error rates (0028 & 0031, the refresh operation is consecutive write operations that are to write alternating states at the memory cells; memory sub-system can utilize a different read voltage than the read voltage that is represented by the curve 320).
With regards to claim 3, Xie teaches the apparatus of claim 2:
wherein the controller is further configured to cause the apparatus to: determine that a third block of non-volatile memory cells of the memory device has a third bit error rate that is within a third range of bit error rates (0029 & 0037, FIG.3 illustrates bit error rates relative to write to read time differences; In the same or alternative embodiments, the data of the write unit is written to a different group of memory cells.); and refrain from refreshing, for the first duration, the third block of non-volatile memory cells based at least in part on determining that the third bit error rate of the third block is within the third range of bit error rates.
With regards to claim 4, Xie teaches the apparatus of claim 1:
wherein the controller is further configured to cause the apparatus to: receive a write command associated with the second block of non-volatile memory cells; and assign a timestamp to the second block of non-volatile memory cells based at least in part on receiving the write command (0037, In the same or alternative embodiments, the data of the write unit is written to a different group of memory cells. In some embodiments, the refresh operation is performed when the write to read time difference satisfies the time difference condition), wherein determining whether the second block of non-volatile memory cells has the second bit error rate is based at least in part on assigning the timestamp (0006 & 0011, bit error rates relative to write to read time differences; when data is written to the memory sub-system, a timestamp or other indication of when the data has been written can be recorded.).
With regards to claim 5, Xie teaches the apparatus of claim 4:
wherein the controller is further configured to cause the apparatus to: transition from the first power state to the second power state; determine that the second block of non-volatile memory cells has the second bit error rate based at least in part on the timestamp and transitioning from the first power state to the second power state (0011, a read voltage can be applied to memory cells to determine whether the memory cell is in a high voltage state representing a bit value of ‘1’ or a low voltage state representing a bit value of ‘0’ (or vice versa). when data is written to the memory sub-system, a timestamp or other indication of when the data has been written can be recorded); and determine that the second bit error rate satisfies a threshold value based at least in part on determining that the second block of non-volatile memory cells has the second bit error rate (0037, the refresh operation is performed responsive to the difference satisfying the threshold difference).
With regards to claim 6, Xie teaches the apparatus of claim 5:
wherein the controller is further configured to cause the apparatus to: associate the second block of non-volatile memory cells with the second range of bit error rates based at least in part on determining that the second bit error rate satisfies the threshold value (0031 & 0037, A memory sub-system can utilize a different read voltage than the read voltage that is represented by the curve 320.the refresh operation is performed responsive to the difference satisfying the threshold difference), wherein the second block of non-volatile memory cells is refreshed during the second duration based at least in part on associating the second block of non- volatile memory cells with the second range of bit error rates (0013, when the data was read satisfies a threshold time difference (e.g., the read operation was performed within a specified time period soon after the data was written), then a refresh operation can be performed at the memory cells that stored the data to re-write the data).
With regards to claim 7, Xie teaches the apparatus of claim 6:
wherein the controller is further configured to cause the apparatus to: receive a command from a host system based at least in part on determining that the second bit error rate satisfies the threshold value, wherein the command indicates a third duration for associating the second block of non-volatile memory cells with the second range of bit error rates, wherein the third duration occurs after the first duration and before the second duration (0013, when the data was read satisfies a threshold time difference (e.g., the read operation was performed within a specified time period soon after the data was written), then a refresh operation can be performed at the memory cells that stored the data to re-write the data).
With regards to claim 8, Xie teaches the apparatus of claim 6:
wherein associating the second block of non- volatile memory cells with the second range of bit error rates occurs absent receiving a command from a host system (0037 & 0020, In the same or alternative embodiments, the data of the write unit is written to a different group of memory cells.
The host interface circuitry can convert the commands received from the host system into command instructions to access the memory components).
With regards to claim 9, Xie teaches the apparatus of claim 1:
wherein the controller is further configured to cause the apparatus to: determine that a fourth block of non-volatile memory cells of the memory device has a fourth bit error rate that is within a fourth range of bit error rates based at least in part on determining whether the second block of non-volatile memory cells of the memory device has the second bit error rate; and refresh, during a fourth duration that corresponds to the fourth range of bit error rates, the fourth block of non-volatile memory cells based at least in part on determining that the fourth bit error rate is within the fourth range of bit error rates (0037 & 0013, In the same or alternative embodiments, the data of the write unit is written to a different group of memory cells. When the data was read satisfies a threshold time difference (e.g., the read operation was performed within a specified time period soon after the data was written), then a refresh operation can be performed at the memory cells that stored the data to re-write the data).
With regards to claim 10, Xie teaches the apparatus of claim 9:
wherein the fourth duration is associated with a duration when the memory device is performing a read operation or a write operation (0013, when the data was read satisfies a threshold time difference (e.g., the read operation was performed within a specified time period soon after the data was written), then a refresh operation can be performed at the memory cells that stored the data to re-write the data).
With regards to claim 11, Xie teaches the apparatus of claim 9:
wherein the controller is further configured to cause the apparatus to: perform, during the fourth duration, a write operation on a fifth block of non- volatile memory cells of the memory device concurrent with refreshing the fourth block of non-volatile memory cells (0027, the processing logic performs a refresh operation at the write unit based on the difference between the time when the data of the write unit was written and the other time when the read operation was performed to retrieve the data of the write unit), wherein a cadence associated with performing the write operation and refreshing the fourth block of non-volatile memory cells is adjustable based at least in part on one or more performance criteria of the memory device (0027, the refresh operation can be performed based on whether the difference satisfies a threshold condition).
With regards to claim 13, Xie teaches the apparatus of claim 1. Xie fails to teach:
wherein the second block comprises a non-PSA block. (0018, Each of the memory cells can store one or more bits of data (e.g., data blocks) used by the host system 120.)
With regards to claim 14, Xie teaches and corresponds to claim 1 and is analyzed accordingly.
With regards to claim 15, Xie teaches the non-transitory computer-readable medium of claim 14 and corresponds to claim 2 as analyzed accordingly.
With regards to claim 16, Xie teaches the non-transitory computer-readable medium of claim 15 and corresponds to claim 3 as analyzed accordingly.
With regards to claim 17, Xie teaches the non-transitory computer-readable medium of claim 14 and corresponds to claim 4 as analyzed accordingly.
With regards to claim 18, Xie teaches the non-transitory computer-readable medium of claim 17 and corresponds to claim 5 as analyzed accordingly.
With regards to claim 19, Xie teaches the non-transitory computer-readable medium of claim 18 and corresponds to claim 6 as analyzed accordingly.
With regards to claim 20, Xie teaches and corresponds to claim 1 as analyzed accordingly.
Prior Art Made of Record
The prior art mode of record and not relied upon is considered pertinent to
Applicant’s disclosure:
Franklin (US 2018/0285007 A1): A non-volatile memory device is configured to receive a
refresh command from a controller over a bus. A non-volatile memory device is
configured to perform one or more maintenance operations.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Applicant's amendments have been considered but are moot in view of the new prior art introduced in the rejection presented in this Office action.
Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner
should be directed to VICTOR PERRY whose telephone number is (571)272-6319. The examiner can
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Mark Featherstone can be reached on (571) 270-3750. The fax phone number for the organization
where this application or proceeding is assigned is 571-273-8300.
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/V.P./Examiner, Art Unit 2111
/GUERRIER MERANT/Primary Examiner, Art Unit 2111 6/22/2026
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