Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 11 & 13 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Xie (US 2021/0019084 A1) in view of Jayaraman (US 2016/0162215 A1) in view of Hsu (US 2003/0009615 A1).
With regards to claim 1, Xie teaches:
An apparatus, comprising: a controller associated with a memory device (0019, The memory system controller), wherein the controller is configured to cause the apparatus to: transition from a first power state to a second power state after a reflow operation (0011, a read voltage can be applied to memory cells to determine whether the memory cell is in a high voltage state representing a bit value of ‘1’ or a low voltage state representing a bit value of ‘0’ (or vice versa). For certain types of memory components, a read operation can change the threshold voltage distribution of the memory cells); refreshing, for a first duration, a first block of non-volatile memory cells of the memory device based at least in part on transitioning from the first power state to the second power state (0028, the refresh operation is consecutive write operations that are to write alternating states at the memory cells), wherein the first block has a first bit error rate that is within a first range of bit error rates (0037, the refresh operation is performed responsive to the difference satisfying the threshold difference.); determine whether a second block of non-volatile memory cells of the memory device has a second bit error rate that is within a second range of bit error rates based at least in part on refreshing the first block (Fig. 3 & 0031, the bit error rate can become larger as shown at point 313. At this point, the memory sub-system can utilize a different read voltage than the read voltage that is represented by the curve 320); and refresh, during a second duration that corresponds to the second range of bit error rates (Fig. 3 & 0030, if a read operation is performed at a time during the specified time period 310, then the refresh operation can be performed to re-write the data at the write unit), the second block of non-volatile memory cells based at least in part on determining that the second bit error rate is within the second range of bit error rates, (Fig. 3 & 0031, the bit error rate can become larger as shown at point 313. At this point, the memory sub-system can utilize a different read voltage than the read voltage that is represented by the curve 320).
Xie fails to teach:
wherein the second duration is associated with an idle duration of the memory device. However, Jayaraman teaches:
wherein the second duration is associated with an idle duration of the memory device. (0004 & 0014, Depending on how fast data is being received from a host device and what types of operations are being performed at the memory, different memory dies may have “idle” time periods and “busy” time periods. The controller 120 may schedule operations to be performed during the idle time periods, such as a write operation, a maintenance operation, an error-checking operation, or a combination thereof, as illustrative, non-limiting examples.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of an apparatus, comprising: a controller associated with a memory device, wherein the controller is configured to cause the apparatus of Xie with the teaching of Jayaraman, which teaches an idle duration of the memory device in order to increase the overall data rate.
With regards to claim 2, Xie teaches the apparatus of claim 1:
wherein the controller is further configured to cause the apparatus to: associate the first block of non-volatile memory cells with the first range of bit error rates (0029, FIG. 3 illustrates bit error rates relative to write to read time differences;) based at least in part on transitioning from the first power state to the second power state (0011, in a high voltage state representing a bit value of ‘1’ or a low voltage state representing a bit value of ‘0’), wherein refreshing the first block of non-volatile memory cells (0037, In the same or alternative embodiments, the data of the write unit is written to a different group of memory cells.) for the first duration is based at least in part on associating the first block of non-volatile memory cells with the first range of bit error rates (0028 & 0031, the refresh operation is consecutive write operations that are to write alternating states at the memory cells; memory sub-system can utilize a different read voltage than the read voltage that is represented by the curve 320).
With regards to claim 3, Xie teaches the apparatus of claim 2:
wherein the controller is further configured to cause the apparatus to: determine that a third block of non-volatile memory cells of the memory device has a third bit error rate that is within a third range of bit error rates (0029 & 0037, FIG.3 illustrates bit error rates relative to write to read time differences; In the same or alternative embodiments, the data of the write unit is written to a different group of memory cells.); and refrain from refreshing, for the first duration, the third block of non-volatile memory cells based at least in part on determining that the third bit error rate of the third block is within the third range of bit error rates.
With regards to claim 4, Xie teaches the apparatus of claim 1:
wherein the controller is further configured to cause the apparatus to: receive a write command associated with the second block of non-volatile memory cells; and assign a timestamp to the second block of non-volatile memory cells based at least in part on receiving the write command (0037, In the same or alternative embodiments, the data of the write unit is written to a different group of memory cells. In some embodiments, the refresh operation is performed when the write to read time difference satisfies the time difference condition), wherein determining whether the second block of non-volatile memory cells has the second bit error rate is based at least in part on assigning the timestamp (0006 & 0011, bit error rates relative to write to read time differences; when data is written to the memory sub-system, a timestamp or other indication of when the data has been written can be recorded.).
With regards to claim 5, Xie teaches the apparatus of claim 4:
wherein the controller is further configured to cause the apparatus to: transition from the first power state to the second power state; determine that the second block of non-volatile memory cells has the second bit error rate based at least in part on the timestamp and transitioning from the first power state to the second power state (0011, a read voltage can be applied to memory cells to determine whether the memory cell is in a high voltage state representing a bit value of ‘1’ or a low voltage state representing a bit value of ‘0’ (or vice versa). when data is written to the memory sub-system, a timestamp or other indication of when the data has been written can be recorded); and determine that the second bit error rate satisfies a threshold value based at least in part on determining that the second block of non-volatile memory cells has the second bit error rate (0037, the refresh operation is performed responsive to the difference satisfying the threshold difference).
With regards to claim 6, Xie teaches the apparatus of claim 5:
wherein the controller is further configured to cause the apparatus to: associate the second block of non-volatile memory cells with the second range of bit error rates based at least in part on determining that the second bit error rate satisfies the threshold value (0031 & 0037, A memory sub-system can utilize a different read voltage than the read voltage that is represented by the curve 320.the refresh operation is performed responsive to the difference satisfying the threshold difference), wherein the second block of non-volatile memory cells is refreshed during the second duration based at least in part on associating the second block of non- volatile memory cells with the second range of bit error rates (0013, when the data was read satisfies a threshold time difference (e.g., the read operation was performed within a specified time period soon after the data was written), then a refresh operation can be performed at the memory cells that stored the data to re-write the data).
With regards to claim 7, Xie teaches the apparatus of claim 6:
wherein the controller is further configured to cause the apparatus to: receive a command from a host system based at least in part on determining that the second bit error rate satisfies the threshold value, wherein the command indicates a third duration for associating the second block of non-volatile memory cells with the second range of bit error rates, wherein the third duration occurs after the first duration and before the second duration (0013, when the data was read satisfies a threshold time difference (e.g., the read operation was performed within a specified time period soon after the data was written), then a refresh operation can be performed at the memory cells that stored the data to re-write the data).
With regards to claim 8, Xie teaches the apparatus of claim 6:
wherein associating the second block of non- volatile memory cells with the second range of bit error rates occurs absent receiving a command from a host system (0037 & 0020, In the same or alternative embodiments, the data of the write unit is written to a different group of memory cells.
The host interface circuitry can convert the commands received from the host system into command instructions to access the memory components).
With regards to claim 9, Xie teaches the apparatus of claim 1:
wherein the controller is further configured to cause the apparatus to: determine that a fourth block of non-volatile memory cells of the memory device has a fourth bit error rate that is within a fourth range of bit error rates based at least in part on determining whether the second block of non-volatile memory cells of the memory device has the second bit error rate; and refresh, during a fourth duration that corresponds to the fourth range of bit error rates, the fourth block of non-volatile memory cells based at least in part on determining that the fourth bit error rate is within the fourth range of bit error rates (0037 & 0013, In the same or alternative embodiments, the data of the write unit is written to a different group of memory cells. When the data was read satisfies a threshold time difference (e.g., the read operation was performed within a specified time period soon after the data was written), then a refresh operation can be performed at the memory cells that stored the data to re-write the data).
With regards to claim 10, Xie teaches the apparatus of claim 9:
wherein the fourth duration is associated with a duration when the memory device is performing a read operation or a write operation (0013, when the data was read satisfies a threshold time difference (e.g., the read operation was performed within a specified time period soon after the data was written), then a refresh operation can be performed at the memory cells that stored the data to re-write the data).
With regards to claim 11, Xie teaches the apparatus of claim 9:
wherein the controller is further configured to cause the apparatus to: perform, during the fourth duration, a write operation on a fifth block of non- volatile memory cells of the memory device concurrent with refreshing the fourth block of non-volatile memory cells (0027, the processing logic performs a refresh operation at the write unit based on the difference between the time when the data of the write unit was written and the other time when the read operation was performed to retrieve the data of the write unit), wherein a cadence associated with performing the write operation and refreshing the fourth block of non-volatile memory cells is adjustable based at least in part on one or more performance criteria of the memory device (0027, the refresh operation can be performed based on whether the difference satisfies a threshold condition).
With regards to claim 12, Xie teaches the apparatus of claim 1:
wherein the second duration is associated with an idle duration of the memory device (0011 & 0013, data is written to the memory sub-system, a timestamp or other indication of when the data has been written can be recorded. operation was performed within a specified time period soon after the data was written).
With regards to claim 13, Xie teaches the apparatus of claim 1. Xie fails to teach:
wherein the first block comprises a production state awareness (PSA) block and the second block comprises a non-PSA block.
However, Hsu teaches:
wherein the first block comprises a production state awareness (PSA) block and the second block comprises a non-PSA block (Hsu: 0020, A primary sense amplifier block PSA is provided for each micro-cell and a secondary sense amplifier block SSA is provided for each bank).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of an apparatus, comprising: a controller associated with a memory device, wherein the controller is configured to cause the apparatus of Xie with the teaching of Hsu, which teaches a production state awareness (PSA) block and a second non-PSA block in order to prioritize refreshing certain blocks at power-on, and other blocks at a later time.
With regards to claim 14, Xie teaches and corresponds to claim 1 and is analyzed accordingly.
With regards to claim 15, Xie teaches the non-transitory computer-readable medium of claim 14 and corresponds to claim 2 as analyzed accordingly.
With regards to claim 16, Xie teaches the non-transitory computer-readable medium of claim 15 and corresponds to claim 3 as analyzed accordingly.
With regards to claim 17, Xie teaches the non-transitory computer-readable medium of claim 14 and corresponds to claim 4 as analyzed accordingly.
With regards to claim 18, Xie teaches the non-transitory computer-readable medium of claim 17 and corresponds to claim 5 as analyzed accordingly.
With regards to claim 19, Xie teaches the non-transitory computer-readable medium of claim 18 and corresponds to claim 6 as analyzed accordingly.
With regards to claim 20, Xie teaches and corresponds to claim 1 as analyzed accordingly.
Response to Arguments
Applicant's arguments filed 01/05/2026 regarding the prior art rejections of Claims 1, 14, and 20 have been fully considered, but they are not persuasive.
The Remarks argue that:
Independent Claims 1, 14, and 20
Without conceding the merits of the rejection of independent claims 1, 14, and 20 under 35 U.S.C. § 102-and solely to expedite prosecution-Applicant has amended independent claims 1, 14, and 20 to include features previously recited in dependent claim 12. For example, independent claim 1 has been amended to recite, in part:
transition from a first power state to a second power state after a reflow operation; refreshing, for a first duration, a first block of non-volatile memory cells
of the memory device based at least in part on transitioning from the first power state to the second power state, wherein the first block has a first bit error rate
that is within a first range of bit error rates;
determine whether a second block of non-volatile memory cells of the
memory device that is different than the first block has a second bit error rate that is within a second range of bit error rates based at least in part on refreshing the
first block; and
refresh, during a second duration that corresponds to the second range of
bit error rates, the second block of non-volatile memory cells based at least in part on determining that the second bit error rate is within the second range of bit error rates, wherein the second duration is associated with an idle duration of the memory device.
Independent claims 14 and 20 have been amended to include similar or complementary features. Xie does not disclose all the features of amended independent claims 1, 14, and 20.
Xie is directed to "refresh operation can be performed for the data of the write unit at the memory sub-system based on the difference between the time of the performance of the read operation and the another time of the performance of the write operation." Xie, Abstract. For example, at the portions cited by the Office Action, Xie discusses a "conventional memory sub- system can perform a read operation to retrieve data stored at memory components of the memory sub-system." Id. [0011]. At other portions cited by the Office Action, Xie describes "performing a refresh operation based on a write to read time difference," for example, "when data is written to the memory sub-system, a timestamp or other indication of when the data has been written can be recorded," and "[s]ubsequently, a read operation can be performed to retrieve the data." Id. [0013]. At other portions cited by the Office Action, Xie discusses "the refresh operation can be multiple consecutive write operations that are each performed to re-write the same data at the memory cells." Id. [0028]. Further, at portions cited by the Office Action, Xie describes that "[i]n response to determining that the write to read time difference satisfies the time difference condition . . . the processing logic performs a refresh operation at the write unit."Id. [0037].
In the rejection of dependent claim 12, the Office Action alleges that the time between the read and write operations of Xie is relevant to "the second duration is associated with an idle duration of the memory device." See Office Action, pp. 7-8 (citing Xie [0011] and [0013]).
Additionally, in the rejection of previously-presented independent claim 1, the Office Action alleges that "the refresh operation can be multiple consecutive write operations" is relevant to "a first duration." See Office Action, p. 2 (citing Xie [0028]). But the Office Action has not shown the cited features of Xie to be the same as those recited in amended independent claim 1.
The Office Action has not shown Xie to be relevant to "a first duration" let alone "a second duration [which] is associated with an idle duration of the memory device." First, the Office Action has not shown "the refresh operation can be multiple consecutive write operations that are each performed to re-write the same data at the memory cells" of Xie to disclose a first duration. Instead, the Office Action merely points to a portion of Xie that discusses consecutive write operations, without discussion how the consecutive write operations are relevant to a first duration.
Second, even if the Office Action shows that consecutive write operations are relevant to a first duration-which Applicant does not concede-the Office Action has not shown the time between the read and write operations to disclose "the second duration is associated with an idle duration of the memory device," as recited in amended independent claim 1. The Office Action has not shown how "performing a refresh operation based on a write to read time difference," for example, "when data is written to the memory sub-system, a timestamp or other indication of when the data has been written can be recorded," discloses and idle duration. Instead, the portions of Xie cited by the Office Action discuss a timestamp and "performing a refresh operation based on a write to read time difference," neither of which the Office Action has shown to be idle. Thus, Xie does not disclose at least "the second duration is associated with an idle duration of the memory device," as recited in amended independent claim 1.
Further, the Office Action alleges that the "[i]n response to determining that the write to read time difference satisfies the time difference condition . .. the processing logic performs a refresh operation at the write unit" of Xie discloses "the first block has afirst bit error rate that is within a first range of bit error rates," as recited in previously-presented independent claim 1. Office Action, p. 2 (citing Xie [0037]). But the cited features of Xie are not the same as those recited in amended independent claim 1.
The Office Action has not shown how "the time difference condition" of Xie is relevant to "the first block has a first bit error rate that is within a first range of bit error rates." The time difference condition of Xie is described as "an amount of time that has elapsed since a write operation was performed .. until the read operation was performed at the write unit" and "the processing logic determines whether the write to read time difference satisfies a time difference condition." Xie [0036]. The Office Action has not shown how a time difference is relevant to "a first bit error rate that is within a first range of bit error rates" at least because a time difference has not been shown to disclose a bit error rate. Further, the Office Action has not shown how a single time difference is relevant to "a first bit error rate that is within afirst range of bit error rates." Thus, Xie does not disclose at least "the first block has a first bit error rate that is within a first range of bit error rates," as recited in amended independent claim 1.
Therefore, for at least these reasons, amended independent claim 1 is allowable over Xie. Amended independent claims 14 and 20 are likewise allowable for at least similar reasons.
Accordingly, Applicant requests that the rejection of independent claims 1, 14, and 20 under 35 U.S.C. § 102 be reconsidered and withdrawn.
Dependent Claims 2-12 and 15-19
Dependent claims 2-12 and 15-19 each depend from one of independent claims 1 and 14 and are therefore allowable for at least the same reasons that independent claims 1 and 14 are allowable. Dependent claims 2-12 and 15-19 also recite allowable features that have not been shown to be disclosed by Xie.
Accordingly, for at least these reasons, Applicant requests that the rejection of dependent claims 2-12 and 15-19 under 35 U.S.C. § 102 be reconsidered and withdrawn.
35 U.S.C. '103
The Office Action rejected claims 13 under 35 U.S.C. § 103 over the stated combinations of Xie and Hsu.
Factual findings made by the Office are the "necessary underpinnings to establish
obviousness." MPEP § 2141(II). The Office must set forth "the relevant teachings of the prior art relied upon." MPEP § 2142. In KSR International Co. v. Teleflex Inc., the Supreme Court noted that the analysis supporting a rejection under 35 U.S.C. § 103 must be made explicit. See 550 U.S. 398, 418 (2007); MPEP § 2142. "[O]bviousness [also] requires a suggestion of all limitations in a claim." In re Wada and Murphy, Appeal 2007-3733 (citing CFM, Inc. v. YieldUP International Corp., 349 F.3d 1333, 1342 (Fed. Cir. 2003)).
Dependent Claim 13
Dependent claim 13 depends from independent claim 1 and is therefore allowable for at least the same reasons that independent claim 1 is allowable. Dependent claim 13 also recites allowable features that have not been shown to be taught or suggested by Xie and Hsu, alone or in any combination.
Accordingly, for at least these reasons, Applicant requests that the rejection of dependent claim 13 under 35 U.S.C. § 103 be reconsidered and withdrawn.
Applicant believes all claims now pending in this Application are in condition for allowance. The issuance of a formal Notice of Allowance at an early date is therefore respectfully requested.
Applicant files this response without conceding the merits of the positions in the Office Action and solely to facilitate prosecution. Applicant reserves the right to supplement, amend, and/or modify the response. Nothing in the response is to be construed as a waiver, an acquiescence, or an admission of any kind, including but not limited to the interpretation of any cited reference(s) or any claim scope. Applicant further reserves the right to present additional arguments, evidence, and/or amendments in any subsequent communications and/or proceedings. Applicant reserves the right to pursue claims of broader or similar scope as those originally filed in this application, a continuing application, and/or other application after allowance of the present application. Any amendment, argument, and/or claim cancellation is not to be construed as abandonment and/or disclaimer of any subject matter, interpretation, position, and/or argument.
The Examiner respectfully disagrees Xie is relevant to first and second durations of the memory device as mentioned in the abstract of Xie. (Abstract, A read operation can be performed to retrieve data of a write unit at a memory sub-system. An indication of a time of the performance of the read operation can be received. Another indication of another time of a performance of a write operation to store the data of the write unit at the memory sub-system can be received. A difference between the time of the performance of the read operation and another time of the performance of the write operation can be determined.)
The Examiner agrees Xie alone doesn’t teach a second duration is associated with an idle duration of the memory device. However, with the new prior art of Jayaraman one skilled in the art could conclude the invention. (Jayaraman: 0014, The controller 120 may schedule operations to be performed during the idle time periods, such as a write operation, a maintenance operation, an error-checking operation, or a combination thereof, as illustrative, non-limiting examples.)
The Examiner respectfully disagrees the office action does show how "the time difference condition" of Xie is relevant to "the first block has a first bit error rate that is within a first range of bit error rates." Additionally, after reviewing Xie’s patent documents, one skilled in the art could see Xie’s relevancy to the “first bit error rate.” (Xie: 0020 & 0030, FIG. 3 illustrates bit error rates relative to write to read time differences in accordance with some embodiments of the present disclosure. In some embodiments, the refresh operation component 113 of FIG. 1 can perform a refresh operation based on the write to read time difference. As shown in FIG. 3, the bit error rate for a particular read voltage is shown by the curve 320. The bit error rates for the same read voltage are illustrated as the write to read time difference for a write unit changes.)
For at least the same reasons discussed with respect to amended claims 1, 14 & 20 are considered but also rejected.
Claims 2 – 11 & 13 which depend from amended claim 1, have been considered and rejected.
Claims 15 – 19 which depend from amended claim 14, have been considered and rejected.
Prior Art Made of Record
The prior art mode of record and not relied upon is considered pertinent to
Applicant’s disclosure:
Franklin (US 2018/0285007 A1): A non-volatile memory device is configured to receive a
refresh command from a controller over a bus. A non-volatile memory device is
configured to perform one or more maintenance operations.
Conclusion
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/V.P./Examiner, Art Unit 2111
/GUERRIER MERANT/Primary Examiner, Art Unit 2111 02/03/2026