DETAILED ACTION
Claims 1, 13, 20 are amended. Claims 6, 9, 11, 18 are canceled. Claims 1-5, 7-8, 10, 12-17, 19-20 are pending.
Priority: 11/16/2022(Provisional)
Assignee: Micron
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/20/2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1-5, 7-8, 10, 12-17, 19-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
1.Amended Claims 1, 13, 20 are rejected for reciting a limitation that is unclear, vague and indefinite.
Claim 1 recites, ‘wherein the accumulated data is received from the second volatile memory device based….on a size of the accumulated data satisfying a threshold quantity of data that corresponds to a quantity of data stored by a respective first page of each physical block of a group of physical blocks….’.
However, spec, Para-0132 recites, ‘transmitting, to the host system, a request for the host system to allocate a portion of the second volatile memory device to the memory system for storage and receiving, from the host system’.
The claim and the spec recite a disconnect, i.e. they establish a host buffer allocation step that is unlinked from the accumulation threshold step. For example, it is unclear what happens if the host allocates a small 32 KB buffer, but the threshold (the pageline size) is 128 KB.
Since the spec does not disclose that the allocated host buffer size is tied to the threshold, the relationship between the allocation step and the accumulation step is left mathematically disconnected.
Crucially, since the size of the host buffer is not communicated by the controller to the host, the host has no input variable from which to calculate when to stop accumulating. The host is effectively operating in a vacuum.
In essence since the mathematical or logical link between the size of the buffer the host allocated and the threshold used to stop accumulating data is unclear, claim 1 is rejected as being indefinite. Claims 13, 20 also have a similar issue.
Dependent claims 2-5, 7-8, 10-19, 20 are rejected for failing to cure the deficiency from their respective parent claim by dependency.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4, 10, 12-16, 20 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Byun (20200174690) in view of Wells et al (20230289078), Huang et al (20110149650) and Gorobets et al (20050144365).
As per Claim 1, Byun discloses an apparatus (Byun, [0030,0031 - Fig. 1 shows a data processing system 100 including a memory system 110, wherein the data processing system 100 includes host 102 and memory system 110]), comprising:
a first non-volatile memory device (Byun, [0040 - In Fig. 1, memory device 150 includes a plurality of memory blocks 152]; [0041 - Memory device 150 includes a plurality of memory dies, and each memory die includes planes. Memory device 150 is a flash memory having a 3D stack structure]; [0126 – In Fig. 10, memory device 6340 includes a plurality of nonvolatile memories/NVMs, thereby implying that the first NVM is the first NVM memory device]);
a second non-volatile memory device (Byun, [0126 – In Fig. 10, memory device 6340 includes a plurality of nonvolatile memories/NVMs, thereby implying that the second NVM is the second NVM memory device]);
a controller (Byun, [Fig. 1: controller 130]) comprising a first volatile memory device (Byun, [0048 – In Fig. 1, memory 144 is dynamic random access memory/DRAM]),
the controller being coupled with the first non-volatile memory device and the first volatile memory device (Byun, [0044 – In Fig. 1, controller 130 includes host interface 132, processor 134, memory interface 142, and memory 144, all coupled to each other via an internal bus]; [0038 - Controller 130 and the memory device 150 may be integrated into a single semiconductor device]),
wherein the controller (Byun, [Fig. 1: controller 130]) is configured to cause the apparatus to:
initiate a folding operation (Byun, [0016 - Fig. 6A shows a garbage collection operation which facilitates the folding operation]) to transfer data from the first non-volatile memory device to the second non-volatile memory device (Byun, [0082 – In Fig. 6A, processor 134 of controller 130 searches a plurality of memory blocks included in memory device 150 to select at least one sacrificial memory block 610/first NVM from the plurality of memory blocks]; [0009 - The sacrificial data is valid data stored in the sacrificial memory block, thereby implying the start of the folding operation; This is similar to Para-0086 of the spec]);
transfer a first portion of the data from the first non-volatile memory device to the first volatile memory device (Byun, [0087 – In Fig. 6B, step S603, processor 134 loads the valid data, i.e., sacrificial data, stored in the sacrificial memory block/first NVM to memory 144/first volatile memory]) as part of the folding operation (Byun, [Figs. 5, 6A-6B, 7A-7C]);
transmit, as part of the folding operation (Byun, [Fig. 6A]), the first portion from the first volatile memory device (Byun, [Fig. 1: memory 144/first volatile memory]) to a second volatile memory device (Byun, [Fig. 6A: Integrated Memory 104/second volatile memory]; [0034 - Integrated memory 104 is a unified memory/UM in host 102 that includes a RAM]) of a host system (Byun, [Fig. 6A: host 102]) based at least in part on a size of the first portion of the data equaling a storage capacity of the first volatile memory device (Byun, [0089 - When the available capacity of the integrated memory 104 is equal to the size of the sacrificial data, ‘Yes’ in step S605, processor 134 provides the sacrificial data to host 102 under the control of the processor 134 in step S607]);
receive, as part of the folding operation (Byun, [Figs. 7A-7C show garbage collection operation which facilitates the folding operation]) and at the first volatile memory device (Byun, [Fig. 7C: step S701]) from the second volatile memory device (Byun, [Fig. 6A: Integrated Memory 104/RAM in host 102]), accumulated data comprising the first portion of the data and a second portion of the data (Byun, [0106 - In step S701, the host 102 may provide the controller 130 with the previous sacrificial data stored in the integrated memory 104 as target data]),
write, as part of the folding operation (Byun, [Fig. 7C]), the accumulated data to the second non-volatile memory device (Byun, [Fig. 7A]; [Fig. 10]) that comprises a set of multiple-level memory cells for storing four or more bits of information (Byun, [0108 - In Fig. 7C, step S705, processor 134 stores the sorted target data in a target memory block in memory device 150]; [0061 - Memory device 150 includes a plurality of quadruple-level cell/QLC memory blocks. The QLC memory block includes a plurality of pages including memory cells each capable of storing 4-bit data]).
Byun discloses aligned physical blocks and each block includes a plurality of physical pages.
Wells discloses a negotiation: the controller defines the NVM layout by notifying the host of the superblock/virtual block size, the host enforces the threshold rule by sending a stream alignment command targeting an empty superblock, and the controller confirms the alignment for accumulated host data, as follows,
receive, as part of the folding operation (Wells, [0031 – In Fig. 3, method 300 is performed by the storage device 100/controller 120 and host 101]) and at the first volatile memory device from the second volatile memory device (Wells, [0032 – In Fig. 3, at step 305, controller 120 notifies host 101 the size of a superblock/virtual block]; [0034 - At step 310, host 101 determines the size of the superblock]; [0035 - At step 315, host 101 notifies storage device 100 via a command, that a stream of data is to be aligned with a superblock, the size of which is determined at 310]; [0038 - At step 320, controller 120 determines that the stream of data is to align with a superblock, thereby confirming the match]), accumulated data (Wells, [0039 - At step 325, host 101 sends the data of the stream and logical addresses corresponding to the stream to storage device 100]),
wherein the accumulated data is received from the second volatile memory device based at least in part on a size of the accumulated data satisfying a threshold quantity of data (Wells, [0035 - The ‘stream alignment command’ from the host at step 315 establishes the threshold rule. By indicating that the stream must align with the superblock size, the host holds accumulated data in its memory until it matches that specific flash threshold]) that corresponds to a quantity of data stored by a respective first page of each physical block of a group of physical blocks (Wells, [0037 - Host 101 notifies storage device 100 using a stream alignment command that indicates that a stream of data should align with a superblock that was previously empty; It is well-known that NAND flash cells cannot be overwritten in place. An entire block must be erased before it can be written to. Due to this, writing data into a ‘previously empty’ or freshly erased physical block requires writing to the first physical page of that block first]) included in a virtual block of the second non-volatile memory device (Wells, [0041 - The host 101 has the capability of completely aligning a data stream to a superblock; It is well-known that NAND flash does not allow writing to page 2, 3, or 4 of an empty NAND flash block without first filling page 0 and page 1. Therefore, if the sequence explicitly states that the host data stream is aligning with and initializing a previously empty superblock, the very first chunk of that accumulated data stream must physically correspond to the first page of each physical block making up that superblock/virtual block]),
wherein the virtual block comprises the group of physical blocks (Wells, [0011 - A superblock/virtual block/metablock structure refers to a plurality of blocks grouped together]), and wherein a physical block comprises two or more physical pages (Wells, [0018 – In Fig. 1, each of the dies 142a-142d, 144a-144d, 146a-146d, and 148a-148d has one or more planes. Each plane has multiple blocks, and each block has multiple pages]) of the second non-volatile memory device (Wells, [0018 - NAND flash memory devices refer to multiple NAND flash memory devices or dies within non-volatile memory 140]);
The sequence of notifying size, verifying alignment rules, and sending the data satisfies the logic of a threshold-driven, geometrically aligned flash/NVM write. When the host subsequently sends the accumulated data and since it has been designated via the stream alignment parameter to target an unused superblock, the stream is aligned to fit a ‘previously empty superblock’ such that the initial data populates the ‘first page of each physical block included in that virtual block’.
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the stream alignment negotiation of Wells into the host-based processing system of Byun, for the benefit of the NVM communicating to the host the size of a superblock. A stream of data is aligned with the superblock. The host is therefore aware of the superblock size and can select streams to align to the superblock. The stream alignment threshold ensures the accumulated data is a perfect fit for the empty virtual block's first physical pages (Wells, 0014).
Huang discloses receiving as part of the folding operation the accumulated data at the first volatile memory device of the controller from the host as follows,
receive, as part of the folding operation (Huang, [Fig. 11]; [0028 - A folding operation includes reading the portions of the data from multiple locations in the first section into the read/write registers and performing a multi-state programming operation of the portions of the data from the read/write registers into a location the second section of the non-volatile memory/second NVM]; [Figs. 23-27 give examples how to combine data folding operation with writes to the binary portion of the memory]) and at the first volatile memory device from the second volatile memory device (Huang, [0128 – In Fig. 20, data is transferred from host 501 onto memory 503, where it is initially stored on the controller resident volatile buffer memory RAM 511/smaller size]), accumulated data (Huang, [0020 - The mapping data is buffered in RAM 511; Here the buffering implies receiving ‘accumulated data’ from the host]),
write, as part of the folding operation (Huang, [Fig. 11]; [0127 – In on-chip data folding, data written into a binary section of the memory is repackaged and written into a multi-state format]), the accumulated data (Huang, [0019 - Consolidating the valid sectors among the various blocks and rewriting the sectors after rearranging them in logically sequential order]) to the second non-volatile memory device (Huang, [Fig. 20: non-volatile memory 513]) that comprises a set of multiple-level (Huang, [0138 - In Fig. 20, for balanced mode, interspersing writes to D1 memory between the foggy and fine and fine and foggy phases of the multi-level programming used in the folding process]) memory cells for storing four or more bits of information (Huang, [0081 - In D3, each cell stores 3 bits, .i.e. low, middle and upper bits, and there are 8 regions. In D4/QLC, there are 4 bits and 16 regions]; [0119 - All Logical Groups in the triplet will be fully consolidated to Virtual Update Blocks in D1 memory 301 before folding to D3 memory 303]; [0128 – In Fig. 20, from RAM 511 the data is then written into NVM 513/second, first into the binary section D1 515 and then on into the MLC section D3 517. In the on-chip D1 to D3 folding operation, same read write registers and other peripheral circuitry is used for both the initial D1 write operation and the folding operation]; [0118 - Update Blocks that consist of three D1/Binary blocks where a full image of all data to be programmed to D3 block is created prior to a folding operation of copying data from the D1 blocks to a D3 block using a foggy-fine programming operation; Here foggy-fine programming is a two-step process used in multi-level cell/MLC NAND, particularly QLC/quad-level cell NAND which stores 4 bits per cell]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the folding operation of Huang into the host-based processing system of Byun, Wells for the benefit of receiving data from a host, storing the received data in the buffer memory, then transferring from the buffer memory to into read/write registers of the non-volatile memory circuit and a binary write operation of the data is then performed from the read/write registers to the first section of the non-volatile memory circuit and then folds portions of the data from the first section of the non-volatile memory to the second section of the non-volatile memory (Huang, 0028);
Gorobets discloses receiving the accumulated data which enters the controller RAM, and the controller routes it across different physical flash channels, dies, and planes simultaneously as follows,
receive (Gorobets, [0468 – In Fig. 32A, step 1112: Receiving host data packaged in logical units]), as part of the folding operation and at the first volatile memory device (Gorobets, [Fig. 1: RAM 130]) from the second volatile memory device (Gorobets, [Fig. 2: host 10, host-side memory manager]), accumulated data (Gorobets, [Fig. 24A: Update Block Sequential with padding/second data]; [0028 - A normal consolidation operation consolidates into a consolidation block the current versions of all logical units of a logical group residing among an original block and an update block]; [Figs. 28-29 show consolidation/accumulated data]]) comprising the first portion of the data and a second portion of the data (Gorobets, [0412 - Fig. 24A shows the plane-aligned sequential update with padding/second data; Here the valid data is the first portion]; [0421 - Fig. 24C shows the plane aligned chaotic/non-sequential update with padding/second data; Here the valid data is the first portion]),
wherein the accumulated data (Gorobets, [0142 - The consolidated update block will be in logically sequential order and can be used to replace the original block. Under some predetermined condition, the consolidation process is preceded by one or more compaction processes]; [0465 - Fig. 32A shows initial update operation that results in a consolidation operation]) is received from the second volatile memory device (Gorobets, [0137 – In Fig. 6, interface 110 allows the metablock management system to interface with a host]) based at least in part on a size of the accumulated data satisfying a threshold quantity of data (Gorobets, [Fig. 21: Metapage MP0]; [0386 - When combining multiple planes, a maximum aggregated unit of parallel read or write is a metapage/pageline which is constituted by a page from each of the multiple planes; This implies that the threshold quantity of data corresponds to the total capacity of a single metapage, e.g., MP0. This is similar to Fig. 1 of the spec]) that corresponds to a quantity of data stored by a respective first page of each physical block (Gorobets, [0121 - Figs. 2, 3A(i)-3A(iii) show the mapping between a logical group and a metablock/virtual block. The metablock has N physical sector/pages for storing N logical sectors of data of a logical group]; [0387 – In Fig. 21, when the logical pages are filled in logically sequential order, the planes are visited in cyclic order with the first page in the first plane, the second page in the second plane, etc. After the last plane is reached, the filling returns cyclically to start from the first plane again in the next metapage]; [0528 - An index of logical units recorded in a block is stored in nonvolatile memory after every N writes]) of a group of physical blocks (Gorobets, [0018 - Each physical group/metablock is erasable as a unit and can be used to store a logical group of data]) included in a virtual block of the second non-volatile memory device (Gorobets, [Fig. 2: Flash memory 200/second NVM]; [0386 - Typically a logical unit is a sector of size 512 bytes. A page is a maximum unit of parallel read or write in a plane. A logical page contains one or more logical units]; [0391 - In Fig. 21, a metapage is formed by multiple logical pages, one in each plane]; [0386 - A metapage such as MP0 has four pages, one from each of the planes, P0, P1, P2 and P3, storing in parallel logical pages LP0, LP1, LP2, LP3, thereby implying Logical Page 0/LP0 maps to physical Page 0 of Physical Block A, LP1 maps to physical Page 0 of Block B, and so on]);
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the metapage of Gorobets into the host-based processing system of Byun, Wells, Huang for the benefit of using a metapage or virtual block formed by multiple logical pages, one in each plane. Each logical page may consist of one or more logical units. As data are being recorded logical unit by logical unit into a block across the planes, each logical unit will fall in one of the four memory plane (Gorobets, 0391).
As per Claim 2, the rejection of claim 1 is incorporated and Byun discloses,
wherein the controller (Byun, [Fig. 1: controller 130]) is further configured to cause the apparatus to:
scan (Byun, [Fig. 6B, step S601]), prior to transferring the first portion of the data from the first non-volatile memory device to the first volatile memory device, one or more source blocks of the first non-volatile memory device for the data (Byun, [0009 - A memory system configured to select/scan at least one sacrificial memory block from a plurality of memory blocks]; [0086 – In Fig. 6B, step S601, on the basis of the number of valid data stored in each of the plurality of memory blocks in memory device 150, processor 134/controller selects the sacrificial memory block, thereby implying scanning source blocks of the first non-volatile memory device for valid data]) based at least in part on page validity information corresponding to logical-to-physical translations associated with the one or more source blocks (Byun, [0128 – In Fig. 10, buffer memory 6325/first volatile memory temporarily stores metadata of flash memories NVMs, for example, map data including a mapping table]), wherein the first portion of the data is stored at the one or more source blocks (Byun, [0009 - The sacrificial data is valid data stored in the sacrificial memory block]).
As per Claim 3, the rejection of claim 1 is incorporated and Byun, Wells, Huang, Gorobets disclose,
wherein, to write the accumulated data to the second non-volatile memory device (Huang, [0107 - In Fig. 11, NVM 200/2nd NVM is partitioned into two portions. The first portion 202 has the memory cells operating as a main memory for user data in either MLC or binary mode. The second portion 204 has the memory cells operating as a cache in a binary mode. Thus, the memory 200 is partitioned into a main memory 202 and a binary cache]), the controller is configured to cause the apparatus to:
perform a first stage of a write operation on a subset of the set of multiple-level memory cells (Huang, [0028 - Receiving data from a host and storing the received data in the buffer memory. The data is then transferred from the buffer memory into read/write registers of the non-volatile memory/2nd NVM and a binary write operation of the data is then performed from the read/write registers to the first section of the non-volatile memory]);
perform a second stage of the write operation on the subset of the set of multiple-level memory cells after the first stage (Huang, [0028 - The method then subsequently folds portions of the data from the first section of the non-volatile memory to the second section of the non-volatile memory]), wherein the accumulated data (Huang, [0023 - The cache buffers the data between a fast host and a slower MLC memory and for accumulation to write to a block]) is written to the second non-volatile memory device based at least in part on the second stage (Huang, [0028 - A folding operation includes reading the portions of the data from multiple locations in the first section into the read/write registers and performing a multi-state programming operation of the portions of the data from the read/write registers into a location the second section of the non-volatile memory/2nd NVM]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the folding operation of Huang into the host-based processing system of Byun, Wells, Gorobets for the benefit of using multi-state programming operations that include a first phase and a second phase and one or more binary write operations are performed between the phases of the multi-state programming operations (Huang, 0028).
As per Claim 4, the rejection of claim 3 is incorporated and Byun, Wells, Huang, Gorobets disclose,
wherein, to receive the accumulated data (Gorobets, [0144 - The update block is allocated when a command is received from the host to write a segment of one or more sectors of the logical group for which an existing metablock has been storing all its sectors intact]; [0028 - A normal consolidation operation consolidates/accumulated data into a consolidation block the current versions of all logical units of a logical group residing among an original block and an update block]), the controller (Gorobets, [Fig. 1: controller 10]) is configured to cause the apparatus to:
receive the accumulated data from the second volatile memory device a first time (Gorobets, [0144 - For the first host write operation, a first segment of data is recorded on the update block]), wherein the first stage is performed using the accumulated data received at the first time (Gorobets, [0144 - Since each host write is a segment of one or more sector with contiguous logical address, it follows that the first update is always sequential in nature]);
receive the accumulated data from the second volatile memory device a second time (Gorobets, [0144 - In subsequent host writes, update segments within the same logical group are recorded in the update block in the order received from the host. A block continues to be managed as a sequential update block whilst sectors updated by the host within the associated logical group remain logically sequential. All sectors updated in this logical group are written to this sequential update block, until the block is either closed or converted to a chaotic update block]), wherein the second stage is performed using the accumulated data received at the second time (Gorobets, [0120 – In Figs. 1-2, a memory-side memory manager is implemented in controller 100 of memory system 20 to manage the storage of the data of host logical sectors among metablocks of flash memory 200/second NVM]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the timing of Gorobets into the host-based processing system of Byun, Wells, Huang for the benefit of utilizing memory devices having a specific time allowance to complete a certain operation. For example when a host writes to a memory device, it expects the write operation to be completed within a specified time, known as write latency. While the memory device is busy writing the data from the host, it signals a busy state to the host. If the busy state lasts longer than the write latency period, the host will time-out the write operation and register an error (Gorobets, 0449).
As per Claim 10, the rejection of claim 1 is incorporated and Byun discloses,
wherein the size of the first portion equals a size of the storage capacity of the first volatile memory device (Byun, [0082 – In Fig. 6A, processor 134 selects a memory block having the smallest number of valid data among the plurality of memory blocks as the sacrificial memory block 610. Then, processor 134 reads valid data/sacrificial data and stores it in memory 144/first volatile memory of controller 130]; [0083 - When available capacity of integrated memory 104 is equal to the size of the sacrificial data, the processor 134 provides host 102 with the stored sacrificial data, thereby implying that the size of the first portion at least equals the size of the storage capacity of the first volatile memory device]) allocated for transfer operations (Byun, [Fig. 6A]) associated with writing data to multiple-level memory cells for storing four or more bits of information (Byun, [0060 – In Fig. 2, each of memory cells in memory blocks BLOCK0 to BLOCKN−1 is a multi-level cell/MLC storing multi-bit data]; [0061 - Memory device 150 includes a plurality of quadruple-level cell/QLC memory blocks. The QLC memory block includes a plurality of pages including memory cells each capable of storing 4-bit data]),
the first portion is transmitted to the host system based at least in part on the first portion equaling the storage capacity of the first volatile memory device (Byun, [0083 – In Fig. 6A, processor 134 compares an available capacity of the integrated memory 104/second volatile memory with a size of the sacrificial data stored in the memory 144/first volatile memory, thereby implying that the first data is transmitted to the host based on equaling the storage capacity of the first volatile memory device]).
As per Claim 12, the rejection of claim 1 is incorporated and Byun discloses,
wherein the first non-volatile memory device and the second non-volatile memory device are the same non-volatile memory device (Byun, [0040 - In Fig. 1, memory device 150 includes a plurality of memory blocks 152]; [0041 - Memory device 150 include a plurality of memory dies, and each memory die includes a plurality of planes. The memory device 150 may be a flash memory having a 3D stack structure]).
Huang clarifies,
wherein the first non-volatile memory device and the second non-volatile memory device are the same non-volatile memory device (Huang, [0023 – A flash memory system operating with a cache and operating in mixed MLC/multi-level cell and SLC/single-level cell modes and with the SLC memory operating as a dedicated cache. The cache is mainly to buffer the data between a fast host and a slower MLC memory and for accumulation to write to a block]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the mixed MLC, SLC modes of Huang into the host-based processing system of Byun, Wells, Gorobets for the benefit of
the SLC memory cache to buffer the data between a fast host and a slower MLC memory and for accumulation to write to a block (Huang, 0023).
As per Claim 13, it is similar to claim 1 and therefore the same rejections are incorporated.
As per Claim 14, it is similar to claim 2 and therefore the same rejections are incorporated.
As per Claim 15, it is similar to claim 3 and therefore the same rejections are incorporated.
As per Claim 16, it is similar to claim 4 and therefore the same rejections are incorporated.
As per Claim 20, it is similar to claims 1, 13 and therefore the same rejections are incorporated.
Claims 5, 7, 17, 19 are rejected under AIA 35 U.S.C. 103(a) as being unpatentable over Byun (20200174690) in view of Wells et al (20230289078), Huang et al (20110149650), Gorobets et al (20050144365) and Szubbocsev (20170300422).
As per Claim 5, the rejection of claim 1 is incorporated and Byun, Wells, Huang, Gorobets disclose,
wherein the controller (Gorobets, [Fig. 1: controller 10]; [0141 – In Fig. 2, update block manager 150 handles the update of logical groups]) is further configured to cause the apparatus to:
update, at the first volatile memory device based at least in part on writing accumulated data (Gorobets, [Fig. 24A]; [Figs. 28-29 show consolidation/accumulated data]; [0272 - Logical to physical address records for recently written sectors are temporarily held in RAM/first volatile memory]; [0372 - Data update management operations are performed in RAM on the ABL, the CBL and the chaotic sector list]), a first set of logical to physical mappings associated with the accumulated data in accordance with the accumulated data being written to the second non-volatile memory device (Gorobets, [0272 – In Fig. 2, the logical to physical address translation module 140 is responsible for relating a host's logical address to a corresponding physical address in flash memory. Mapping between logical groups and physical groups/metablocks are stored in a set of table and lists distributed among the nonvolatile flash memory 200/second NVM and the volatile but more agile RAM 130]);
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the mapping of Gorobets into the host-based processing system of Byun, Wells, Huang for the benefit of having the hierarchy of address records for logical groups include the open update block list, the closed update block list in RAM and the group address table/GAT maintained in flash memory (Gorobets, 0272).
Szubbocsev discloses,
transmit the first set of logical-to-physical mappings (Szubbocsev, [Fig. 4A: step 414, transfer selected zone/mapping table to host]) from the first volatile memory device (Szubbocsev, [Fig. 1: Memory 132; Embedded memory 132 is DRAM in ASIC controller 106. It is well-known that ASIC controllers get assembled with SRAM or DRAM]) to the second volatile memory device (Szubbocsev, [Fig. 1: host memory 105, DRAM]) based at least in part on a size of the first set of logical-to-physical mappings equaling the storage capacity of the first volatile memory device (Szubbocsev, [0024 – In Fig. 1, controller 106 retrieves the first mapping table 134a from the main memory 102 in a sequence of exchanges. During the exchanges, a portion, or zone, of physical to logical address mappings is read out into the embedded memory 132/first volatile memory, thereby implying that the size of the first L2P mappings/134a is equal to the capacity of the first volatile memory device 132]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the host device interface of Szubbocsev into the host-based processing system of Byun, Wells, Huang, Gorobets for the benefit of enabling a host device to read from the memory of the memory device (Szubbocsev, 0011).
As per Claim 7, the rejection of claim 5 is incorporated and Byun, Wells, Huang, Gorobets, Szubbocsev disclose,
wherein the controller (Huang, [Fig. 1: controller 100]) is further configured to cause the apparatus to:
determine that the folding operation has been completed (Huang, [0140 – In Fig. 21, the bottom line shows the stages of D1 to D3 folding process. Three D1 blocks are available for folding into one D3 block, so that all D1 data pages are available for folding to D1. The fine phase then follows, again the word lines x, y, and z are loaded into the read/write latches and programmed into the D3 word line for the fine write. This completes the first, foggy, fine stages and the data can then be read out]; [0142 – In Fig. 21, the transfers at 735 and 737 are pipelined with the fine programming phase, as were the transfers at 731 and 733 hidden behind the initial phases 701-707, which provided the data subsequently transferred out of RAM at 721. This process then continues until the transfer is complete]; [0158 - When controller's firmware recognizes that it is approaching the end of a write command, it can set a folding control flag which tells the folding task to continue so as to end on a fine programming step/last step]);
receive, from the second volatile memory device, the first set of logical-to-physical mappings based at least in part on the folding operation being completed (Huang, [Fig. 21 shows completion of folding operation]; [0145 – In Fig. 22B, for balanced folding, it is preferable that the amount of folding output is faster that amount of D1 write input, in the second NVM. The reason is to be able to flush out the data in D1 to D3 faster than the system is taking in new host data to D1 in order to better prepare system D1 resources]; [0149 - The system performance is improved by increasing the amount of host-to-RAM transfer; The citations imply that after folding is completed, due to the host flush the memory system receives the accumulated L2P mapping from the host. This is similar to Para-0104 of the spec]),
update, based at least in part on the first set of logical-to-physical mappings and the folding operation being completed (Huang, [Fig. 21 shows completion of folding operation]), a set of entries of a logical-to-physical mapping table (Huang, [0020 - Updates are at the logical sector level and a write pointer points to the corresponding physical sectors in a block to be written. The mapping information is buffered in RAM and eventually stored in a sector allocation table in the main memory]) that map logical addresses of the apparatus to physical addresses (Huang, [0017 - The memory system/controller keeps track of how the logical address space is mapped into the physical memory but the host is unaware of this]) of the apparatus (Huang, [0099 - Figs. 10A(i)-10A(iii) show the mapping between a logical group and a metablock]; [0101 - Fig. 10B shows the mapping between logical groups and metablocks. Each logical group 380 is mapped to a unique metablock 370, except for a small number of logical groups in which data is currently being updated. After a logical group has been updated, it may be mapped to a different metablock. The mapping information is maintained in a set of logical to physical directories]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the mapping of Huang into the host-based processing system of Byun, Wells, Gorobets for the benefit of mapping between a logical group and a metablock. The metablock of the physical memory has N physical sectors for storing N logical sectors of data of a logical group. When the logical sectors are in contiguous logical order, the data are stored in the metablock in the same logical order (Huang, 0099).
Szubbocsev clarifies,
receive, from the second volatile memory device (Szubbocsev, [Fig. 1: Memory 105 in host 108]), the first set of logical-to-physical mappings based at least in part on the folding operation being completed (Szubbocsev, [Fig. 4B: step 421, Receive a write request from host 108]; [0037 – In Fig. 4B, step 423, the routine looks up a physical memory address in the first mapping table 134a using the logical address/L2P mapping contained in the write request sent from host 108. In Fig. 4B, step 424, the data in the write request is written to memory device 102 at the translated physical address; The writing to NVM memory device implies that folding is complete]),
update, based at least in part on the first set of logical-to-physical mappings and the folding operation being completed (Szubbocsev, [Fig. 4B]), a set of entries of a logical-to-physical mapping table that map logical addresses of the apparatus to physical addresses of the apparatus (Szubbocsev, [0038 – In Fig. 4B, after step 423, at step 425, routine 420 re-maps/updates at least a portion/subset of the first mapping table 134a in response to writing the main memory 102]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the host device interface of Szubbocsev into the host-based processing system of Byun, Wells, Huang, Gorobets for the benefit of enabling a host device to directly read from the memory of the memory device (Szubbocsev, 0011).
As per Claim 17, it is similar to claim 5 and therefore the same rejections are incorporated.
As per Claim 19, it is similar to claim 7 and therefore the same rejections are incorporated.
Claim 8 is rejected under AIA 35 U.S.C. 103(a) as being unpatentable over Byun (20200174690) in view of Wells et al (20230289078), Huang et al (20110149650), Gorobets et al (20050144365) and Yano et al (20100037011).
As per Claim 8, the rejection of claim 1 is incorporated and Byun, Wells Huang, Gorobets disclose receiving the accumulated data.
Yano further discloses,
receive the accumulated data at the first volatile memory device (Yano, [0190 – In Fig. 9, the input data from the host is first written in the first memory area 11/first volatile memory and the data is stored in the first memory area 11 for a certain period]) in respective data chunks having sizes corresponding to the storage capacity of the first volatile memory device (Yano, [0198 – In Fig. 9, controller 10 determines the physical address for data writing based on the logical address of the input data and the logical address and the physical address of the selected entry. The controller 10 instructs the volatile semiconductor memory including the first memory area 11 to write the input data in the area designated by the physical address, in step ST8, thereby implying receiving the data in chunk sizes corresponding to size of the first volatile memory]; [0200 - In the case where the input data from the host is larger than the page size, plural entries in the cache management table may be required. In such a case, the controller 10 updates the plural entries by repeating the process in Fig. 9]),
the controller further configured to cause the apparatus to:
delete a data chunk from the first volatile memory device (Yano, [Fig. 11: step ST8’, Invalidate entry in first memory area 11 corresponding to written data, thereby implying deleting the data chunk in first volatile memory]) after writing the data chunk to the second non-volatile memory device and before receiving a next data chunk (Yano, [Fig. 11: step ST7’, Write data in third memory area/second NVM]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the improved write performance of Yano, into the host-based processing system of Byun, Wells, Huang, Gorobets for the benefit of using the semiconductor storage device comprising nonvolatile semiconductor memory such as a NAND type flash memory with a specified unit of erasing, reading, and writing (Yano, 0101).
Response to Arguments
The Applicant's arguments filed on April 20, 2026 have been fully considered, but they are not persuasive.
Applicant argues,‘[0092….]That is, the return transfer from the host to the controller in Byun is triggered by host capacity insufficiency for new data, not by the accumulated data at the host reaching a quantity corresponding to a "a threshold….quantity of data stored by a….e," as recited in amended independent claim 1. (Rem, Pg. 16)
Response: This argument is incorrect.
The combination of Byun,Huang,Gorobets, where Byun, Fig. 6B, Para-0092 discloses storage of data into the host memory. Fig. 6B discloses two paths, the first path being when the available capacity of the integrated memory 104/host memory is larger than or equal to the size of the first portion, and the second path when the available capacity of the host memory is smaller than the first portion.
As explained in Byun, at least Figs. 6B, 7C, when the size of the second portion is evaluated, the host memory size is insufficient. So the first portion is retrieved and stored in NVM. This indicates that the retrieval (‘receiving….’) by the controller, the bus master, is based on determining accumulated data satisfying a threshold.
The threshold is defined by the physical layout of the flash memory: ‘a quantity of data stored by a respective first page of each physical block included in a virtual block’. The combination of Byun,Huang,Gorobets disclose that the controller is the one that controls this flash layout/geometry. It knows exactly how many physical blocks make up a virtual block and how many bytes a ‘first page’ holds because that information is hardcoded into the controller's FTL. The controller does not need to receive this threshold from the host, it calculates the threshold locally before any transmission ever occurs.
The controller has its internal tracking mechanism that pulls the data back in exact ‘portions’ that correspond to the ‘respective first page’ as claimed.
As an aside, the spec fails to support the argument. Since the controller does not communicate the allocation size to the host, the host could allocate a 32 KB buffer, but the calculated flash threshold (the pageline size) is 128 KB. The host operates in vacuum. The host does not know when to stop accumulating data. Please see the 112(b).
Applicant argues, ‘However, Gorobets does not teach or suggest "receiv[ing]….accumulated data…..satisfying a threshold quantity of data……… across physical planes, not a threshold condition governing when a host system transmits accumulated data back to a memory controller, as claimed’ (Rem, Pg. 17)
Response: This argument is incorrect.
The claim says the data is received based on the size equaling a threshold. The claim does not say the host sent it based on the threshold, only that the reception and folding operation use the threshold limit.
As explained in the 112(b), the host does not know when to stop accumulating data. In fact, this is a lack of enablement loop for the host.
That being said, in NVM/flash layout, a ‘pageline’ or ‘stripe’ represents the minimum size required to write across parallel structures (like multiple planes or channels) simultaneously. The combination of Byun,Huang,Gorobets where Gorobets discloses an architecture where data is aggregated on the host side to match the structure of the flash memory (such as planes or pages).
The combination of Byun,Huang,Gorobets, where Huang Fig. 11 discloses the host cache/RAM 82. And Gorobets Fig. 2, Para-0119 recites ‘The host 10 accesses the memory 200 …. each sector may contain 512 bytes of data….Also,….usual for the host to read or write to the memory system in unit of logical clusters, each consisting of one or more logical sectors’. NVM does not store data in 512-byte chunks. It uses physical pages, like 4 KB to 16 KB. This suggests that because the host RAM groups the logical sectors into clusters e.g., 4 KB or 8 KB at a time, the host’s RAM fulfills the task of accumulating and organizing data for transferring to the NVM system. Therefore it is reasonable to interpret that the host RAM is functionally acting as the HMB/host memory buffer.
A key feature of a HMB used as a write buffer or accumulator is that it avoids small, random writes over the PCIe bus to protect NAND endurance. Instead, it holds onto data until a specific threshold is reached. Gorobets discloses that if a host sends fragmented data or updates versions of logical units out of order, the controller intentionally delays finalizing the parallel programming routine. It waits until the sequential data segments fill the threshold requirement of a complete physical layout unit, e.g., a ‘pageline’ or ‘metapage’ mapping across planes. Since Gorobets teaches a controller that waits to pull/receive data from a host buffer until a specific logical group size is achieved to allow parallel plane processing, Gorobets teaches ‘accumulated data is received from the host memory based on a threshold’.
The threshold inside the host's memory is directly tied to the physical layout of the NVM, specifically matching the first pages of a group of physical blocks within a virtual block/metablock. The only way host memory can ‘map’ an accumulation threshold based on NVM layout is if the controller has extended its NVM mapping into the host memory space.
As explained by Gorobets, Fig. 21, a metablock (aka superblock aka virtual block) is a logical grouping of one physical block from each plane. So if the NVM supports a virtual block spanning 4 planes, and each physical page is 4KB, the controller will set its pull threshold at exactly 16KB (4 planes × 4KB). The host data is filled into the 16KB buffer in system RAM/first volatile memory with 4 contiguous logical pages (Logical Pages 0, 1, 2, and 3).
Since the 16KB threshold is reached, the controller triggers a sequential multi-plane write command. Due to the alignment:
Logical Page 0 goes to Plane 0, Physical Block X, Physical Page 0.
Logical Page 1 goes to Plane 1, Physical Block X, Physical Page 0.
Logical Page 2 goes to Plane 2, Physical Block X, Physical Page 0.
Logical Page 3 goes to Plane 3, Physical Block X, Physical Page 0.
Since the data acquired from the host is aligned, sequential data, when the next 16KB batch (Logical Pages 4, 5, 6, and 7) is acquired, the controller increments the pageline index across the virtual block. It repeats the same cyclic layout, but shifts down to fill Physical Page 1 across all four planes. This process repeats until the entire virtual block is filled from top to bottom.
Therefore the combination of Byun,Huang,Gorobets disclose the above requirement. The spec, Para-0030 states a similar mechanism.
Applicant further argues: ‘Stated alternatively, nowhere in Gorobets is there any disclosure of monitoring the accumulated data…., or the host transmitting the accumulated data to the controller's volatile memory based on satisfaction of that threshold’. (Rem, Pg. 17)
Response: This argument is incorrect.
As explained above, neither the spec nor the claim recite ‘monitoring’ by the host or that the host sends the accumulated data.
In Para-0013 of the spec recites, ‘The second volatile memory device may accumulate the portions of data until an aggregate size of the data satisfies a threshold (e.g., a quantity….stored by a pageline….), and the first volatile memory device may read the aggregate data (e.g., in respective portions) for writing to the second non-volatile memory device as part of a first stage’. Here ‘read’ means the controller is the active initiator of the data retrieval event. The host accumulates data and the controller actively executes a read command to pull the accumulated data back down when threshold is reached.
The combination of Byun,Huang,Gorobets disclose the same mechanism. The host accumulates data, and the controller is the active retriever that pulls the exact amount of data down based on its flash layout when threshold is reached. The controller has its internal tracking mechanism that pulls the data back in exact ‘portions’ that correspond to the ‘respective first page’ as claimed. Please see O/A.
That said, whether the system uses the host to monitor the threshold and send a write command or the controller's internal tracking mechanism monitors the threshold and executes a fetch, the main requirement is the same: the transfer of data is triggered by the accumulation threshold.
However, because the controller is the bus master over the PCIe/NVMe interface (spec, Paras-0018,0073), the two approaches are functionally equivalent.
Conclusion
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Arvind Talukdar
Primary Examiner
Art Unit 2132
/ARVIND TALUKDAR/Primary Examiner, Art Unit 2132
Prosecution Insights