DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of claims 1-9 in the reply filed on 12/16/2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 10-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/16/2025.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, 5-9 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yang (pub # US 20090113169 A1).
Regarding claim 1, Yang discloses a system (reconfigurable array processor system shown in figure 1, details shown in subsequent figures), comprising: a first processing chain (processor groups shown in figure 3, groups of two processing elements, PEs, shown as an example); and a second processing chain (any other group of PEs in the figure, for example, the next group connected to the top-left most group), the first processing chain comprising: a first core; a second core (first and second PEs shown in figure 3); and a first inter-core bus connecting the second core of the first processing chain to the first core of the first processing chain the system being configured to forward an output of a calculation of the first processing chain to the second processing chain (connection between first PE and second PE shown in figure 3, paragraph 12, forwarding discussed in paragraph 54).
Regarding claim 2, Yang discloses the system of claim 1, wherein the first core of the first processing chain comprises: a memory (register file 125 in figure 8); and a packet processing circuit (ALU 122in figure 8), the packet processing circuit being configured: to receive a packet comprising instructions; and to store the instructions in the memory (storing the operation and intermediate result in the temporary register and re-used for operations, paragraph 78).
Regarding claim 5, Yang discloses the system of claim 1, further comprising a first inter-chain bus, wherein an initial core of the first processing chain is connected, through the first inter-chain bus, to an initial core of the second processing chain (shown in figure 3, paragraph 56).
Regarding claim 6, Yang discloses the system of claim 5, further comprising: a third processing chain; and a second inter-chain bus, wherein an initial core of the first processing chain is connected, through the second inter-chain bus, to an initial core of the third processing chain (shown in figure 3, paragraph 56).
Regarding claim 7, Yang discloses the system of claim 1, further comprising a packet scheduler (context layer of the configuration cache 200, paragraph 53) connected to the first processing chain and to the second processing chain, the packet scheduler being configured to send, to each of the first processing chain and the second processing chain, packets comprising instructions, parameters, and input data (PEs exchange data based on the context cache 200, paragraph 54).
Regarding claim 8, Yang discloses the system of claim 1, further comprising a packet scheduler (context layer of the configuration cache 200, paragraph 53) connected to the first processing chain, the packet scheduler being configured: to send a first sequence of symbols to the first core of the first processing chain, for testing for a second sequence of symbols; and to send a third sequence of symbols to a first core of the second processing chain, for testing for the second sequence of symbols, wherein the first sequence of symbols overlaps with the third sequence of symbols (results from PEs are forwarded to other PEs, paragraph 54; examiner further notes that “for testing” appears to be intended use and not necessarily functions performed by the circuits).
Regarding claim 9, the above combination discloses the system of claim 8, wherein the first sequence of symbols overlaps with the third sequence of symbols in an overlapped area having a size greater than the second sequence of symbols (operands are various numbers and sizes shown in paragraph 60, and when operands are mostly similar, can overlaps in a greater size).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 3 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang further in view of Acar (US 20160259826 A1).
Regarding claim 3, Yang discloses the system of claim 1, and that the processing elements pass results to other processing elements in the chain, but does not disclose explicitly speculative processing. However, Acar discloses wherein the first processing chain is configured: to perform, in the first core of the first processing chain, a first calculation based on a first speculative value; to perform, in the second core of the first processing chain, a second calculation based on a second speculative value; and to validate the first speculative value, wherein the forwarding of the output of the first calculation to the second processing chain is based on the validating (speculative loading data from cache for the processors, and validating as “hit” when results are in fact in the cache, or “miss” when they are not; and a “miss” will result in reloading the data and corresponding computation; paragraph 53). Furthermore, teachings of Acar and Yang are from the same field of array processors.
Therefore, it would have been obvious before the effective filing date of the invention for a person of ordinary skill in the art to combine teachings of Acar with Yang by using speculative loading and dense data packing, to increase the performance of the processor system.
Regarding claim 4, Yang discloses the system of claim 1, that multiple PEs process data in parallel, but does not explicitly speculative processing. However, Acar discloses wherein the system is configured to perform a number of speculative operations using a number of cores based on the number of speculative operations (paragraph 53, see rejection of claim 3 above, the same rationale is applied).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SCOTT C SUN whose telephone number is (571)272-2675. The examiner can normally be reached Monday - Friday, 12-8:30 PM.
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/SCOTT C SUN/Primary Examiner, Art Unit 2181