DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 5, 13, and 18 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 5, the limitation “wherein the interfacial film and the active area each include an oxide of a same material” fails to comply with the written description requirement because in view of applicant’s disclosure, it is not clear how an interfacial film and an active area can be an oxide of a same material because that makes an active area (silicon, [0018]) a silicon oxide.
Regarding claim 13, the limitation “wherein the interfacial film and the active area includes an oxide of a same material” fails to comply with the written description requirement because in view of applicant’s disclosure, it is not clear how an interfacial film and an active area can be an oxide of a same material because that makes an active area (silicon, [0018]) a silicon oxide.
Regarding claim 18, the limitation “wherein the interfacial film and the active area include an oxide of a same material” fails to comply with the written description requirement because in view of applicant’s disclosure, it is not clear how an interfacial film and an active area can be an oxide of a same material because that makes an active area (silicon, [0018]) a silicon oxide.
Clear explanation or claim modification is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1-4, 6-11, 15-17, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US publication 2022/0077154 A1), hereinafter referred to as Kim154.
Regarding claim 1, Kim154 teaches a semiconductor memory device (fig. 1-3 and related text) comprising: a substrate (101, [0017]); an element isolation pattern (110, [0017]) defining an active area (ACT, [0017]) in the substrate; a first conductive pattern (BL/DC, [0017]) on the substrate and the element isolation pattern (fig. 2a-2b), and extending in a first direction (Y direction, fig. 1), wherein the first conductive pattern is connected to a first portion (portion of ACT near DC, fig. 2a) of the active area; a capacitor structure (CAP, [0017]) on the substrate and the element isolation pattern and connected to a second portion (portion of ACT near BC, fig. 2a) of the active area; a gate trench (trenches for WL and GE, [0022-0025], fig. 2a) defined in the substrate and the element isolation pattern and extending in a second direction (X direction) that intersects the first direction (fig. 1), the gate trench extending across the active area in an area between the first portion and the second portion thereof (fig. 2a); and a second conductive pattern (GE/WL) in the gate trench and extending in the second direction, wherein a first trench width (trench width at top portion in ACT area) of a portion of the gate trench in the active area is greater than a second trench width (trench width at bottom portion in 110 area) of a portion of the gate trench in the element isolation pattern (fig. 2a).
Regarding claim 2, Kim154 teaches wherein the area between the first portion and the second portion of the active area includes a lower pattern (120, [0022]) covered with the element isolation pattern (fig. 2a), and an upper pattern (115, [0034]) on the lower pattern and free from coverage by the element isolation pattern (fig. 2a), wherein a first pattern width of the upper pattern is smaller than a second pattern width of the lower pattern (fig. 2a).
Regarding claim 3, Kim154 teaches wherein a portion of the upper pattern adjacent to the first portion and the second portion overlaps the element isolation pattern in the second direction (fig. 2a).
Regarding claim 4, Kim154 teaches further comprising: an interfacial film (125, [0025]) in the gate trench and extending along a side surface of the first portion and a side surface of the second portion (fig. 2a); and a gate dielectric film (120, [0022]) between the interfacial film and the second conductive pattern and extending along the interfacial film and the element isolation pattern (fig. 2a).
Regarding claim 6, Kim154 teaches further comprising a capping pattern (128, [0022]) in the gate trench and extending along an upper surface of the second conductive pattern (fig. 2a).
Regarding claim 7, Kim154 teaches wherein the element isolation pattern defines a plurality of active areas in the substrate, wherein the plurality of active areas are arranged in a lattice structure in the first direction and the second direction (fig. 1-2).
Regarding claim 8, Kim154 teaches wherein a first gate width of a portion of the second conductive pattern (upper portion) in the active area is greater than a second gate width of a portion of the second conductive pattern (lower portion) in the element isolation pattern.
Regarding claim 9, Kim154 teaches wherein a first gate width of a portion of the second conductive pattern (lower portion) in the active area is smaller than a second gate width of a portion of the second conductive pattern (upper portion) in the element isolation pattern.
Regarding claim 10, Kim154 teaches a semiconductor memory device (fig. 1-3 and related text) comprising: a substrate 101, [0017]); an element isolation pattern (110, [0017]) defining an active area (ACT, [0017]) in the substrate; a first conductive pattern (BL/DC, [0017]) on the substrate and the element isolation pattern (fig. 2a-2b), wherein the first conductive pattern extends in a first direction (Y direction, fig. 1), and wherein the first conductive pattern is connected to a first portion (portion of ACT near DC, fig. 2a) of the active area; a capacitor structure (CAP, [0017]) on the substrate and the element isolation pattern (fig. 2a-2b), the capacitor structure connected to a second portion (portion of ACT near BC, fig. 2a) of the active area; a gate trench (trenches for WL and GE, [0022-0025], fig. 2a) defined in the substrate and the element isolation pattern and extending in a second direction (X direction) that intersects the first direction (fig. 1), wherein the gate trench extends across the active area in an area between the first portion and the second portion thereof (fig. 2a); and a second conductive pattern (GE/WL) in the gate trench and extending in the second direction, wherein the area between the first portion and the second portion of the active area includes a lower pattern (120, [0022]) covered with the element isolation pattern (fig. 2a), and an upper pattern (115, [0034]) disposed on the lower pattern and free from coverage by the element isolation pattern (fig. 2a), wherein a first pattern width of the upper pattern is smaller than a second pattern width of the lower pattern (fig. 2a), wherein a portion of the upper pattern adjacent to the first portion and the second portion overlaps the element isolation pattern in the second direction (fig. 2a).
Regarding claim 11, Kim154 teaches wherein a first trench width (trench width at top portion in ACT area) of a portion of the gate trench in the active area is greater than a second trench width (trench width at bottom portion in 110 area) of a portion of the gate trench in the element isolation pattern (fig. 2a).
Regarding claim 15, Kim154 teaches wherein the element isolation pattern defines each of a plurality of active areas in the substrate, wherein the plurality of active areas are arranged in a lattice structure in the first direction and the second direction (fig. 1-2).
Regarding claim 16, Kim154 teaches a semiconductor memory device (fig. 1-3 and related text) comprising: a substrate (101, [0017]); an element isolation pattern (110, [0017]) defining an active area (ACT, [0017]) in the substrate; a first conductive pattern (BL, [0017]) on the substrate and the element isolation pattern (fig. 2a-2b) and extending in a first direction (Y direction, fig. 1); a direct contact (DC, [0017]) connecting the active area and the first conductive pattern to each other (fig. 2a); a spacer structure (140, [0017]) extending along a side surface of the first conductive pattern (fig. 2a); a buried contact (BC, [0017]) on a side surface of the spacer structure and connected to the active area (fig. 2a); a capacitor structure CAP, [0017]) on the buried contact and connected to the buried contact (fig. 2a); a gate trench (trenches for WL and GE, [0022-0025], fig. 2a) defined in the substrate and the element isolation pattern and extending in a second direction (X direction) that intersects the first direction (fig. 1-2), wherein the gate trench extends across the active area in an area between the direct contact and the buried contact (fig. 2a); and a second conductive pattern (GE/WL) in the gate trench and extending in the second direction, wherein a first width of a portion of the gate trench (trench width at top portion in ACT area) in the active area is greater than a second width of a portion of the gate trench (trench width at bottom portion in 110 area) in the element isolation pattern (fig. 2a).
Regarding claim 17, Kim154 teaches further comprising a gate dielectric film (120, [0022]) interposed between the active area and the second conductive pattern (fig. 2a).
Regarding claim 19, Kim154 teaches wherein the element isolation pattern defines each of a plurality of active areas in the substrate, wherein the plurality of active areas are arranged in a lattice structure in the first direction and the second direction (fig. 1-2).
Allowable Subject Matter
Claims 12, 14, and 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 12 and 14, the claim contains the following limitations: “further comprising: an interfacial film in the gate trench and extending along a side surface of the first portion, a side surface of the second portion, and a side surface and an upper surface of the upper pattern; and a gate dielectric film in the gate trench and extending along an upper surface of the element isolation pattern, and a side surface and an upper surface of the interfacial film” and none of the prior art of record discloses, teaches or fairly suggests, alone or in combinations when taken in combination with all other limitations of the base claim and any intervening claims.
Regarding claim 20, the claim contains the following limitations: “further comprising: a base metal film between the substrate and the first conductive pattern; a base semiconductor film between the substrate and the base metal film, and including a semiconductor material doped with impurities; and a base silicide film between the base semiconductor film and the base metal film, and including a metal silicide material, wherein the direct contact directly contacts the base metal film” and none of the prior art of record discloses, teaches or fairly suggests, alone or in combinations when taken in combination with all other limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: see the attached form PTO-892 for pertinent cited art.
Kim et al. (US publication 2022/0115377 A1) teaches (a bitline structure and a bitline contact of a memory cell, fig. 1-2).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mohammed R Alam whose telephone number is 469-295-9205 and can normally be reached between 8:00am-6:00pm (M-F) or by e-mail via Mohammed.Alam1@uspto.gov.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached on 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMED R ALAM/Primary Examiner, Art Unit 2897