DETAILED ACTION
Election/Restrictions
1. Claims 9-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/23/2025.
Applicant’s election without traverse of 1-8 in the reply filed on 12/23/2025 is acknowledged.
Priority
2. Receipt is acknowledged of papers submitted under 35 U.S.C. 119 (a) — (d), which papers have been placed of record in the file. Oath/Declaration
Oath/Declaration
3. Oath and declaration filed is missing (i.e., ADS filed on 11/13/2023 is ok).
Information Disclosure Statement
4. The prior art documents submitted by application in the Information Disclosure Statement filed on 8/6/2024 and 1/14/2025 have all been considered and made of record ( note the attached copy of form PTO – 1449).
Claim Rejections - 35 USC § 102
5.In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s)1-5 and 7-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yap et al (9,647,187 B1).
Regarding claim 1, Yap et al discloses (refer to figures 3A,3B, 8C and 8D) an optical phased board comprising: a plurality of optical waveguide layers (figures 8A-8C discloses multiple waveguides 98 on each chip level 82), wherein each of the optical waveguide layers comprises a plurality of optical waveguides (waveguide 98) arranged side by side (figure 8A, all waveguides 98 are located next to each other), wherein a quantity of the optical waveguide layers is 2a, and wherein a is an integer greater than 1; and a plurality of isolation layers superposed over the optical waveguide layers (figure 8C and 8D), wherein each of the isolation layers is located between two adjacent optical waveguide layers (figures 8A-8D , dielectric material 130).
Regarding claim 2, Yap et al discloses wherein the two adjacent optical waveguide layers comprise a first optical waveguide layer and a second optical waveguide layer, wherein the first optical waveguide layer comprises an optical waveguide gap, and wherein each of the isolation layers comprises a filling layer located in the optical waveguide gap; and a support layer located between the filling layer and the second optical waveguide layer (figures 8A ,8C ,8D and 9, dielectric layer 130 covering all waveguides 98 in each chip 82 ).
Regarding claim 3, Yap et al discloses wherein a thickness of the filling layer is greater than or equal to a depth of the optical waveguide gap (figures 8A ,8C ,8D and 9, dielectric layer 130 covering all waveguides 98 in each chip 82 ). .
Regarding claim 4, Yap et al discloses wherein the optical waveguide layers comprise a first optical waveguide layer that is located at a first outermost layer and that comprises a top surface located away from the isolation layers and an optical waveguide gap, and wherein the optical phased board further comprises a filling layer located in the optical waveguide gap (figures 8C-8D and figure 9, Chip alignment base 78 and transfer base 150 and stack 80).
Regarding claim 5, Yap et al discloses wherein the optical waveguide layers further comprise a second optical waveguide layer that is located at a second outermost layer and that comprises a bottom surface located away from the isolation layers, and wherein the optical phased board further comprises a substrate layer supported at the bottom surface (figures 8C-8D and figure 9, Chip alignment base 78 and transfer base 150 and stack 80).
Regarding claim 7, Yap et al discloses further comprising: a plurality of through holes extending along a thickness direction of the optical phased board and located in the lateral area, wherein each of the through holes has a conductive medium; and a plurality of solder balls located at the bottom surface, wherein each of the solder balls is electrically coupled to the corresponding electrode through the conductive medium (figure 8C,8D,9 , posts 90, solder bumps 172).
Regarding claim 8, Yap et al discloses further comprising a redistribution layer (RDL) located on the bottom surface and comprising a first surface located away from the second optical waveguide layer, and wherein the solder balls are further located on the first surface (figure 8C,8D,9 , posts 90, solder bumps 172).
Allowable Subject Matter
6.Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
7.The following is a statement of reasons for the indication of allowable subject matter: wherein the optical phased board is in a stepped shape and has a plurality of steps, wherein the steps are located in a lateral area of the optical waveguides, wherein an upper surface of each of the steps comprises a plurality of pads, and wherein each of the pads is electrically coupled to a corresponding electrode of a corresponding optical waveguide of the optical waveguides.
Conclusion
8.Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED A HASAN whose telephone number is (571)272-2331. The examiner can normally be reached M-TH 6 AM -4 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bumsuk Won can be reached at 571-272-2713. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MOHAMMED A HASAN/Primary Examiner, Art Unit 2872 3/16/2026