Prosecution Insights
Last updated: April 19, 2026
Application No. 18/507,549

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Non-Final OA §102§103
Filed
Nov 13, 2023
Examiner
CHOI, CALVIN Y
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
2y 4m
To Grant
99%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allow Rate
686 granted / 842 resolved
+13.5% vs TC avg
Strong +18% interview lift
Without
With
+17.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
30 currently pending
Career history
872
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
65.1%
+25.1% vs TC avg
§102
23.8%
-16.2% vs TC avg
§112
5.6%
-34.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 842 resolved cases

Office Action

§102 §103
DETAILED ACTION This Office Action is in response to the application filed on 13 November 2023. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 2, 5, 7-14, 16, and 17 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Xie et al. (US 2023/0132353 A1; hereinafter Xie ) . In regards to claim 1, Xie teaches a semiconductor device comprising: a support member (103/105/107/109) including a substrate insulation layer (103) and a power wire (109) , the substrate insulating layer including a plurality of separating insulators (fig. 16: portions of (103) horizontally between elements (107/109)) [0024-0027] , the power wire being at a space between the plurality of separating insulators (fig. 16) ; an active region (119) [0029] on the power wire (figs. 8 and 16: (119) is over and on (109)) ; source and drain regions (123) [0031] adjacent to the active region; and a gate electrode (131) on the active region (fig. 8) [0029] . In regards to claim 2, Xie teaches the limitations discussed above in addressing claim 1. Xie further teaches the limitations wherein a lateral side between a corresponding one of the separating insulators and the power wire includes a slope side or an inclined surface so that a width of the corresponding one of the separating insulators narrows, and a width of the power wire widens, when approaching a rear side of the support member from a front side of the support member (figs. 16-18) [0058] . In regards to claim 5, Xie teaches the limitations discussed above in addressing claim 1. Xie further teaches the limitations wherein the support member (103/105/107/109) includes the substrate insulation layer (103) and the power wire (109) and does not include a semiconductor substrate (101) . In regards to claim 7, Xie teaches the limitations discussed above in addressing claim 1. Xie further teaches the limitations further comprising: an insulating portion including an insulating material (115) [0024-0027] and being on the power wire (109) [0024-0027] , and a penetration connector (139) [0033] penetrating the insulating portion to connect at least one of source and drain electrodes connected to the source and drain regions and the power wire (figs. 14-16) . In regards to claim 8, Xie teaches the limitations discussed above in addressing claim 7. Xie further teaches the limitations wherein a lateral side of the penetration connector includes a slope side or an inclined surface so that a width of the penetration connector narrows when approaching a rear side from a front side (figs. 16-18) . In regards to claim 9, Xie teaches the limitations discussed above in addressing claim 7. Xie further teaches the limitations further comprising: a rear insulation layer (111) between the power wire (109) and the active region (119) and between the power wire and the source and drain regions (123) [0024-0029] . In regards to claim 10, Xie teaches the limitations discussed above in addressing claim 7. Xie further teaches the limitations wherein at least one of the source and drain electrodes (123) [0031] includes a main body portion and an extending portion, the main body on the substrate insulation layer with an insulation layer interposed therebetween, the extending portion penetrating the insulation layer and connecting the main body portion and the penetration connector [0034] . In regards to claim 11, Xie teaches the limitations discussed above in addressing claim 10. Xie further teaches the limitations further comprising: an insulator (ILD) separating the source and drain electrodes (143) , wherein a lower side of the insulator is below a lower side of the extending portion (figs. 16-18) . In regards to claim 12, Xie teaches the limitations discussed above in addressing claim 1. Xie further teaches the limitations wherein the power wire (109) [0024-0027] further includes a connector (139) connected to a rear side of at least one of the source and drain regions (123) (figs. 16-18) . In regards to claim 13, Xie teaches the limitations discussed above in addressing claim 12. Xie further teaches the limitations further comprising: a rear insulation layer (111) between the active region (119) and the power wire (109) , wherein the power wire includes a main body and the connector, the main body being at a space between the plurality of separating insulators, the connector protruding from a front side of the main body, penetrating the rear insulation layer, and connected to at least one of the source and drain regions (figs. 16-19) . In regards to claim 14, Xie teaches the limitations discussed above in addressing claim 1. Xie further teaches the limitations further comprising: a rear wire portion (105/107/109) disposed on a rear side of the support member (103/105/107/109) [0024-0027] , wherein the rear wire portion includes the power wire (109) [0024-0027] . In regards to claim 16, Xie teaches the limitations discussed above in addressing claim 1. Xie further teaches the limitations further comprising: a signal wire [0035] on the active region (119) [0029] , the source and drain regions (123) [0031] , and the gate electrode (131) on a front side of the support member (103/105/107/109) (fig. 8) [0029] , wherein the signal wire is at a center region of a standard cell to overlap the insulating separators when viewed in a plan view (figs. 16-18) . In regards to claim 17, Xie teaches a semiconductor device comprising: a support member (103/105/107/109) including a substrate insulation layer (103) , the substrate insulation layer including a plurality of separating insulators (fig. 16: portions of (103) horizontally between elements (107/109)) [0024-0027] ; a rear wire portion (105/107/109) including a power wire (109) and a rear wire layer (103) , the power wire being at a space between the plurality of separating insulators (fig. 16: (103) is placed in a horizontal space between elements (109) in a plan view and also in a vertical space between upper (103) and lower (103)) , the rear wire layer being on a rear side (bottom side) of the power wire [0024-0027] ; a rear insulation layer (111) on a front side (upper side) of the power wire [0024-0027] ; a plurality of channel layers (119) [0029] on a front side of the rear insulation layer and spaced apart from each other (figs. 8 and 16: elements (119) are spaced apart from one another by elements (123)) ; source and drain regions (123) [0031] adjacent to the plurality of channel layers (fig. 8) ; and a gate electrode (131) on the plurality of channel layers (fig. 8) [0029] . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 3, 4, 6, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie . In regards to claim 3, Xie teaches the limitations discussed above in addressing claim 1. Xie appears to be silent as to, but does not preclude, the limitations wherein each of the separating insulators corresponds to a center region of a corresponding standard cell . Xie teaches the limitations of varying the placement of separating insulators to affect conductivities and conductive paths of elements within a semiconductor device (figs. 16-18) ([0027], [0073]) . Absent persuasive evidence, it would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to find that the configuration of an element is a matter of choice. In re Dailey , 357 F. 2d 669, 149 USPQ 47 (CCPA 1966). In regards to claim 4, Xie teaches the limitations discussed above in addressing claim 3. Xie appears to be silent as to, but does not preclude, the limitations wherein the power wire includes a first power wire shared by the standard cell and a first adjacent cell adjacent to one side of the standard cell, and a second power wire shared by the standard cell and a second adjacent cell adjacent to another side of the standard cell . Xie teaches the limitations of varying the placement of separating insulators to affect conductivities and conductive paths of elements within a semiconductor device (figs. 16-18) ([0027], [0073]) . Absent persuasive evidence, it would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to find that the configuration of an element is a matter of choice. In re Dailey , 357 F. 2d 669, 149 USPQ 47 (CCPA 1966). In regards to claim 6, Xie teaches the limitations discussed above in addressing claim 5. Xie appears to be silent as to, but does not preclude, the limitations wherein a thickness of the power wire is substantially equivalent to a depth of a corresponding one of the separating insulators, or an entire portion of a lateral side of the power wire contacts an entire portion of a lateral side of the corresponding one of the separating insulators . Xie teaches the limitations of varying the placement of separating insulators to affect conductivities and conductive paths of elements within a semiconductor device (figs. 16-18) ([0027], [0073]) . Absent persuasive evidence, it would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to find that the configuration of an element is a matter of choice. In re Dailey , 357 F. 2d 669, 149 USPQ 47 (CCPA 1966). In regards to claim 15, Xie teaches the limitations discussed above in addressing claim 5. Xie appears to be silent as to, but does not preclude, the limitations wherein a thickness of the power wire is less than a height to a front side of the active region from the front side of the power wire . Xie teaches the limitations of varying the placement of separating insulators to affect conductivities and conductive paths of elements within a semiconductor device (figs. 16-18) ([0027], [0073]) . Absent persuasive evidence, it would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to find that the configuration of an element is a matter of choice. In re Dailey , 357 F. 2d 669, 149 USPQ 47 (CCPA 1966). Allowable Subject Matter Claim s 18-20 are allowed. The following is a statement of reasons for the indication of allowable subject matter: independent claim 1 is allowable because the closest prior art does not appear to disclose, alone or in combination, the limitations of a method of manufacturing a semiconductor device comprising: providing a support structure including a substrate; forming a substrate insulation layer including a separating insulator and an upper insulator, by forming a plurality of first separators and a second separator and filling the first separators and the second separator with an insulating material, a rear side of the second separator being higher than the first separators in the support structure; forming source and drain regions and a gate electrode on the support structure; forming a space portion by removing at least a part of the substrate disposed between the first separators; and forming a power wire by filling a conductive material in the space portion. The claims of the application at hand that depend from allowable claims are allowable because they respectively depend, directly or indirectly, from the allowable claims of the application at hand. Therefore, the dependent claims in question incorporate the allowable limitations of the claims from which they depend. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT CALVIN Y CHOI whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-7882 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT M-F 8-4 (Pacific Time) . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice . If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT William (Blake) Partridge can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT (571) 270-1402 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. FILLIN "Examiner Stamp" \* MERGEFORMAT CALVIN CHOI Patent Examiner Art Unit 2812 /CALVIN Y CHOI/ Patent Examiner, Art Unit 2812
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Prosecution Timeline

Nov 13, 2023
Application Filed
Mar 21, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
99%
With Interview (+17.5%)
2y 4m
Median Time to Grant
Low
PTA Risk
Based on 842 resolved cases by this examiner. Grant probability derived from career allow rate.

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