DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note by the Examiner
For clarity, references to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and examiner explanations for 102 &/or 103 rejections are provided in parenthesis.
Election/Restrictions
Applicant's election with traverse of Species I in the reply filed on 5/13/2026 is acknowledged. The traversal is on the ground(s) that the Examiner did not provide reasoning for mutual exclusivity of the asserted species and that the Examiner did not provide specific fields of search in order to prove search burden. This is not found persuasive because reasoning is provided on pages 2 and 3 of the Requirement for Restriction/Election, and it is not required to provide specific examples of fields of search to prove search burden.
The requirement is still deemed proper and is therefore made FINAL.
Claims 11-12 and 17-18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 5/13/2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 4, 8, 16, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jung et al. (Pub. No.: US 20130020719 A1), hereinafter as Jung.
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Image A: close up of Jung Fig. 29, showcasing 1st-4th surfaces.
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Image B: close up of Jung Fig. 29, showcasing 1st-3rd connection pads and bottom surface of first connection pad.
With respect to claim 1, Jung teaches a semiconductor structure comprising: an interposer die (see Jung Fig. 29, first semiconductor device 100 (Jung [0178])) comprising a first surface (see Image A) and a second surface (see Image A) that is opposite the first surface (see Jung Fig. 29 and Image A); a slave die (see Jung Fig. 29, second semiconductor device 300 (Jung [0178])) comprising a third surface (see Image A) and a fourth surface (see Image A) that is opposite the third surface (see Jung Fig. 29 and Image A), wherein the slave die includes a plurality of through-silicon vias (see Jung Fig. 29, second through silicon via electrodes 30b (Jung [0180])); a plurality of first connection members (see Jung Fig. 29, first bumps 71 (Jung [0181])) on the first surface (see Jung Fig. 29); and a plurality of second connection members (see Jung Fig. 29, third bumps 75 (Jung [0180])) configured to electrically connect the second surface and the third surface (see Jung Fig. 29).
With respect to claim 2, Jung teaches the semiconductor structure of claim 1, wherein the first surface (see Image A) is a front-side of the interposer die (let the first surface of the interposer die be called the front-side of the interposer die), and the second surface (see Image A) is a back-side of the interposer die (let the second surface of the interposer die be called the back-side of the interposer die).
With respect to claim 4, Jung teaches the semiconductor structure of claim 1, wherein the slave die (see Jung Fig. 29, second semiconductor device 300) is configured to operate as a single chip (see Jung Fig. 29, where the slave die is a single chip on the interposer die).
With respect to claim 8, Jung teaches a semiconductor structure, comprising: an interposer die (see Jung Fig. 29, first semiconductor device 100 (Jung [0178])) comprising a first surface (see Image A) and a second surface (see Image A) that is opposite the first surface (see Jung Fig. 29 and Image A), wherein the interposer die comprises a plurality of first connection pads (see Fig. 1, third pad 69 (Jung [0090] and [0179]: “The first and second semiconductor devices 100 and 300 may have the same structure as any of the semiconductor devices described above with reference to FIGS. 1 to 26.”); and see Image B, first connection pads) at the first surface (see Jung Fig. 29, Image A, and Image B), a plurality of second connection pads (see Fig. 1, second pads 67 (Jung [0088] and [0179]); and see Image B, second connection pads) at the second surface (see Jung Fig. 29, Image A, and Image B), and a plurality of first through-silicon vias (see Jung Fig. 29, first through silicon via electrodes 30a (Jung [0180])) connected to the plurality of first connection pads and the plurality of second connection pads (see Jung Fig. 29 and Image B); a slave die (see Jung Fig. 29, second semiconductor device 300 (Jung [0178])) comprising a third surface (see Image A) and a fourth surface (see Image A) opposite the third surface (see Jung Fig. 29 and Image A), wherein the slave die comprises a plurality of third connection pads (see Fig. 1, third pad 69 (Jung [0090] and [0179]); and see Image B, third connection pads) at the third surface (see Jung Fig. 29, Image A, and Image B), and a plurality of second through-silicon vias (see Jung Fig. 29, second through silicon via electrodes 30b (Jung [0180])) on the plurality of third connection pads (see Jung Fig. 29 and Image B); a plurality of first connection members (see Jung Fig. 29, first bumps 71 (Jung [0181])) respectively on bottom surfaces (see Jung Fig. 29 and Image B, bottom surface) of the plurality of first connection pads (see Jung Fig. 29 and Image B); and a plurality of second connection members (see Jung Fig. 29, third bumps 75 (Jung [0180])) configured to electrically connect the second surface and the third surface (see Jung [0181]: “The bumps 71, 73 and 75 may correspond to solder balls, conductive bumps, conductive spacers, pin grid arrays or a combination thereof.” Because the second connection members are electrically conductive, they electrically connect the two surfaces.).
With respect to claim 16, Jung teaches the semiconductor structure of claim 8, wherein the plurality of second connection members (see Jung Fig. 29, third bumps 75) comprise a micro-bump (see Jung [0181]: “The bumps 71, 73 and 75 may correspond to solder balls, conductive bumps, conductive spacers, pin grid arrays or a combination thereof.”).
With respect to claim 19, Jung teaches a semiconductor package, comprising: a substrate (see Jung Fig. 29, package substrate 200 (Jung [0178])); an interposer die (see Jung Fig. 29, first semiconductor device 100 (Jung [0178])) on the substrate (see Jung Fig. 29) and comprising a first surface (see Image A) and a second surface (see Image A) opposite the first surface (see Jung Fig. 29 and Image A), wherein the interposer die comprises a plurality of first connection pads (see Fig. 1, third pad 69 (Jung [0090] and [0179]: “The first and second semiconductor devices 100 and 300 may have the same structure as any of the semiconductor devices described above with reference to FIGS. 1 to 26.”); and see Image B, first connection pads) at the first surface (see Jung Fig. 29, Image A, and Image B), a plurality of second connection pads (see Fig. 1, second pads 67 (Jung [0088] and [0179]); and see Image B, second connection pads) at the second surface (see Jung Fig. 29, Image A, and Image B), and a plurality of first through-silicon vias (see Jung Fig. 29, first through silicon via electrodes 30a (Jung [0180])) connected to the plurality of first connection pads and the plurality of second connection pads (see Jung Fig. 29 and Image B); a slave die (see Jung Fig. 29, second semiconductor device 300 (Jung [0178])) comprising a third surface (see Image A) and a fourth surface (see Image A) opposite the third surface (see Jung Fig. 29 and Image A), wherein the slave die comprises a plurality of third connection pads (see Fig. 1, third pad 69 (Jung [0090] and [0179]); and see Image B, third connection pads) at the third surface (see Jung Fig. 29, Image A, and Image B), and a plurality of second through-silicon vias (see Jung Fig. 29, second through silicon via electrodes 30b (Jung [0180])) on the plurality of third connection pads (see Jung Fig. 29 and Image B); a plurality of first connection members (see Jung Fig. 29, first bumps 71 (Jung [0181])), wherein the plurality of first connection members are on bottom surfaces (see Jung Fig. 29 and Image B, bottom surface) of respective ones of the plurality of first connection pads (see Jung Fig. 29 and Image B); a plurality of second connection members (see Jung Fig. 29, third bumps 75 (Jung [0180])) configured to electrically connect the second surface and the third surface (see Jung [0181]: “The bumps 71, 73 and 75 may correspond to solder balls, conductive bumps, conductive spacers, pin grid arrays or a combination thereof.” Because the second connection members are electrically conductive, they electrically connect the two surfaces.); and a molding material (see Jung Fig. 29, mold layer 310 (Jung [0181])) configured to mold the interposer die and the slave die on the substrate (see Jung [0181]: “The semiconductor package 403 may further include a mold layer 310 surrounding or covering the first and second semiconductor devices 100 and 300.”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3, 5, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Jung, in view of Choi et al. (Pub. No.: US 20210343616 A1), hereinafter as Choi.
With respect to claim 3, Jung teaches the semiconductor structure of claim 1.
Jung does not teach that the interposer die comprises a silicon interposer die.
Choi teaches that an interposer die (see Choi fig. 1, first semiconductor chip 100 (Choi [0016])) comprises a silicon interposer die (see Choi [0022] “The first semiconductor substrate 110 and the second semiconductor substrate 210 may include a semiconductor material, e.g., silicon (Si).”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the material of the interposer die of Jung with the material taught by Choi in order to have semiconductor properties in the interposer die.
With respect to claim 5, Jung teaches the semiconductor structure of claim 1.
Jung does not teach a non-conductive film (NCF) between the interposer die and the slave die, and surrounding the plurality of second connection members.
Choi teaches a non-conductive film (NCF) (see Choi Fig. 1, insulating adhesive layer 350 (Choi [0053])) between an interposer die (see Choi Fig. 1, first semiconductor chip 100 (Choi [0016])) and a slave die (see Choi Fig. 1, second semiconductor chips 200 (Choi [0016])), and surrounding a plurality of second connection members (see Choi Fig. 1, connecting bumps 260 (Choi [0039])).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to add a non-conductive film taught by Choi to the device of Jung in order to further insulate the two dies from each other.
With respect to claim 20, Jung teaches the semiconductor package of claim 19.
Jung does not teach a non-conductive film (NCF) between the substrate and the interposer die, the NCF surrounding the plurality of first connection members.
Choi teaches a non-conductive film (NCF) (see Choi Fig. 7, first underfill layer 380 (Choi [0153])) between a substrate (see Choi Fig. 7, base layer 510 (Choi [0151])) and an interposer die (see Choi Fig. 7, first semiconductor chip 100 (Choi [0146])), the NCF surrounding a plurality of first connection members (see Choi Fig. 7, first connecting bumps 160 (Choi [0147])).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to add a non-conductive film taught by Choi to the device of Jung in order to further adhere the die to the substrate and offer further support underneath the die.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Jung, in view of Jo et al. (Pub. No.: US 20210407890 A1), hereinafter as Jo.
With respect to claim 6, Jung teaches the semiconductor structure of claim 1.
Jung does not teach that a footprint of the interposer die in top plan view is smaller than and included within a footprint of the slave die.
Jo teaches that a footprint of an interposer die (see Jo Fig. 8, first sub-integrated circuit device 11a (Jo [0076])) in top plan view (see Jo Fig. 1 and see Jo [0076]: “In FIG. 8, the first sub-integrated circuit device 11a may be substantially the same as or similar to a structure, in which a portion of the first integrated circuit device 11, the portion including the first TSV region (R1 of FIG. 1) in which the first TSV structures 120 are arranged, is separated,”) is smaller than and included within a footprint of a slave die (see Jo Fig. 8, second integrated circuit device 12 (Jo [0076])).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the size of the interposer die of Jung with the interposer die taught by Jo in order to electrically connect specific through vias.
Claims 7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Jung, in view of Song et al. (Pub. No.: US 20210193640 A1), hereinafter as Song.
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Image C: close up of Song Fig. 3A, showcasing neighboring connection members, connections pads, and through vias.
With respect to claim 7, Jung teaches the semiconductor structure of claim 1.
Jung does not teach an additional slave die on the slave die.
Song teaches an additional slave die (see Song Fig. 1, passive element chip 200 (Song [0019])) on a slave die (see Song Fig. 1, integrated voltage regulator (IVR) chip 100 (Song [0019])).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to add an additional slave die taught by Song to the device of Jung in order to include additional passive circuit elements (see Song [0031]: “The switch logic circuit may be connected to passive elements such as, for example, an inductor and a capacitor, disposed on the passive element chip 200. That is, the passive element chip 200 may include a passive element, and the passive element may be, for example, an inductor or a capacitor.”).
With respect to claim 9, Jung teaches the semiconductor structure of claim 8.
Jung does not teach that neighboring second connection members among the plurality of second connection members, and neighboring third connection pads among the plurality of third connection pads have a first pitch, neighboring first connection members among the plurality of first connection members, neighboring first connection pads among the plurality of first connection pads, and neighboring first through-silicon vias among the plurality of first through-silicon vias have a second pitch, and the second pitch is larger than the first pitch.
Song teaches that neighboring second connection members (see Image C) among a plurality of second connection members (see Song Fig. 3A, chip pad 322 (Song [0053])), and neighboring third connection pads (see Image C) among a plurality of third connection pads (see Song Fig. 3A, lower pad 105 (Song [0053])) have a first pitch (see Song Fig. 3A, first pitch P1 (Song [0054])), neighboring first connection members (see Image C) among a plurality of first connection members (see Song Fig. 3A, connection member 330 (Song [0055])), neighboring first connection pads (see Image C) among a plurality of first connection pads (see Song Fig. 3A, lower pads 305 (Song [0055])), and neighboring first through-silicon vias (see Image C) among a plurality of first through-silicon vias (see Song Fig. 3A, through-electrode 310 (Song [0055])) have a second pitch (see Song Fig. 3A, third pitch P3 (Song [0055])), and the second pitch is larger than the first pitch (see Song Fig. 3A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the pitches of Jung with the pitches taught by Song in order to prevent short circuit defects during bonding process (see Song [0044]: “In the case of bonding using the connection member, a sufficient distance may be secured between adjacent pads to prevent short circuit defects due to reflow during the bonding process.”).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Jung and Song, in view of Lee (Pub. No.: US 20160148906 A1).
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Image D: close up of Jung Fig. 29, showcasing contacting surfaces of second connection pad and member and second connection pads extending in a horizontal direction.
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Image E: close up of Lee Fig. 1E, showcasing contacting surfaces of second connection pad and first via.
With respect to claim 10, Jung and Song teach the semiconductor structure of claim 9, wherein the plurality of second connection pads (see Fig. 1, second pads 67; and see Image B, second connection pads) extend in a horizontal direction (see Image D, horizontal direction), and second surfaces (see Image D, second surface of second connection pad) of the plurality of second connection pads (see Fig. 1, second pads 67 (Jung [0088] and [0179]); and see Image B, second connection pads) are in contact with respective ones (see Image D, second surface of second connection member) of the plurality of second connection members (see Jung Fig. 29, third bumps 75).
Jung and Song do not teach that first surfaces of the plurality of second connection pads are in contact with respective ones of the plurality of first through-silicon vias.
Lee teaches first surfaces (see Image E, first surface of second connection pad) of a plurality of second connection pads (see Lee Fig. 1E, redistribution pads 113 (Lee [0080])) are in contact with respective ones (see Image E, respective surface of via) of a plurality of first through-silicon vias (see Lee Fig. 1E, first connection vias V1 (Lee [0080])).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the second connection pads of the combined device of Jung and Song to contact their respective vias like how Lee teaches in order to simplify manufacturing processes.
Claims 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Jung, in view of Lee (Pub. No.: US 20160148906 A1).
With respect to claim 13, Jung teaches the semiconductor structure of claim 8.
Jung does not teach that the slave die further comprises a plurality of third through-silicon vias.
Lee teaches that a slave die (see Lee Fig. 6, semiconductor chip 120 (Lee [0122])) further comprises a plurality of third through-silicon vias (see Lee Fig. 6, second dummy vias DV2 (Lee [0124])).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to add dummy vias taught by Lee to the device of Jung in order to mitigate and control stress in the device.
With respect to claim 14, Jung and Lee teach the semiconductor structure of claim 13, wherein the plurality of third through-silicon vias (see Lee Fig. 6, second dummy vias DV2) comprise dummy vias (the second dummy vias DV2 are dummy vias (Lee [0124])).
Claims 13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Jung, in view of Tong et al. (Pub. No.: US 20240379498 A1), hereinafter as Tong.
With respect to claim 13, Jung teaches the semiconductor structure of claim 8.
Jung does not teach that the slave die further comprises a plurality of third through-silicon vias.
Tong teaches that a slave die (see Tong Fig. 22A, processor die 2202 (Tong [0159])) further comprises a plurality of third through-silicon vias (see Tong Fig. 22B, conductive vias 2234 and 2238 (Tong [0160])).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to add additional vias taught by Tong to the device of Jung in order to provide more options for power connections (see Tong [0167]: “The [backside power delivery network (BSPDN)] may provide more opportunities of power connections for the semiconductor package 2200A from the backside of the semiconductor package 2200A in addition to the front side of the semiconductor package 2200A.”).
With respect to claim 15, Jung and Tong teach the semiconductor structure of claim 13, wherein the plurality of third through-silicon vias (see Tong Fig. 22B, conductive vias 2234 and 2238) transfer only power (see Tong [0167]: “According to some embodiments, the conductive vias, 2234 and 2238, may be configured to provide power to the first substrate 2220 through a backside (i.e., the second substrate side) of the processor die 2202,”).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EKATERINA T BIRCH whose telephone number is (571)272-8676. The examiner can normally be reached Mon-Fri, 8am-4pm ET.
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/E.T.B./Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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