Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Election/Restriction
In response to election/restriction, applicant elected claims 1-20 without traverse.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 6-11 are rejected under 35 U.S.C. 103 as being unpatentable over Ha et al. (US 2021/0217860, hereinafter Ha).
With respect to claim 1, Ha discloses a semiconductor device (Fig. 2) comprising: an active pattern (AP1 & CH1) comprising a lower pattern (AP1) and a plurality of sheet patterns (CP1/CP2/CP3) spaced apart from the lower pattern in a first direction (Fig.2 – CP1/CP2/CP3 are spaced apart from AP1 in vertical direction); a plurality of gate structures (GE &GS – Para 0028-0029) being spaced apart from each other in a second direction on the lower pattern (Fig. 2 -there are multiple GE structures and spaced apart from each other in horizontal direction) , wherein each of the plurality of gate structures comprises a gate electrode (GE) and a gate insulating layer (GS and Para 0078 – GS comprises of SiN); a source/drain recess between the gate structures adjacent to each other (opening to have SD structure is between the gate structures adjacent to each other); and a source/drain pattern filling the source/drain recess (SD1- there are multiple layers to form SD structure), wherein the source/drain pattern comprises: a first epitaxial region (SL2) extended along a sidewall and a bottom surface of the source/drain recess (Fig. 2), a second epitaxial region (SL3) on the first epitaxial region, and a plurality of insertion epitaxial regions (SL1 has different regions – Para 0050 and 0082) that are in contact with the first epitaxial region (SL1 regions are in contact with SL2), wherein the respective insertion epitaxial regions comprise of silicon germanium (para 0027 and 0053), and wherein the first epitaxial region is disposed between the second epitaxial region and the insertion epitaxial region (SL2 is between SL1 and SL3).
In the same embodiment, Ha does not explicitly disclose wherein the respective insertion epitaxial regions are spaced apart from each other.
In another embodiment, Ha discloses wherein the respective insertion epitaxial regions are spaced apart from each other (Figs. 7 & 8 – SL1 regions are spaced apart). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Ha’s first embodiment by having disclosure from second embodiment in order to improve the electrical characteristics and reduce an operating voltage of a semiconductor device.
With respect to claim 6, Ha discloses wherein the plurality of insertion
epitaxial regions comprise a first insertion epitaxial region and a second insertion epitaxial region, which are closest to each other in the first direction (Figs. 7 & 8 – SL1 regions are spaced apart), and wherein the first insertion epitaxial region is not in contact with the second insertion epitaxial region (Figs. 7 & 8 – SL1 regions are spaced apart).
With respect to claim 7, Ha discloses wherein the plurality of sheet patterns
comprises a first sheet pattern and a second sheet pattern, which are closest to each other in the first direction (Fig. 2 - CP1/CP2/CP3 are closer to each other in vertical direction), wherein the first sheet pattern and the second sheet pattern comprise an upper surface and a bottom surface (upper and lower surfaces of CP1/CP2/CP3), which are opposite to each other in the first direction (upper and lower surfaces are opposite to each other in vertical direction), wherein the upper surface of the first sheet pattern faces the bottom surface of the second sheet pattern (upper surface of the bottom sheet faces the bottom surface of the upper sheet), and wherein the insertion epitaxial region is continuously formed from the upper surface of the first sheet pattern to the bottom surface of the second sheet pattern (Fig. 7).
With respect to claim 8, Ha discloses wherein the insertion epitaxial region
comprises an inner side that is in contact with the first epitaxial region (Fig. 8 - SL1 is in contact with SL2), and wherein the inner side of the insertion epitaxial region has a concave shape (Fig. 8 - inner side of SL1 has concave shape).
With respect to claim 9, Ha discloses wherein each of the insertion epitaxial
regions comprises impurities (Para 0082), and wherein the impurities comprise at least one of arsenic (As), boron (B), or carbon (C) (Para 0081 – Boron).
With respect to claim 10, Ha discloses wherein the gate structure comprises an
inner gate structure (G1 of Fig. 2) disposed between the lower pattern (AP1) and the sheet pattern (CP1) and between adjacent sheet patterns (G1 is between CP1 & CP2), and wherein the insertion epitaxial region is in contact with the gate insulating layer of the inner gate structure (SL1s are in contact with the insulating layer/outer layer of G1).
With respect to claim 11, Ha discloses wherein the source/drain recess
comprises a plurality of width extension regions (Fig. 8 – WT1 & WT2), and
wherein a width of each of the width extension regions in the first direction is
increased and then reduced as each of the width extension regions becomes far away from the upper surface of the lower pattern (Fig. 8; Para 0067).
Claims 2-5 are rejected under 35 U.S.C. 103 as being unpatentable over
Ha in view of Bomberger et al. (US 2020/0303502, hereinafter Bomberger).
With respect to claim 2, Ha discloses the semiconductor device of claim 1.
Ha does not explicitly disclose wherein a germanium fraction of the
insertion epitaxial region is greater than that of the first epitaxial region.
In an analogous art, Bomberger discloses herein a germanium fraction of the
insertion epitaxial region is greater than that of the first epitaxial region (Para 0026 and 0028).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Ha’s device by having Bomberger’s disclosure in order to boost charge carrier mobility of a semiconductor device.
With respect to claim 3, Ha discloses wherein each of the first epitaxial region
and the second epitaxial region comprises silicon (Para 0053).
With respect to claim 4, Ha discloses wherein each of the first epitaxial region
and the second epitaxial region comprises silicon germanium (Para 0053).
With respect to claim 5, Ha discloses wherein a germanium fraction of the
second epitaxial region is greater than that of the first epitaxial region (Para 0054).
Claim 12-17 are rejected under 35 U.S.C. 103 as being unpatentable over
Cheng et al. (US 2020/0266060, hereinafter Cheng) in view of Ha.
With respect to claim 12, Cheng discloses a semiconductor device (Fig. 12A) comprising: an active pattern comprising a lower pattern (112) and a plurality of sheet patterns (114 & 116) spaced apart from the lower pattern in a first direction (114 & 116 are spaced apart from each in vertical direction); a plurality of gate structures (para 0031), wherein each of the plurality of gate structures (170) comprises a gate electrode (174) and a gate insulating layer (172); a source/drain recess (opening to create S/D) between the gate structures adjacent to each other (para 0031); and a source/drain pattern filling the source/drain recess (S/D),
wherein the gate structure comprises an inner gate structure between the lower pattern and the sheet pattern (lower gate structure 172& 174 between 112 & 114) and between the sheet patterns adjacent to each other (lower gate structure 172& 174 between 114 & 116), wherein the source/drain pattern comprises:
a plurality of insertion epitaxial regions (140s), and a first epitaxial region (150) that is in contact with each of the insertion epitaxial regions and is extended along a sidewall and a bottom surface of the source/drain recess (Fig. 12A), and wherein the plurality of insertion epitaxial regions are disposed between the lower pattern and the sheet pattern (140s are disposed between 112 & 114) and between the sheet patterns adjacent to each other in the first direction (140s are between 114 & 116) and are in contact with the gate insulating layer of the inner gate structure (140s are in contact with 172).
Cheng does not explicitly disclose that the gate structures being spaced apart from each other in a second direction on the lower pattern.
In an analogous art, Ha discloses that the gate structures being spaced apart from each other in a second direction on the lower pattern (there are multiple gate structure (G1&GS) thar are spaced apart from each other in horizontal direction and are on lower patter (CP1/CP2/CP3). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Cheng’s device by having Ha’s disclosure in order to improve electrical control over the conducting channel and reduce current leakage.
With respect to claim 13, Cheng discloses wherein each of the insertion epitaxial regions comprises silicon germanium (Para 0062).
With respect to claim 14, Cheng discloses wherein each of the insertion epitaxial regions comprises impurities, and wherein the impurities comprise at least one of arsenic (As), boron (B), or carbon (C) (Para 0062 – carbon doped)
With respect to claim 15, Cheng discloses wherein the first epitaxial region
comprises silicon (para 0067).
With respect to claim 16, Cheng discloses wherein the first epitaxial region
comprises silicon germanium (Para 0062 & 0067), and wherein a germanium fraction of the first epitaxial region is different from that of the insertion epitaxial region (Para 0062).
With respect to claim 17, Cheng discloses wherein the first epitaxial region is in
contact with each of the sheet patterns (150 is in contact with 114 & 116), and wherein the first epitaxial region is not in contact with the gate insulating layer of the inner gate structure (150 is not in contact with 172).
Allowable Subject Matter
Claims 18-20 have been allowed.
With respect to claim 18, none of the prior art on record disclose or render obvious the claimed limitations including “a source/drain pattern filling the source/drain recess, wherein the gate structure comprises an inner gate structure disposed between the lower pattern and the sheet pattern and between the sheet patterns adjacent to each other, wherein a width of each of the width extension regions in the first direction is increased and then reduced as each of the width extension regions becomes far away from an upper surface of the lower pattern, wherein a point at which a width of the width extension region in a second direction is maximum is positioned between the lower pattern and the sheet pattern and between the sheet patterns adjacent to each other in the first direction, wherein the source/drain pattern comprises:
a plurality of insertion epitaxial regions that are in contact with the gate insulating layer of the inner gate structure and include silicon germanium doped with arsenic (As), a first epitaxial region that is in contact with each of the insertion epitaxial regions and each of the sheet patterns, including silicon, and a second epitaxial region disposed on the first epitaxial region, including silicon doped with phosphorus (P)” when considered as a whole along with all of the limitations of the base claim and any intervening claims.
Claims 19-20 have been allowed because of their dependency on claim 18.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M CHOUDHRY whose telephone number is (571)270-5716. The examiner can normally be reached Monday - Friday.
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/MOHAMMAD M CHOUDHRY/Primary Examiner, Art Unit 2899
