DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-4, 6-10, 14 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US. Pub: 2021/0408496 A1~hereinafter “Choi”) of record in view of Chung et al. (US. Pat: 11,678,555 B2~ hereinafter “Chung”) of record.
Regarding claim 1, Choi discloses (in at least figs. 14-19) a display device comprising: a substrate (PI1, PI2; [0095]) comprising a non-display area and a display area (see at least fig. 1), the display area including an optical area (CA; see at least fig. 15) including a light-emitting area (best seen in at least fig. 15) and a transmissive area (see figs. 14 and 15), and a general area that is adjacent to the optical area (see figs. 14 and 15); a planarization layer (PLN2; [0105]; [0107]) disposed on the substrate in the display area; a plurality of light-emitting elements (see fig. 3) disposed on the planarization layer (see figs. 14 and 15), each including an anode (AND; see fig. 14; [0108]), a light-emitting layer (EL; [0109]), and a cathode (Cat; [0109]); a bank (BNK; [0108]-[0109]) disposed on the planarization layer (PNL2) and covering an end of the anode; and a deposition-suppressing layer (PCL) disposed on the light-emitting layer in the transmissive area between the light-emitting area and the transmissive area of the optical area (CA; see fig. 15), wherein the bank (BNK) is disposed in the light-emitting area and between the light-emitting area and the transmissive area of the optical area (see at least fig. 15).
Choi does not expressly disclose the light-emitting layer is disposed in both the light-emitting area and the transmissive area.
However, as can be seen in at least fig. 15 of Choi, the light-emitting layer is disposed in the light-emitting area, and the cathode is also disposed in the transmissive area.
One of ordinary skill in the art would have found it obvious before the effective filing date of the invention to consider forming the light-emitting layer in the transmissive area of Choi as well in order to reduce the manufacturing steps and cost of the device.
Chung in the same field of display device discloses (in at least fig. 7) a light-emitting layer (EL) that is disposed in both the light-emitting area (PA2) and the transmissive area (TA) in order to reduce the manufacturing steps and cost of the invention.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the display device of Choi with the teaching of Chung in order to reduce the manufacturing steps and cost of the device.
Regarding claim 2, Choi discloses (in at least figs. 14-19) an optical-electronic device (400) disposed on a lower portion of the substrate in the optical area (CA; see fig. 15).
Regarding claim 3, Choi discloses (in at least figs. 14-19) the deposition-suppressing layer (PCL) is disposed on a flat surface in the transmissive area of the optical area (see figs. 14 and 15).
Regarding claim 4, Choi discloses (in at least figs. 14-19) a bottom surface of the light-emitting layer (EL) adjoins the planarization layer (PLN2) in the transmissive area of the optical area.
Regarding claim 6, Choi discloses (in at least figs. 14-19) a side surface of the cathode (CAT) disposed in the light-emitting area of the optical area (CA) adjoins a side surface of the deposition-suppressing layer (PCL) disposed in the transmissive area of the optical area (CA).
Regarding claim 7, Choi discloses (in at least figs. 14-19) at least a part of the deposition-suppressing layer (PCL) has a constant thickness.
Regarding claim 8, Choi discloses (in at least figs. 14-19) the deposition-suppressing layer (PCL) comprises: a first part having the constant thickness (see fig. 15); and a second part that surrounds the first part, the second part having a smaller thickness than the first part (see fig. 15).
Regarding claim 9, Choi discloses (in at least figs. 14-19) the thickness of the second part decreases as a distance from the first part increases.
Regarding claim 10, Choi discloses (in at least figs. 14-19) the first part and the second part are integral to each other and made of a same material (see at least fig. 15).
Regarding claim 14, Choi as modified by Chung does not expressly disclose the deposition-suppressing layer does not overlap the light-emitting area.
However, it is well-known in the art to form a display device comprised of, in part, a deposition-suppressing layer does not overlap the light-emitting area as evident by Lim et al. (US. Pat: 11,678,560 B2~ hereinafter “Lim”) of record at least fig. 5, which discloses “a deposition-suppressing layer (142) that does not overlap the light-emitting area (DA; see fig. 5).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the display device of Choi and Chung with the deposition-suppressing layer arrangement teaching of Kim, since it has been held that rearranging parts of an invention involves only routine skill in the art.
Regarding claim 15, Choi as modified by Chung and Lim discloses (in at least fig. 5 Kim) the cathode (140) is not disposed in the transmissive area (TA) and is disposed in the light-emitting area (DA).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US. Pub: 2021/0408496 A1~hereinafter “Choi”) of record in view of Chung et al. (US. Pat: 11,678,555 B2~ hereinafter “Chung”) of record and further in view of Han et al. (US. Pub: 2021/0193754 A1~hereinafter “Han”) of record.
Regarding claim 5, Choi discloses (in at least figs. 14-19) the deposition-suppressing layer (PCL) and the bank (BNK).
Choi does not expressly disclose the deposition-suppressing layer and the bank do not overlap each other in the optical area.
Han discloses (in at least figs. 4 and 5) a deposition-suppressing layer (144) and a bank (138) that do not overlap each other in the optical area.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the display device of Choi and Chung with the deposition arrangement of Han, since it has been held that rearranging parts of an invention involves only routine skill in the art.
Claim(s) 11-13, 16 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US. Pub: 2021/0408496 A1~hereinafter “Choi”) in view of Lim et al. (US. Pat: 11,678,560 B2~hereinafter “Lim”) and further in view of Chung et al. (US. Pat: 11,678,555 B2~ hereinafter “Chung”) of record.
Regarding claim 11, Choi discloses (in at least figs. 14-19) a display device comprising: a substrate (PI1, PI2) comprising a non-display area and a display area (see at least fig. 1), the display area including an optical area (CA) including a light-emitting area and a transmissive area (best seen in at least fig. 15), and a general area that is adjacent to the optical area (see fig. 15); a planarization layer (PLN2) disposed on the substrate in the display area; a plurality of light-emitting elements (best seen in at least figs. 3 and 15) disposed on the planarization layer (PLN2), each including an anode (AND; [0108]), a light-emitting layer (EL; [0109]) and a cathode (CAT); a deposition-suppressing layer (PCL) disposed on the light-emitting layer in the transmissive area, and an optical-electronic device (400) disposed on a lower portion of the substrate in the optical area (see fig. 15), wherein the optical-electronic device (400) overlaps the deposition-suppressing layer.
Choi does not expressly disclose the deposition-suppressing layer does not overlap the cathode; and the light-emitting layer is disposed in both the light-emitting area and the transmissive area.
Lim discloses (in at least fig. 5) a display device comprised of, in part, a deposition-suppressing layer (142) that does not overlap the cathode (140) in the transmissive area (TA; see fig. 5).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to rearrange the deposition-suppressing layer of Choi as taught by Han, since it has been held that rearranging parts of an invention involves only routine skill in the art.
Lim does not expressly disclose the light-emitting layer is disposed in both the light-emitting area and the transmissive area.
However, as can be seen in at least fig. 15 of Choi, the light-emitting layer is disposed in the light-emitting area, and the cathode is also disposed in the transmissive area.
One of ordinary skill in the art would have found it obvious before the effective filing date of the invention to consider forming the light-emitting layer in the transmissive area of Choi as well in order to reduce the manufacturing steps and cost of the device.
Chung in the same field of display device discloses (in at least fig. 7) a light-emitting layer (EL) that is disposed in both the light-emitting area (PA2) and the transmissive area (TA) in order to reduce the manufacturing steps and cost of the device.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the display device of Choi and Lim with the teaching of Chung in order to reduce the manufacturing steps and cost of the device.
Regarding claim 12, Choi discloses (in at least figs. 14-19) a bank (BNK) disposed on the planarization layer (PLN2) and covering an end of the anode (AND), wherein the bank (BNK) is disposed in the light-emitting area.
Regarding claim 13, Choi discloses (in at least figs. 14-19) the deposition-suppressing layer (PCL) is disposed on a flat surface in the transmissive area.
Regarding claim 16, Choi as modified by Chung does not expressly disclose the deposition-suppressing layer does not overlap the light-emitting area.
However, it is well-known in the art to form a display device comprised of, in part, a deposition-suppressing layer does not overlap the light-emitting area as evident by Lim et al. (US. Pat: 11,678,560 B2~ hereinafter “Kim”) of record at least fig. 5, which discloses “a deposition-suppressing layer (142) that does not overlap the light-emitting area (DA; see fig. 5).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the display device of Choi and Chung with the deposition-suppressing layer arrangement teaching of Kim, since it has been held that rearranging parts of an invention involves only routine skill in the art.
Regarding claim 17, Choi as modified by Chung and Lim discloses (in at least fig. 5 Lim) the cathode (140) is not disposed in the transmissive area (TA) and is disposed in the light-emitting area (DA).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELMITO BREVAL whose telephone number is (571)270-3099. The examiner can normally be reached M-Th~ 7:30-5:30.
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ELMITO BREVAL
Primary Examiner
Art Unit 2875
/ELMITO BREVAL/Primary Examiner, Art Unit 2875
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