DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Remarks
This action is in response to the amendments received on 2/10/26. Claims 1-20 are pending in the application. Applicants' arguments have been carefully and respectfully considered.
Claim(s) 1-6, 8-10, 17, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Ki et al. (US 2023/0273731), and further in view of Helmick et al. (US 2021/0374067).
Claims 7 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ki in view of Helmick, and further in view of Grigorik, SSTable and Log Structured Storage: Level DB, February 6, 2012.
Claims 11, 13, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Benisty et al. (US 2022/0107893), and further in view of Helmick et al. (US 2021/0374067).
Claims 12 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Benisty in view of Helmick, and further in view of Ki et al. (US 2023/0273731).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Benisty in view of Helmick and Ki, and further in view of Howard et al. (US 2002/0073276).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Ki in view of Helmick, and further in view of Howard et al. (US 2002/0073276).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6, 8-10, 17, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Ki et al. (US 2023/0273731), and further in view of Helmick et al. (US 2021/0374067).
With respect to claim 1, Ki teaches a method, comprising:
communicating between a host system and a memory sub-system (Ki, Fig. 4 & pa 0036, the volatile memory is shown divided into three areas 305-1, 305-2, and 305-3, which may also be referred to collectively as areas 305. & pa 0037, Persistent memory spaces 310 and 315 may represent exposed available storage in the underlying non-volatile storage) over a connection configured to support a first protocol of cache coherent memory access and using a second protocol of storage access, the memory sub-system including a first portion access via the first protocol and a second portion accessed via the second protocol (Ki, pa 0060, Cache coherent interconnect protocols such as CXL may offer different types of commands to access persistent memory device 135. For example, CXL offers the CXL.IO and the CXL.MEMORY protocols, which may offer different ways to access persistent memory device 135. CXL.IO protocol may function similar to the Peripheral Component Interconnect Express (PCie) standard (which may be used to access storage devices such as storage device 120 of FIG. 1), whereas the CXL.MEMORY protocol may be used to access storage devices such as memory 115 of FIG. 1.);
storing, to a first portion of the memory sub-system, first data identifying one or more first changes to a database over the connection using the first protocol of cache coherent memory access; storing, to the first portion of the memory sub-system, second data identifying one or more second changes to the database over the connection using the first protocol of cache coherent memory access (Ki, pa 0046, area 305-3 may be used to store redo log data. When a server, such as a database server, makes changes to data stored on machine 105 of FIG. 1, the particular changes themselves (as compared with the changed data) may be stored in persistent memory device 135 as a redo log.); and
automatically writing, in response to determining that a size of the first data and the second data reaches a threshold, the first data and the second data into … the second portion of the memory sub-system accessible via the second protocol of storage access (Ki, pa 0048, One question that may arise is what to do if area 305-3 is full (there are no free cache lines) but the database server attempts to write a new redo log to area 305-3. Rather than evicting a redo log from area 305-3 (and writing it to the non-volatile storage), persistent memory device 135 to reject the request to write the data to area 305-3. At that point, the database server may write data into area 305-2 to update actual stored data, and once that store request is complete, the corresponding redo logs in area 305-3 may be deleted freeing up one or more cache lines for new redo logs).
Ki doesn't expressly discuss writing, based on a determination that an amount of the first and second data exceeding a threshold, the first data and the second data automatically into a file hosted in the second portion of the memory sub-system.
Helmick teaches automatically writing, in response to determining that a size of the first and second data stored in the first portion reaches a threshold, the first data and the second data automatically into a file hosted in the second portion of the memory sub-system (Helmick, Fig. 4 & pa 0058, The DRAM 410 comprises a first logical to physical address (L2P) table 420 and one or more change log tables 430 (referred to as change log table 430). Examiner Note: change log tables 430 are in volatile memory & pa 0064, once the change log table 430 is at capacity, the change log table is copied to the second L2P table 440 in the NVM 404. Examiner note: when full, change log table is copied to table in non-volatile memory).
It would have been obvious at the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Ki with the teachings of Helmick because it provides a mapping between the logical and physical addresses of the commands from the host (Helmick, pa 0058).
With respect to claim 2, Ki in view of Helmick teaches the method of claim 1, wherein the connection is a computer express link (CXL) connection (Ki, pa 0060, persistent memory device 135 may be use a cache coherent interconnect protocol, such as the Compute Express Link (CXL) protocol.).
With respect to claim 3, Ki in view of Helmick teaches the method of claim 2, wherein the first portion of the memory sub-system is addressable by the host system using memory addresses configured in store instructions; and the second portion of the memory sub-system is addressable by the host system using logical block addresses configured in write commands (Ki, pa 0080, At block 710, controller 335 of FIG. 3 may be locate an address in the volatile storage of persistent memory device 135 of FIG. 1. Note that the data might be stored in area 305-2 of FIG. 3 if, for example, the host had previously sent data to be written for that logical identifier, but the data had not yet been committed to the non-volatile storage of persistent memory device 135 of FIG. 1.).
With respect to claim 4, Ki in view of Helmick teaches the method of claim 3, wherein the first data and the second data are written into the second portion of the memory sub-system via a write command into a file hosted in the second portion of the memory sub-system (Ki, pa 0046, when a server, such as a database server, makes changes to data stored on machine 105 of FIG. 1, the particular changes themselves (as compared with the changed data) may be stored in persistent memory device 135 as a redo log.).
With respect to claim 5, Ki in view of Helmick teaches the method of claim 4, wherein the first data and the second data are stored into the first portion of the memory sub-system via store instructions executed in host system identifying memory addresses in the first portion of the memory sub-system (Ki, pa 0083, In FIG. 9, at block 905, persistent memory device 135 of FIG. 1 may receive a store request from a host, such as database server 405 of FIG. 4. At block 910, controller 335 of FIG. 3 may be locate an address in area 305-2 of FIG. 3 of the volatile storage of persistent memory device 135 of FIG. 1 where the original data is stored. At block 715, persistent memory device 135 of FIG. 1 may update the original data at the located address using the change data.).
With respect to claim 6, Ki in view of Helmick teaches the method of claim 5, wherein the first data includes a first write-ahead log entry; and the second data includes a second write-ahead log entry (Ki, pa 0096, When the data block is modified and becomes dirty, the database server may capture all changes made by the database server for this transaction and may create a redo log entry in the redo log buffer).
With respect to claim 8, Ki in view of Helmick teaches the method of claim 5, wherein the write command is configured to identify data to be written at a logical block address in the second portion of the memory sub-system by a reference to the first portion of the memory sub-system (Ki, pa 0080, At block 710, controller 335 of FIG. 3 may be locate an address in the volatile storage of persistent memory device 135 of FIG. 1. Note that the data might be stored in area 305-2 of FIG. 3 if, for example, the host had previously sent data to be written for that logical identifier, but the data had not yet been committed to the non-volatile storage of persistent memory device 135 of FIG. 1.).
With respect to claim 9, Ki in view of Helmick teaches the method of claim 1, further comprising providing an indication of an amount of available memory of the memory sub-system to be considered non-volatile by the host system (Ki, pa 0048, One question that may arise is what to do if area 305-3 is full (there are no free cache lines) but the database server attempts to write a new redo log to area 305-3. Rather than evicting a redo log from area 305-3 (and writing it to the non-volatile storage), persistent memory device 135 to reject the request to write the data to area 305-3.).
With respect to claim 10, Ki in view of Helmick teaches the method of claim 5, wherein after the first data and the second data are stored in the first portion of the memory sub-system, the writing of the first data and the second data into the second portion of the memory sub-system includes no communications of the first data and the second data over the computer express link (CXL) connection (Ki, pa 0100, Embodiments of the disclosure may include a Compute Express Link (CXL)-SSD to provide one persistent memory space based on NAND backing store and DRAM cache. Examiner note: writes within persistent memory device do not go over connection).
With respect to claim 17, Ki teaches a non-transitory computer storage medium storing instructions which, when executed in a computing system, cause the computing system to perform a method, comprising:
writing, using a storage protocol through a connection to a host interface of a memory sub-system (Ki, pa 0060, CXL.IO protocol may function similar to the Peripheral Component Interconnect Express (PCie) standard (which may be used to access storage devices such as storage device 120 of FIG. 1)), records of a database into a storage portion of the memory sub-system (Ki, pa 0037, The volatile storage may be backed, in whole or in part, by underlying non-volatile storage. The underlying non-volatile storage may include, for example, one or more SSDs. Persistent memory spaces 310 and 315 may represent exposed available storage in the underlying non-volatile storage);
storing, using a cache coherent memory access protocol through the connection (Ki, pa 0060, persistent memory device 135 may be use a cache coherent interconnect protocol, such as the Compute Express Link (CXL) protocol.), first data identifying first changes and second data identifying second changes into a memory portion of the memory sub-system prior to making the first and second changes to the database (Ki, pa 0046, pa 0046, when a server, such as a database server, makes changes to data stored on machine 105 of FIG. 1, the particular changes themselves (as compared with the changed data) may be stored in persistent memory device 135 as a redo log. & pa 0048, the database server may write data into area 305-2 to update actual stored data, and once that store request is complete, the corresponding redo logs in area 305-3 may be deleted freeing up one or more cache lines for new redo logs);
writing, in response to a determination that an amount of the first and second data identifying the first and second changes reaching a threshold, the first and second data identifying the first and second changes automatically to a file in the memory sub-system (Ki, pa 0048, One question that may arise is what to do if area 305-3 is full (there are no free cache lines) … the database server may write data into area 305-2 to update actual stored data, and once that store request is complete, the corresponding redo logs in area 305-3 may be deleted freeing up one or more cache lines for new redo logs); and
making the changes to the database after the data is stored in the memory portion of the memory sub-system (Ki, pa 0047, Because redo logs may be stored only long enough to ensure that the actual changed data itself is written, redo logs may be thought of as temporary files: they may be deleted once the changes are actually written to machine 105 of FIG. 1.).
Ki doesn't expressly discuss writing, in response to a determination that an amount of the first and second data identifying the first and second changes reaching a threshold, the first and second data identifying the first and second changes automatically to a file in the memory sub-system.
Helmick teaches automatically writing, in response to determining that a size of the first and second data reaches a threshold, the first and second data to a file in the storage portion of the memory sub-system (Helmick, Fig. 4 & pa 0058, The DRAM 410 comprises a first logical to physical address (L2P) table 420 and one or more change log tables 430 (referred to as change log table 430). Examiner Note: change log tables 430 are in volatile memory & pa 0064, once the change log table 430 is at capacity, the change log table is copied to the second L2P table 440 in the NVM 404. Examiner note: when full, change log table is copied to table in non-volatile memory).
It would have been obvious at the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Ki with the teachings of Helmick because it provides a mapping between the logical and physical addresses of the commands from the host (Helmick, pa 0058).
With respect to claim 18, Ki in view of Helmick teaches the non-transitory computer storage medium of claim 17, wherein the connection is a computer express link (CXL) connection (Ki, pa 0060, persistent memory device 135 may be use a cache coherent interconnect protocol, such as the Compute Express Link (CXL) protocol.).
Claims 7 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ki in view of Helmick, and further in view of Grigorik, SSTable and Log Structured Storage: Level DB, February 6, 2012.
With respect to claim 7, Ki in view of Helmick teaches the method of claim 5, as discussed above. Ki in view of Helmick doesn't expressly discuss wherein the first data and the second data are stored into a simply sorted table in the first portion of the memory sub-system.
Grigorik teaches wherein the first data and the second data are stored into a simply sorted table in the first portion of the memory sub-system (Grigorik, item 1, On-disk SSTable indexes are always loaded into memory), wherein the data is stored into the simple sorted tables (Grigorik, 4th pa, Read in the entire file sequentially and you have a sorted index. Optionally, if the file is very large, we can also prepend, or create a standalone key: offset index for fast access.).
It would have been obvious at the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Ki in view of Helmick to have included the teachings of Grigorik because it is a useful way to exchange large, sorted data segments (Grigorik, 4th pa).
With respect to claim 20, Ki in view of Helmick teaches the non-transitory computer storage medium of claim 18, as discussed above. Ki in view of Helmick doesn't expressly discuss creating simple sorted tables in the memory portion of the memory sub-system, wherein the data is stored into the simple sorted tables.
Grigorik teaches wherein the method further comprises: creating simple sorted tables in the memory portion of the memory sub-system (Grigorik, item 1, On-disk SSTable indexes are always loaded into memory), wherein the data is stored into the simple sorted tables (Grigorik, 4th pa, Read in the entire file sequentially and you have a sorted index. Optionally, if the file is very large, we can also prepend, or create a standalone key: offset index for fast access.).
It would have been obvious at the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Ki in view of Helmick to have included the teachings of Grigorik because it is a useful way to exchange large, sorted data segments (Grigorik, 4th pa).
Claims 11, 13, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Benisty et al. (US 2022/0107893), and further in view of Helmick et al. (US 2021/0374067).
With respect to claim 11, Benisty teaches a memory sub-system, comprising:
a host interface (Benisty, Fig. 1, host 102);
volatile memory, wherein the memory sub-system is operable to allocate a portion of the volatile memory to provide memory services to a host system over a connection (Benisty, pa 0024, The data storage device 110 includes a device controller 112, a volatile memory, such as a dynamic random-access memory (DRAM));
non-volatile memory (Benisty, pa 0024, The data storage device 110 includes… one or more non-volatile memory devices, such as one or more NVMs 140a-n.); and
a controller (Benisty, pa 0024, The data storage device 110 includes a device controller 112) configured to:
receive, over the connection via the memory services and in the portion of the volatile memory (Benisty, pa 0030, the device controller 112 may use volatile memory as a cache. For instance, the device controller 112 may store cached information in volatile memory until cached information is written to the one or more NVMs 140a-n.), first data identifying first changes and the second data identifying second changes to a database having records in the non-volatile memory (Benisty, pa 0031, when the data storage device 110 receives a write command from the host computer system 102, the controller 112 temporarily stores the data associated with the write command in the internal memory or a write buffer, such as a write cache buffer 132, before sending the data to the one or more NVMs 140a-n. & pa 0041, the write cache manager to receive the next write command. Examiner note: write buffer may include two write commands); and
writing the first data identifying the first changes and the second data identifying the second changes to a file in the non-volatile memory automatically (Benisty, pa 0041, if the “(D*t)<TH*maxDataWritten” is returns a false value (i.e., “D*t” is greater than “TH*maxDataWritten”), then the flush decision engine flushes the data to the NVM at block 210.) in response to determining that a size of the first and second data stored in the portion of the volatile memory reaches a threshold (Benisty, pa 0040, the write cache manager calculates the maximum data written (maxDataWritten). The “maxDataWritten” may be calculated using the following formula: maxDataWritten=maxD*tStop, where “maxD” is the maximum capacity of the write cache and the “tStop” is the hard stop time parameter. At block 214, the formula, (D*t)<TH*maxDataWritten, where “D” is the amount of data currently stored in the write cache buffer and “TH” is the maximum data allowed to be written to the write cache buffer prior to flushing write cache buffer to the NVM, is utilized by the flush decision engine to determine if the write cache buffer should be flushed. Examiner note: amount of data in cache buffer represents first and second data identifying first and second changes).
Benisty doesn't expressly discuss writing the first data identifying the first changes and the second data identifying the second changes to a file in the non-volatile memory.
Helmick teaches volatile memory, wherein the memory sub-system is operable to allocate a portion of the volatile memory to provide memory services to a host system over a connection (Helmick, pa 0021, The storage device 106 includes … a first random-access memory (RAM) or volatile memory 112, such as a dynamic random-access memory (DRAM) & pa 0023, The interface 114 of the storage device 106 may include one or both of a data bus for exchanging data with the host device 104 and a control bus for exchanging commands with the host device 104.);
…
writing the first data identifying the first changes and the second data identifying the second changes to a file in the non-volatile memory automatically in response to determining that a size of the first and second data stored in the portion of the volatile memory reaches a threshold (Helmick, Fig. 4 & pa 0058, The DRAM 410 comprises a first logical to physical address (L2P) table 420 and one or more change log tables 430 (referred to as change log table 430). Examiner Note: change log tables 430 are in volatile memory & pa 0064, once the change log table 430 is at capacity, the change log table is copied to the second L2P table 440 in the NVM 404. Examiner note: when full, change log table is copied to table in non-volatile memory).
It would have been obvious at the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Benisty with the teachings of Helmick because it provides a mapping between the logical and physical addresses of the commands from the host (Helmick, pa 0058).
With respect to claim 13, Benisty in view of Helmick teaches the memory sub-system of claim 11, wherein the controller is configured to communicate with the host system over the connection to write the data to the file (Benisty, pa 0025, the data storage device 110 may include an interface, which may include one or both of a data bus (e.g., an ingress bus 150a and an egress bus 150b) for exchanging data with the host computer system 102 and a control bus for exchanging commands with the host computer system 102. & Helmick, pa 0023, The interface 114 of the storage device 106 may include one or both of a data bus for exchanging data with the host device 104 and a control bus for exchanging commands with the host device 104.).
With respect to claim 14, Benisty in view of Helmick teaches the memory sub-system of claim 13, wherein the controller is configured to read the first and second data from the file and stored the first and second data into the portion of the volatile memory in response to a request from the host system over the connection (Benisty, pa 0030, the device controller 112 may store cached information in volatile memory until cached information is written to the one or more NVMs 140a-n. & (Helmick, pa 0027, When the controller 108 receives a command, such as from a host device 104, the controller 108 can read data from and write data to the plurality of logical blocks associated with the plurality of erase blocks of the NVM 110.).
Claims 12 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Benisty in view of Helmick, and further in view of Ki et al. (US 2023/0273731).
With respect to claim 12, Benisty in view of Helmick teaches the memory sub-system of claim 11, as discussed above.
Ki teaches wherein the connection is a computer express link (CXL) connection (Ki, pa 0060, persistent memory device 135 may be use a cache coherent interconnect protocol, such as the Compute Express Link (CXL) protocol.).
It would have been obvious at the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Benisty in view of Helmick with the teachings of Ki because it provides memory expansion.
With respect to claim 15, Benisty in view of Helmick teaches the memory sub-system of claim 14, as discussed above.
Ki teaches wherein the memory subsystem further comprises a backup power source configured to be sufficient to at least allow the controller to continue operations to preserve content in the portion of the volatile memory into the non-volatile memory in response to an interruption in an external power supply to the memory sub-system (Ki, pa 0041, Backup power source 325 may provide sufficient power such that, in case of a power loss or power interruption, the data stored in area 305-2 may be maintained until it is written to the nonvolatile storage.).
It would have been obvious at the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Benisty in view of Helmick with the teachings of Ki because it provides sufficient power in the case of a power loss so the data is not lost (pa 0041).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Benisty in view of Helmick and Ki, and further in view of Howard et al. (US 2002/0073276).
With respect to claim 16, Benisty in view of Helmick and Ki teaches the memory sub-system of claim 15, as discussed above. Benisty in view of Helmick and Ki doesn't expressly discuss wherein the data includes write-ahead log entries.
Howard teaches wherein the data includes write-ahead log entries (Howard, pa 0042, At various times, log recorder 121 creates log records to be written to write-ahead hash log 134. … A new log block is constructed by log recorder 121 by detecting newly modified data blocks from block cache 127).
It would have been obvious at the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Benisty in view of Helmick and Ki with the teachings of Howard because it maintains a record of changes such that in the event of a network or disk failure the records of the write ahead log can be used (Howard, pa 0009).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Ki in view of Helmick, and further in view of Howard et al. (US 2002/0073276).
With respect to claim 19, Ki in view of Helmick teaches the non-transitory computer storage medium of claim 18, wherein the method further comprises: storing the data from the memory portion to the storage portion (Ki, pa 0071, data 510 may be copied into persistent memory space 310 as data 515 in the non-volatile storage to ensure that data 510 is not lost should power be interrupted.).
Ki in view of Helmick doesn't expressly discuss wherein the generating includes performing write-ahead logging to generate the data including write-ahead log entries.
Howard teaches wherein the generating includes performing write-ahead logging to generate the data including write-ahead log entries (Howard, pa 0029, the log record containing the updated hash value has been successfully written to write ahead hash log 134 & pa 0042, At various times, log recorder 121 creates log records to be written to write-ahead hash log 134. … A new log block is constructed by log recorder 121 by detecting newly modified data blocks from block cache 127);
It would have been obvious at the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Ki in view of Helmick with the teachings of Howard because it maintains a record of changes such that in the event of a network or disk failure the records of the write ahead log can be used (Howard, pa 0009).
Response to Amendment
35 U.S.C. 112
With regard to claims 1-16, the amendments to the claims have overcome the 35 U.S.C. 112 rejection. The Examiner withdraws the 35 U.S.C. 112 rejection to claims 1-16.
Response to Arguments
35 U.S.C. 102 and 103
With respect to claims 1-20, Applicant’s amendment has rendered the previous rejection moot. Upon further consideration of the amendment, a new grounds of rejection is made in view of Helmick et al. (US 2021/0374067).
Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRITTANY N ALLEN whose telephone number is (571)270-3566. The examiner can normally be reached M-F 9 am - 5:00 pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sherief Badawi can be reached at 571-272-9782. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRITTANY N ALLEN/ Primary Examiner, Art Unit 2169
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