DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note by the Examiner
For clarity, references to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and examiner explanations for 102 &/or 103 rejections are provided in parenthesis.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 20 states “a gate cutting pattern” in the ninth line of the claim. It later on states “wherein a gate cutting pattern” in the fortieth line of the claim. There is a discrepancy in the antecedent basis. For examination purposes, this will be treated as the same feature.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 10, 13, 14, 16, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kanemura et al. (Pub. No.: US 20170236872 A1), herein after as Kanemura.
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Image A.1: Kanemura Fig. 5A showing Gate and Channel cutting patterns
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Image A.2: Kanemura Fig. 5A showing sides of gate cutting pattern
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Image A.3: Kanemura Fig. 5A showing sides of gate cutting pattern
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Image B: close up of Kanemura Fig. 5A showing 1st and 2nd memory channel structures contacting the gate cutting pattern
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Image C: showcasing that the space next to the connection parts act as the first and second separation structures in Kanemura
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Image D: close up of Kanemura Fig. 5A showing width difference between the gate cutting pattern and the memory channel structures
With regards to claim 1, Kanemura teaches a semiconductor device, comprising: a first conductive pattern (see Kanemura Fig. 5A, conductive layer 42A) including a first connection part (see Kanemura Fig. 5A and Image A.2, connecting part 42Ab) and a plurality of first branch parts (see Kanemura Fig. 5A and Image A.3, branch parts 42Aa) connected to the first connection part (see Kanemura Fig. 5A); a second conductive pattern (see Kanemura Fig. 5A, conductive layer 42B) including a second connection part (see Image A.3) and a plurality of second branch parts (see Kanemura Fig. 5A and Image A.2, branch parts 42Ba) connected to the second connection part (see Kanemura Fig. 5A); a first memory channel structure (see Kanemura Fig. 5A, columnar semiconductor layer 43 and variable resistance films 44A and 44B) in contact with a corresponding one of the plurality of first branch parts and a corresponding one of the plurality of second branch parts (see Kanemura Fig. 5A); and a gate cutting pattern (see Kanemura Fig. 5A and above Image A.1, where the space between the first connection part and the second branch act as the gate cutting pattern) including a first side (see Image A.2 and A.3) and a second side (see Image A.2 and A.3), the first side and the second side being opposite to each other (see Image A.2 and A.3) in an extension direction (in the y-direction) of the plurality of first branch parts and the plurality of second branch parts (see Kanemura Fig. 5A), (1) the first side being in contact with a corresponding one of the plurality of second branch parts (see Image A.2) and the second side being in contact with the first connection part (see Image A.2) or (2) the first side being in contact with the second connection part (see Image A.3) and the second side being in contact with a corresponding one of the plurality of first branch parts (see Image A.3), wherein the first conductive pattern and the second conductive pattern are spaced apart from each other (see Kanemura Fig. 5A).
With regards to claim 2, Kanemura teaches the semiconductor device of claim 1, wherein the plurality of first branch parts (see Kanemura Fig. 5A and Image A.3, branch parts 42Aa) and the plurality of second branch parts (see Kanemura Fig. 5A and Image A.2, branch parts 42Ba) are arranged alternately with each other (see Kanemura Fig. 5A).
With regards to claim 3, Kanemura teaches the semiconductor device of claim 1, further comprising: a channel cutting pattern (see Kanemura Fig. 5A and above Image A.1) in contact with the first memory channel structure (see Kanemura Fig. 5A, columnar semiconductor layer 43 and variable resistance films 44A and 44B), the corresponding one of the plurality of first branch parts (see Kanemura Fig. 5A and Image A.3, branch parts 42Aa), and the corresponding one of the plurality of second branch parts (see Kanemura Fig. 5A and Image A.2, branch parts 42Ba).
With regards to claim 10, Kanemura teaches the semiconductor device of claim 1, further comprising: a bit line (see Kanemura Fig. 18, conductive layer 36 (upper global bit line GBLU)) electrically connected to the first memory channel structure (see Kanemura Fig. 18), wherein the plurality of first branch parts and the plurality of second branch parts (see Kanemura Fig. 5A and Images A.2 & A.3, branch parts 42Aa and 42Ba) extend in a first direction (see Kanemura Figs. 5A and 18, where they extend in the x-direction), and wherein the bit line extends in a second direction intersecting the first direction (see Kanemura Fig. 18, where it extends in the y-direction).
With regards to claim 13, Kanemura teaches the semiconductor device of claim 1, further comprising: a second memory channel structure (see Kanemura Fig. 5A, columnar semiconductor layer 43 and variable resistance films 44A and 44B, and above Image B) adjacent to the first memory channel structure (see Kanemura Fig. 5A, columnar semiconductor layer 43 and variable resistance films 44A and 44B, and above Image B), wherein the gate cutting pattern (see Kanemura Fig. 5A and above Image A.1) is in contact with the first memory channel structure and the second memory channel structure (see Kanemura Fig. 5A and above Image A.1).
With regards to claim 14, Kanemura teaches the semiconductor device of claim 1, further comprising: a first separation structure (see Kanemura Fig. 5A & 18 and Image C, where the space next to the connection parts act as the first and second separation structures) and a second separation structure (see Kanemura Fig. 5A & 18 and Image C, where the space next to the connection parts act as the first and second separation structures) spaced apart from each other (see Kanemura Fig. 5A & 18 and Image C), the first separation structure being in contact with the first connection part (see Kanemura Fig. 5A & 18 and Image C) and the second separation structure being in contact with the second connection part (see Kanemura Fig. 5A & 18 and Image C), wherein at least a portion of the first connection part is between the gate cutting pattern (see Kanemura Fig. 5A and above Image A.1) and the first separation structure (see Kanemura Fig. 5A and Image C).
With regards to claim 16, Kanemura teaches a semiconductor device, comprising: a first separation structure (see Kanemura Fig. 5A & 18 and Image C, where the space next to the connection parts act as the first and second separation structures); a second separation structure (see Kanemura Fig. 5A & 18 and Image C, where the space next to the connection parts act as the first and second separation structures) adjacent to the first separation structure (see Kanemura Fig. 5A & 18 and Image C); a first conductive pattern (see Kanemura Fig. 5A, conductive layer 42A) between the first separation structure and the second separation structure (see Kanemura Fig. 5A & 18 and Image C), the first conductive pattern including a first connection part (see Kanemura Fig. 5A and Image A.2, connecting part 42Ab) in contact with the first separation structure (see Kanemura Fig. 5A & 18 and Image C) and a first branch part (see Kanemura Fig. 5A and Image A.3, branch parts 42Aa) connected to the first connection part (see Kanemura Fig. 5A); a second conductive pattern (see Kanemura Fig. 5A, conductive layer 42B) between the first separation structure and the second separation structure (see Kanemura Fig. 5A & 18 and Image C), the second conductive pattern including a second connection part (see Image A.3) in contact with the second separation structure (see Kanemura Fig. 5A & 18 and Image C) and a second branch part (see Kanemura Fig. 5A and Image A.2, branch parts 42Ba) connected to the second connection part (see Kanemura Fig. 5A); and a plurality of memory channel structures (see Kanemura Fig. 5A, columnar semiconductor layer 43 and variable resistance films 44A and 44B) in contact with the first branch part and the second branch part (see Kanemura Fig. 5A); and a gate cutting pattern (see Kanemura Fig. 5A and above Image A.1, where the space between the first connection part and the second branch act as the gate cutting pattern) separating the first connection part and the second branch part from each other (see Image A.1 and Image A.2), the gate cutting pattern including a first side (see Image A.2, 2nd side) and a second side (see Image A.2, 1st side), the first side and the second side being opposite to each other (see Image A.2) in an extension direction (in the y-direction) of the first branch part and the second branch part (see Image A.2), the first side being in contact with the first connection part (see Image A.2) and the second side being in contact with the second branch part (see Image A.2), wherein the first branch part and the second branch part are spaced apart from each other (see Kanemura Fig. 5A).
With regards to claim 19, Kanemura teaches the semiconductor device of claim 16, wherein a width (see Kanemura Fig. 5A and above Image D) of the gate cutting pattern (see Kanemura Fig. 5A and above Image A.1) is greater than a width (see Kanemura Fig. 5A and above Image D) of each of the plurality of memory channel structures (see Kanemura Fig. 5A, columnar semiconductor layer 43 and variable resistance films 44A and 44B).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 4, 5, 8, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Kanemura in view of Zhou et al. (Pub. No.: US 20200006375 A1), hereinafter as Zhou.
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Image E: close up of Zhou Fig. 12B showing branch parts and structure of the memory channel structure
With regards to claim 4, Kanemura teaches the semiconductor device of claim 1.
Kanemura does not teach that the first memory channel structure includes: a first memory layer in contact with the corresponding one of the plurality of first branch parts; a second memory layer in contact with the corresponding one of the plurality of second branch parts; a first channel layer and a second channel layer between the first memory layer and the second memory layer; and a memory core dielectric layer between the first channel layer and the second channel layer.
Zhou teaches a first memory channel structure (see Zhou Fig. 12B, in-process memory stack structure 155) that includes: a first memory layer (see Zhou Fig. 12B, in-process charge storage layer 154) in contact with the corresponding one of a plurality of first branch parts (see Zhou Fig. 12B and Image E, sacrificial material layers 42); a second memory layer (see Zhou Fig. 12B, in-process charge storage layer 154) in contact with the corresponding one of a plurality of second branch parts (see Zhou Fig. 12B and Image E, sacrificial material layers 42); a first channel layer (see Zhou Fig. 12B, vertical semiconductor channels 60) and a second channel layer (see Zhou Fig. 12B, vertical semiconductor channels 60) between the first memory layer and the second memory layer (see Zhou Fig. 12B); and a memory core dielectric layer (see Zhou Fig. 13D, laterally undulating dielectric rail 62) between the first channel layer and the second channel layer (see Zhou Fig. 13D).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to substitute the memory channel structure of Kanemura with the memory channel structure taught by Zhou in order to provide a wider programming window and wider erase window (see Zhou [0049]: “The flat memory cells of an embodiment of the present disclosure can provided in an inverse configuration, in which the tunneling dielectric is located adjacent to the control gate electrode and the blocking dielectric is located adjacent to the semiconductor channel. The inverse flat memory provides a wider programming window and a wider erase window than prior art flat memory cells.”).
With regards to claim 5, Kanemura and Zhou teach the semiconductor device of claim 4, wherein the first channel layer (see Zhou Fig. 12B, vertical semiconductor channels 60) and the second channel layer (see Zhou Fig. 12B, vertical semiconductor channels 60) are electrically separated from each other (see Zhou Fig. 13D, where there is a laterally undulating dielectric rail 62 separating the two layers. Zhou Fig. 13C is a cross-sectional view showing the electrical separation of the two layers.).
With regards to claim 8, Kanemura and Zhou teach the semiconductor device of claim 4, wherein the first memory layer (see Zhou Fig. 12B, in-process charge storage layer 154) and the second memory layer (see Zhou Fig. 12B, in-process charge storage layer 154) each have a flat sidewall (see Zhou Fig. 12B).
With regards to claim 21, Kanemura teaches the semiconductor device of claim 1, wherein the gate cutting pattern (see Kanemura Fig. 5A and Image A.1, where the space between the first connection part and the second branch act as the gate cutting pattern) is a dielectric structure (it is made of air, which is a dielectric.) extending in a direction (in the z-direction as seen in Kanemura Fig. 18.) crossing a plane (the x-y plane as seen in Kanemura Fig. 18.) including the first conductive pattern (see Kanemura Fig. 5A, conductive layer 42A) and the second conductive pattern (see Kanemura Fig. 5A, conductive layer 42B).
Kanemura does not teach that the gate cutting pattern comprises oxide.
Zhou teaches that a gate cutting pattern (see Zhou Fig. 22B, dielectric pillar structure 76) comprises oxide (see Zhou [0131]: “The insulating material can include silicon oxide, silicon nitride, a dielectric metal oxide, an organosilicate glass, or a combination thereof. In one embodiment, the insulating material can include silicon oxide… Each remaining portion of the insulating material constitutes a dielectric pillar structure 76.”, where one would choose either silicon oxide or a dielectric metal oxide).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the material taught by Zhou for the gate cutting pattern of Kanemura because oxides like silicon oxide are known to be better dielectric material than air.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kanemura and Zhou, in view of Kanamori et al. (Pub. No.: US 20170287928 A1), hereinafter as Kanamori.
With regards to claim 6, Kanemura and Zhou teach the semiconductor device of claim 5.
Kanemura and Zhou do not teach a first selection channel structure on the first channel layer; and a second selection channel structure on the second channel layer.
Kanamori teaches a first selection channel structure (see Kanamori Fig. 3, first string channel pillars SCP1) on a first channel layer (see Kanamori Fig. 3, vertical channel section VC); and a second selection channel structure on a second channel layer (this would have been obvious to a person of ordinary skill in the art because every channel layer has a selection channel structure (see Kanamori Fig. 3, first string channel pillars SCP1 and second string channel pillars SCP2). So, if the vertical pillar VP1 were to be cut in half and each half electrically isolated from each other, there would be a selection channel structure for each half. Thus, showing a second selection channel structure on a second channel layer.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor device of Kanemura and Zhou with the selection channel structure taught by Kanamori in order to further control the connection between the memory channel structure and the bit line.
Claims 11, 12, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kanemura in view of Kim et al. (Pub. No.: US 20180374961 A1), hereinafter as Kim.
With regards to claim 11, Kanemura teaches the semiconductor device of claim 1 further comprising: a plurality of selection lines (see Kanemura Fig. 18, upper select gate line SGU) on the first conductive pattern and the second conductive pattern (see Kanemura Fig. 5A, conductive layer 42A and 42B).
Kanemura does not teach a plurality of selection isolation dielectric layers separating the plurality of selection lines, wherein each of the plurality of selection isolation dielectric layers overlaps the plurality of first branch parts and the plurality of second branch parts.
Kim teaches a plurality of selection lines (see Kim Fig. 16, uppermost gate electrode layers 133, where “The plurality of regions of the uppermost gate electrode layer 133 may be referred to as a plurality of upper selection lines.” Kim [0025]) on a first conductive pattern and a second conductive pattern (see Kim Fig. 16, where the uppermost gate electrode layers 133 is disposed upon the intermediate gate electrode layers 133 (of which make up the first and second conductive patterns)); and a plurality of selection isolation dielectric layers (see Kim Fig. 16 & 22, upper isolation insulating layers 143) separating the plurality of selection lines (see Kim Fig. 16 & 22), wherein each of the plurality of selection isolation dielectric layers overlaps a plurality of first branch parts and a plurality of second branch parts (see Kim Fig. 16 & 22, where the upper isolation insulating layers 143 is disposed upon the intermediate gate electrode layers 133 (of which make up the first and second conductive patterns)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to substitute the selection lines of Kanemura with the selection lines and selection isolation dielectric layers taught by Kim in order to connect to more memory channel structures with the same selection line while also isolating the selection lines from each other.
With regards to claim 12, Kanemura and Kim teach the semiconductor device of claim 11, further comprising: a bit line (see Kanemura Fig. 18, conductive layer 36 (upper global bit line GBLU)) electrically connected to the first memory channel structure (see Kanemura [0091]: “As shown in FIGS. 18 and 19, a conductive layer 36 (upper global bit line GBLU) is connected to an upper end of the columnar semiconductor layer 43 (bit line BL).”), wherein the plurality of first second branch parts and the plurality of second branch parts (see Kanemura Fig. 5A and Images A.2 & A.3, branch parts 42Aa and 42Ba) extend in a first direction (see Kanemura Fig. 5A, where the branches extend in the x-direction), and wherein the bit line extends in a second direction intersecting the first direction (see Kanemura Fig. 18, where the bit line extends in the y-direction), and wherein the plurality of selection isolation dielectric layers (see Kim Fig. 16 & 22, upper isolation insulating layers 143) extend in a third direction that intersects the first direction and the second direction (see Kim Fig. 22, where the upper isolation insulating layers 143 extend at an angle between the x and y directions).
With regards to claim 17, Kanemura teaches the semiconductor device of claim 16 further comprising: a plurality of selection lines (see Kanemura Fig. 18, upper select gate line SGU) on the first conductive pattern and the second conductive pattern (see Kanemura Fig. 5A, conductive layer 42A and 42B).
Kanemura does not teach a plurality of selection isolation dielectric layers between the plurality of selection lines, wherein the plurality of selection isolation dielectric layers overlap the first branch part and the second branch part.
Kim teaches a plurality of selection lines (see Kim Fig. 16, uppermost gate electrode layers 133, where “The plurality of regions of the uppermost gate electrode layer 133 may be referred to as a plurality of upper selection lines.” Kim [0025]) on the first conductive pattern and the second conductive pattern (see Kim Fig. 16, where the uppermost gate electrode layers 133 is disposed upon the intermediate gate electrode layers 133 (of which make up the first and second conductive patterns)); and a plurality of selection isolation dielectric layers (see Kim Fig. 16 & 22, upper isolation insulating layers 143) between the plurality of selection lines (see Kim Fig. 16 & 22), wherein the plurality of selection isolation dielectric layers overlap the first branch part and the second branch part (see Kim Fig. 16 & 22, where the upper isolation insulating layers 143 is disposed upon the intermediate gate electrode layers 133 (of which make up the first and second conductive patterns)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to substitute the selection lines of Kanemura with the selection lines and selection isolation dielectric layers taught by Kim in order to connect to more memory channel structures with the same selection line while also isolating the selection lines from each other.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Kanemura, in view of Hu (Pub. No.: US 20210358890 A1).
With regards to claim 15, Kanemura teaches the semiconductor device of claim 14, wherein the first separation structure and the second separation structure (see Kanemura Fig. 5A & 18 and Image C, where the space next to the connection parts act as the first and second separation structures) extend in a first direction (see Kanemura Fig. 18 and Image C, where the separation structures extend in the z-direction), and the first separation structure and the second separation structure are spaced apart from each other in a second direction (see Kanemura Fig. 5A and Image C, where the separation structures spaced apart in the x-direction), the second direction intersecting the first direction (the x and y directions are orthogonal)
Kanemura does not teach that the plurality of first branch parts and the plurality of second branch parts extend in a third direction intersecting the first direction and the second direction.
Hu teaches a first separation structure and a second separation structure (see Hu Fig. 18, slit structures 1706) that extend in a first direction (see Hu Fig. 18) and are spaced apart from each other in a second direction (see Hu Fig. 18, where they are spaced apart by a direction orthogonal to the angle they extend), where, by modifying the separation structures of Kanemura with the angle taught by Hu, the first and second directions would intersect a third direction (along the x-axis) in which the branch parts of Kanemura extend.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the separation structures of Kanemura with the angle taught by Hu in order to increase the amount of memory channel structures in a given area of a memory cell.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (Pub. No.: US 20230024655 A1), hereinafter as Lee, in view of Kanemura.
With regards to claim 20, Lee teaches an electronic system, comprising: a main board (see Lee Fig. 2, main board 2001); a semiconductor device (see Lee Fig. 2, semiconductor package 2003) on the main board (see Lee Fig. 2); and a controller (see Lee Fig. 2, controller 2002) on the main board (see Lee Fig. 2) and electrically connected to the semiconductor device (see Lee [0046]: “The semiconductor package 2003 and the DRAM 2004 may be connected to the controller 2002 through wiring patterns 2005 formed on the main board 2001.”), wherein the semiconductor device includes, a source structure (see Lee Fig. 7, source structure CST), a gate stack structure (see Lee Fig. 7, stack structure ST) on the source structure (see Lee Fig. 7), a memory channel structure (see Lee Fig. 7, lower vertical structures VS) penetrating the gate stack structure (see Lee Fig. 7), a first separation structure (see Lee Fig. 5&7, separation structure SS; as one can see, there are two, so let the separation structure SS on the right be the first and the separation structure SS on the left be the second.) and a second separation structure (see Lee Fig. 5&7, separation structure SS on the left) spaced apart from each other and in contact with the gate stack structure (see Lee Fig. 5&7), a plurality of selection lines (see Lee Fig. 7, first and second selection gate electrodes SGE1 and SGE2) on the gate stack structure (see Lee Fig. 7), a plurality of selection isolation dielectric layers (see Lee Fig. 7, upper isolation structure SIP, UIL below SIP; in which there would be a plurality of if more than two selection lines are desired, in order to electrically separate said lines from each other) separating the plurality of selection lines (see Lee Fig. 6&7), a selection channel structure (see Lee Fig. 7, upper vertical structures UVS, UVP) electrically connected to the memory channel structure (see Lee Fig. 7), and a bit line (see Lee Fig. 7, bit lines BIL) electrically connected to the selection channel structure (see Lee Fig. 7 and Lee [0093]: “The upper vertical structures UVS may be electrically connected to the bit lines BIL through lower and upper contact plugs BCTa and BCTb.”), wherein the gate stack structure includes, a plurality of first conductive patterns (see Lee Fig. 7, gate electrodes GE) and a plurality of first dielectric patterns (see Lee Fig. 7, dielectric layers ILD) alternately stacked on each other (see Lee Fig. 7).
Lee does not teach a gate cutting pattern, and a channel cutting pattern in contact with the memory channel structure and penetrating the gate stack structure, and a plurality of second conductive patterns and a plurality of second dielectric patterns alternately stacked on each other, and that each of the plurality of first conductive patterns includes, a first connection part in contact with the first separation structure, and a first branch part in contact with the memory channel structure and the channel cutting pattern, wherein each of the plurality of second conductive patterns includes, a second connection part in contact with the second separation structure, and a second branch part in contact with the memory channel structure and the channel cutting pattern, wherein the first branch part and the second branch part are spaced apart from each other, and wherein the plurality of selection isolation dielectric layers overlap the first branch part and the second branch part, and wherein the gate cutting pattern separating the first connection part and the second branch part from each other, the gate cutting pattern including a first side and a second side, the first side and the second side being opposite to each other in an extension direction of the first branch part and the second branch part, the first side being in contact with the first connection part and the second side being in contact with the second branch part.
Kanemura teaches a gate cutting pattern (see Kanemura Fig. 5A and above Image A.1, where the space between the first connection part and the second branch act as the gate cutting pattern), and a channel cutting pattern (see Kanemura Fig. 5A and above Image A.1) in contact with a memory channel structure (see Kanemura Fig. 5A, columnar semiconductor layer 43 and variable resistance films 44A and 44B) and penetrating a gate stack structure (see Kanemura Fig. 4, where the gate stack structure comprises of inter-layer insulating layer 41 and conductive layer 42; and see Kanemura Fig. 12 for isometric view), a plurality of first conductive patterns (see Kanemura Fig. 5A, conductive layer 42A) and a plurality of first dielectric patterns (see Kanemura Fig. 4, inter-layer insulating layer 41) alternately stacked on each other (see Kanemura Fig. 4), and a plurality of second conductive patterns (see Kanemura Fig. 5A, conductive layer 42B) and a plurality of second dielectric patterns (see Kanemura Fig. 4, inter-layer insulating layer 41) alternately stacked on each other (see Kanemura Fig. 4), wherein each of the plurality of first conductive patterns includes, a first connection part (see Kanemura Fig. 5A and Image A.2, connecting part 42Ab) in contact with a first separation structure (see Kanemura Fig. 5A & 18 and Image C, where the space next to the connection parts act as the first and second separation structures), and a first branch part (see Kanemura Fig. 5A and Image A.3, branch parts 42Aa) in contact with the memory channel structure and the channel cutting pattern (see Kanemura Fig. 5A), wherein each of the plurality of second conductive patterns includes, a second connection part (see Image A.3) in contact with a second separation structure (see Kanemura Fig. 5A & 18 and Image C), and a second branch part (see Kanemura Fig. 5A and Image A.2, branch parts 42Ba) in contact with the memory channel structure and the channel cutting pattern (see Kanemura Fig. 5A), wherein the first branch part and the second branch part are spaced apart from each other (see Kanemura Fig. 5A), and (if the conductive patterns of Lee are substituted with the conductive patterns taught by Kanemura) wherein the plurality of selection isolation dielectric layers (of Lee) overlap the first branch part and the second branch part (the selection isolation dielectric layer of Lee extends in the same direction as the separation structures of Lee and the branch parts of Kanemura extend in a direction orthogonal to the separation structures of Kanemura. When substituted in, the branching parts would be orthogonal to the separation structure of Lee. Therefore, there would be an intersection of directions where the selection isolation dielectric layer overlaps the branching parts.), and wherein the gate cutting pattern separating the first connection part and the second branch part from each other (see Image A.1 and Image A.2), the gate cutting pattern including a first side (see Image A.2, 2nd side) and a second side (see Image A.2, 1st side), the first side and the second side being opposite to each other (see Image A.2) in an extension direction (in the y-direction) of the first branch part and the second branch part (see Image A.2), the first side being in contact with the first connection part (see Image A.2) and the second side being in contact with the second branch part (see Image A.2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to substitute the conductive pattern of Lee with the conductive patterns taught by Kanemura in order to reduce the number of contacts that would connect to the conductive pattern (see Kanemura [0047]: “Moreover, the conductive layer 42 functions as the word line WL. Forming the conductive layer 42 in a comb tooth shape makes it possible to reduce the number of contacts connected to the word line WL. For example, assuming the number of word lines WL arranged along the Z direction and the Y direction to each be 32, the number of contacts required when the word line WL is not formed in a comb tooth shape is 32×32=1024. However, the number of contacts required when the word line WL is configured in a comb tooth shape is 32. Moreover, by combining the pair of the conductive layers 42A and 42B, two variable resistance films 44A and 44B can be caused to function independently with respect to one columnar semiconductor layer 43 (bit line BL). The number of contacts at this time is 64.”). Note that the channel cutting patterns would occur due to the comb shape of the conductive pattern leaving gaps, which would be the channel cutting patterns, between the memory channel structures.
Response to Arguments
Applicant's arguments filed 8/12/2026 have been fully considered but they are not persuasive. The
Conclusion
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/E.T.B./Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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