CTNF 18/508,889 CTNF 97733 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1-2, 5-8, 12-17, and 20 is/are rejected under 35 U.S.C. 102 (a)(1) and 102(a)(2) as being anticipated by Picalausa et al. (US 20150212151 A1) . Regarding claim 1, Picalausa teaches An apparatus (Fig. 2, system 200) to implement safety diagnostics ([0002] “It is desirable to test digital systems periodically, because--as with all other manmade devices--they have been known to fail, both with permanent problems and with sensitivities to operating conditions such as high temperatures, radiation, and weak batteries.”) , the apparatus comprising: interface circuitry ([0005] “Typically, a data input 112 is provided to the scan chain from a test mode interface circuit 120, and a data output 114 is provided from the scan chain to the test interface circuit 120.”) coupled to a plurality of circuit modules (Fig. 2, on-chip test control 220 with units 202 and 204) ; and diagnostic circuitry (test control 220) configured to: determine a set of signal chains that may be used by programmable circuitry ([0024] lines 12-14, “Control logic 314 selects 406 a scan chain of the unit by incrementing chain counter 308, and clears seed counter 310”; [0032] “In embodiments, the unit-level, idle-time, self test circuitry herein described is implemented on an integrated circuit configured such that one, two, or more units 202, 204, and test control, vector generator, signature generator and signature verifier are on the same integrated circuit. In some of these embodiments, the same integrated circuit may also incorporate processor 226.”) , wherein a first signal chain in the set of signal chains (scan chains 212, 214) includes one or more circuit modules of the plurality of circuit modules (Fig. 2, respective units 202, 204) ; identify the first signal chain was used by the programmable circuitry ([0023] lines 1-4, “In operation, the system remainder 224 determines 402 (FIG. 5) when a particular functional unit of units 202, 204, is idle, and when that occurs sets the associated unit-idle flag 352, 354 in unit idle register 322”) ; and run a diagnostic test on the first signal chain via the interface circuitry in response to a determination that the one or more circuit modules in the first signal chain are idle ([0024] lines 1-9, “Control logic 314 is configured to begin testing when the test enable bit 350 is set and at least one unit-idle flag 352, 354 is set; when this occurs the control unit is configured to select a unit from units 352, 354 for testing, in an embodiment selection is by incrementing unit counter 306 until a unit associated with a current unit count is found idle, the control logic then sets 404 the associated unit-under-test flag 356, 358 to warn the system remainder 224 that the unit is not now available, and clears chain counter 308.”; lines 16-25, “Control logic 314 is configured to place the associated scan chain of the selected unit into scan mode 410, whereupon a current state of the flip-flops of the scan chain are shifted into and saved in the state memory 328 of the state memorizer. Simultaneously a first test vector is generated by vector generator 316 and shifted into the selected scan chain. The selected unit is then clocked 412 to capture an output of the associated logic units 206, 208, 210 in the scan chain, the output of the logic units is dependent on the vector.”) . Regarding claim 2, Picalausa teaches The apparatus of claim 1, wherein to run the diagnostic test, the diagnostic circuitry is configured to: provide an input to a first circuit module in the first signal chain ([0007] lines 1-8, “Typically, scan testing is performed during a production test environment, where the system being tested performs no normal operations, and external tester 122 provides a sequence of "test vectors" to exercise logic block 102, the vectors typically include stimuli associated with inputs 124 as well as data for initializing each scanable flip-flop 106 of the scan chain to a desired state. The tester loads each vector into the scan chain and onto inputs 124”; ) ; obtain an output from a last circuit module in the first signal chain ([0024] lines 20-25, “a first test vector is generated by vector generator 316 and shifted into the selected scan chain. The selected unit is then clocked 412 to capture an output of the associated logic units 206, 208, 210 in the scan chain, the output of the logic units is dependent on the vector.”) ; and compare the output to an expected value ([0025] lines 12-16, “Once the data has been shifted into the signature generator and a signature dependent on the data generated, the signature is verified 420 by comparison in comparator 318 to an output of signature memory 304, and a fail signal generated if there is a mismatch.”; [0019] lines 1-4, “An output of the signature memory 304 is coupled to a signature comparator 318 that is configured to compare an expected signature read from the signature memory 304 to a signature generated by a signature generator 320”) . Regarding claim 5, Picalausa teaches The apparatus of claim 1, wherein: the first signal chain includes a first circuit module (units 202, 204) ; and the diagnostic circuitry is configured to: receive, while running the diagnostic test, a request from the programmable circuitry to access the first circuit module (Fig. 5, set scan mode 410) ; and provide access to the first circuit module to the programmable circuitry after the diagnostic test is completed (set normal mode 422) . Regarding claim 6, Picalausa teaches The apparatus of claim 5, wherein the diagnostic circuitry is configured to: determine, based on a policy register in memory, the programmable circuitry will wait to access the first circuit module until the diagnostic test is completed ([0025] lines 1-8, “Control logic 314 determines 416 if the current seed is the last seed of one or more seeds in seed memory 302 for testing the selected chain of the selected unit, and, if the last seed OR a unit request flag has been set by the system remainder 224, data from memory 328 of the state memorizer is selected by multiplexor 334 as a bit stream to the scan chain and copied to the scan chain 418.”) ; and provide access to the first circuit module based on the determination (Fig. 5, verify 420, set normal mode 422) . Regarding claim 7, Picalausa teaches The apparatus of claim 1, wherein: the first signal chain includes a first circuit module (units 202, 204) ; and the diagnostic circuitry is configured to: receive, while running the diagnostic test, a request from the programmable circuitry to access the first circuit module (Fig. 5 reserve unit for testing 404) ; and provide access to the first circuit module to the programmable circuitry before the diagnostic test is completed ([0024] lines 6-19, “the control logic then sets 404 the associated unit-under-test flag 356, 358 to warn the system remainder 224 that the unit is not now available, and clears chain counter 308. Unit-under-test flag 356, 358 is configured to disable operation of the functional unit when set, such that input pins are ignored and outputs of the functional unit remain stable. Control logic 314 selects 406 a scan chain of the unit by incrementing chain counter 308, and clears seed counter 310. A seed selected according to seed counter 310, chain counter 308, and unit counter 306 is read from seed memory 302 to load 408 the vector generator 316 with an initial value. Control logic 314 is configured to place the associated scan chain of the selected unit into scan mode 410”) . Regarding claim 8, Picalausa teaches An apparatus (Fig. 2, system 200) to implement safety diagnostics, the apparatus ([0002] “It is desirable to test digital systems periodically, because--as with all other manmade devices--they have been known to fail, both with permanent problems and with sensitivities to operating conditions such as high temperatures, radiation, and weak batteries.”) comprising: programmable circuitry ([0024] lines 12-14, “Control logic 314 selects 406 a scan chain of the unit by incrementing chain counter 308, and clears seed counter 310”; [0032] “In embodiments, the unit-level, idle-time, self test circuitry herein described is implemented on an integrated circuit configured such that one, two, or more units 202, 204, and test control, vector generator, signature generator and signature verifier are on the same integrated circuit. In some of these embodiments, the same integrated circuit may also incorporate processor 226.”) ; a plurality of circuit modules (two or more units 202, 204) ; and diagnostic circuitry (test control 220) configured to: determine a set of signal chains that may be used by the programmable circuitry ([0024] lines 12-14, “Control logic 314 selects 406 a scan chain of the unit by incrementing chain counter 308, and clears seed counter 310”) , wherein a first signal chain in the set of signal chains (scan chains 212, 214) includes one or more circuit modules of the plurality of circuit modules (Fig. 2, respective units 202, 204) ; identify the first signal chain was used by the programmable circuitry ([0023] lines 1-4, “In operation, the system remainder 224 determines 402 (FIG. 5) when a particular functional unit of units 202, 204, is idle, and when that occurs sets the associated unit-idle flag 352, 354 in unit idle register 322”) ; run a diagnostic test on the first signal chain in response to a determination that the one or more circuit modules in the first signal chain are idle ([0024] lines 1-9, “Control logic 314 is configured to begin testing when the test enable bit 350 is set and at least one unit-idle flag 352, 354 is set; when this occurs the control unit is configured to select a unit from units 352, 354 for testing, in an embodiment selection is by incrementing unit counter 306 until a unit associated with a current unit count is found idle, the control logic then sets 404 the associated unit-under-test flag 356, 358 to warn the system remainder 224 that the unit is not now available, and clears chain counter 308.”; lines 16-25, “Control logic 314 is configured to place the associated scan chain of the selected unit into scan mode 410, whereupon a current state of the flip-flops of the scan chain are shifted into and saved in the state memory 328 of the state memorizer. Simultaneously a first test vector is generated by vector generator 316 and shifted into the selected scan chain. The selected unit is then clocked 412 to capture an output of the associated logic units 206, 208, 210 in the scan chain, the output of the logic units is dependent on the vector.”) ; and provide a result of the diagnostic test to the programmable circuitry (Fig. 3, fail signal; [0033] lines 14-19, “In these embodiments, processor 226, after determining that a unit is idle and should be tested, determines a suitable seed, configures the LSFR to generate a vector according to the seed, and, after a test is run, compares the generated signature with an expected signature to determine whether a failure has occurred.”) . Regarding claim 12, Picalausa teaches The apparatus of claim 8, wherein the plurality of circuit modules include an Intellectual Property (IP) core (logic 206, 208, 210) that executes machine-readable instructions ([0033] lines , “In these embodiments, storage of prior seed counter 340, seed counter 310, unit counter 306, and chain counter 308 may be implemented in random access memory of memory 228. In these embodiments, processor 226, after determining that a unit is idle and should be tested, determines a suitable seed, configures the LSFR to generate a vector according to the seed, and, after a test is run, compares the generated signature with an expected signature to determine whether a failure has occurred.”) . The logic units, which process and output from machine-readable instructions, execute machine-readable instructions. Regarding claim 13, Picalausa teaches The apparatus of claim 8, wherein: the first signal chain includes a first circuit module (units 202, 204) ; and the diagnostic circuitry configured to: receive, while running the diagnostic test, a request from the programmable circuitry to access the first circuit module (Fig. 5, set scan mode 410) ; and provide access to the first circuit module to the programmable circuitry after the diagnostic test is completed (set normal mode 422) . Regarding claim 14, Picalausa teaches The apparatus of claim 13, wherein the diagnostic circuitry is configured to: determine, based on a policy register in memory, the programmable circuitry will wait to access the first circuit module until the diagnostic test is completed ([0025] lines 1-8, “Control logic 314 determines 416 if the current seed is the last seed of one or more seeds in seed memory 302 for testing the selected chain of the selected unit, and, if the last seed OR a unit request flag has been set by the system remainder 224, data from memory 328 of the state memorizer is selected by multiplexor 334 as a bit stream to the scan chain and copied to the scan chain 418.”) ; and provide access to the first circuit module based on the determination (Fig. 5, verify 420, set normal mode 422) . Regarding claim 15, Picalausa teaches The apparatus of claim 8, wherein: the first signal chain includes a first circuit module (units 202, 204) ; and the diagnostic circuitry configured to: receive, while running the diagnostic test, a request from the programmable circuitry to access the first circuit module (Fig. 5 reserve unit for testing 404) ; and provide access to the first circuit module to the programmable circuitry before the diagnostic test is completed ([0024] lines 6-19, “the control logic then sets 404 the associated unit-under-test flag 356, 358 to warn the system remainder 224 that the unit is not now available, and clears chain counter 308. Unit-under-test flag 356, 358 is configured to disable operation of the functional unit when set, such that input pins are ignored and outputs of the functional unit remain stable. Control logic 314 selects 406 a scan chain of the unit by incrementing chain counter 308, and clears seed counter 310. A seed selected according to seed counter 310, chain counter 308, and unit counter 306 is read from seed memory 302 to load 408 the vector generator 316 with an initial value. Control logic 314 is configured to place the associated scan chain of the selected unit into scan mode 410”) . Regarding claim 16, Picalausa teaches The apparatus of claim 8, wherein the diagnostic circuitry is configured to run the diagnostic test on the first signal chain while other circuit modules in the apparatus implement instructions from the programmable circuitry ([0023] lines 10-13, “It should be noted that idle condition of a particular functional unit may be detected and set in the unit-idle flags despite a non-idle state of the system as a whole.”; [0025] lines 16-18, “The control logic 314 then clears 422 the unit under test flag and re-enables normal operation of the unit”) . Regarding claim 17, Picalausa teaches A method (Abstract) to implement safety diagnostics ([0002] “It is desirable to test digital systems periodically, because--as with all other manmade devices--they have been known to fail, both with permanent problems and with sensitivities to operating conditions such as high temperatures, radiation, and weak batteries.”) , the method comprising: determining, with diagnostic circuitry, a set of signal chains that may be used by programmable circuitry ([0024] lines 12-14, “Control logic 314 selects 406 a scan chain of the unit by incrementing chain counter 308, and clears seed counter 310”) , wherein a first signal chain in the set of signal chains (scan chains 212, 214) includes one or more circuit modules (Fig. 2, respective units 202, 204) ; identifying, with the diagnostic circuitry, the first signal chain was used by the programmable circuitry ([0023] lines 1-4, “In operation, the system remainder 224 determines 402 (FIG. 5) when a particular functional unit of units 202, 204, is idle, and when that occurs sets the associated unit-idle flag 352, 354 in unit idle register 322”) ; and running a diagnostic test on the first signal chain with the diagnostic circuitry and in response to a determination that the one or more circuit modules in the first signal chain are idle ([0024] lines 1-9, “Control logic 314 is configured to begin testing when the test enable bit 350 is set and at least one unit-idle flag 352, 354 is set; when this occurs the control unit is configured to select a unit from units 352, 354 for testing, in an embodiment selection is by incrementing unit counter 306 until a unit associated with a current unit count is found idle, the control logic then sets 404 the associated unit-under-test flag 356, 358 to warn the system remainder 224 that the unit is not now available, and clears chain counter 308.”; lines 16-25, “Control logic 314 is configured to place the associated scan chain of the selected unit into scan mode 410, whereupon a current state of the flip-flops of the scan chain are shifted into and saved in the state memory 328 of the state memorizer. Simultaneously a first test vector is generated by vector generator 316 and shifted into the selected scan chain. The selected unit is then clocked 412 to capture an output of the associated logic units 206, 208, 210 in the scan chain, the output of the logic units is dependent on the vector.”) . Regarding claim 20, Picalausa teaches The method of claim 17, wherein: the first signal chain includes a first circuit module (units 202, 204) ; and the method further includes: receiving, while running the diagnostic test, a request from the programmable circuitry to access the first circuit module (Fig. 5, set scan mode 410) ; determining, based on a policy register in memory, the programmable circuitry will wait to access the first circuit module until the diagnostic test is completed ([0025] lines 1-8, “Control logic 314 determines 416 if the current seed is the last seed of one or more seeds in seed memory 302 for testing the selected chain of the selected unit, and, if the last seed OR a unit request flag has been set by the system remainder 224, data from memory 328 of the state memorizer is selected by multiplexor 334 as a bit stream to the scan chain and copied to the scan chain 418.”) ; and providing, based on the determination, control of the first circuit module to the programmable circuitry after the diagnostic test is completed (Fig. 5, verify 420, set normal mode 422) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 4, 10, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Picalausa . Regarding claim 4, Picalausa teaches The apparatus of claim 1, wherein: The circuit modules are first circuit modules (units 202; [0016] lines 1-2, “A system 200 (FIG. 2) has one, two, or more units or subsystems 202, 204”; [0001] Most modern digital systems spend much operating time with some or all major parts of the system idle, or nearly idle. Even fast typists rarely can provide input exceeding one character every 100 milliseconds. Although a cell phone or tablet must maintain a digital-radio listening watch while in "standby", such phones spend most of their lives with display blanked, audio processing circuitry disabled, and camera shut down to conserve battery power. Older "CRT"-based televisions and monitors had vertical and horizontal retrace intervals, during which no video is displayed.) ; and the diagnostic circuitry is configured to: access a list of signal chains ([0024] lines 12-14, “Control logic 314 selects 406 a scan chain of the unit by incrementing chain counter 308”) , the list including signal chains that describe second circuit modules ([0016] lines 1-2, “A system 200 (FIG. 2) has one, two, or more units or subsystems 202, 204”; unnamed “more units” of Fig. 2) separate from the apparatus; and determine the set of signal chains that may be used by the programmable circuitry by identifying signal chains within the list ([0024] lines 1-9, “Control logic 314 is configured to begin testing when the test enable bit 350 is set and at least one unit-idle flag 352, 354 is set; when this occurs the control unit is configured to select a unit from units 352, 354 for testing, in an embodiment selection is by incrementing unit counter 306 until a unit associated with a current unit count is found idle, the control logic then sets 404 the associated unit-under-test flag 356, 358 to warn the system remainder 224 that the unit is not now available”; lines 14-26, “A seed selected according to seed counter 310, chain counter 308, and unit counter 306 is read from seed memory 302 to load 408 the vector generator 316 with an initial value. Control logic 314 is configured to place the associated scan chain of the selected unit into scan mode 410, whereupon a current state of the flip-flops of the scan chain are shifted into and saved in the state memory 328 of the state memorizer. Simultaneously a first test vector is generated by vector generator 316 and shifted into the selected scan chain. The selected unit is then clocked 412 to capture an output of the associated logic units 206, 208, 210 in the scan chain, the output of the logic units is dependent on the vector.”) that exclude the second circuit modules ([0025] lines 16-21, “The control logic 314 then clears 422 the unit under test flag and re-enables normal operation of the unit; the control unit then looks to repeat the process of FIG. 5 for the next scan chain of the same unit if one exists and no unit-request flag is set, or the first chain of the next unit marked idle, or if no unit is marked idle it stops until a unit is marked idle and test is enabled.”) . The selection of the unit and scan chain includes not selecting modules not marked idle, and therefore excludes second circuit modules. Even if Picalausa does not explicitly teach the second circuit modules are separate from the apparatus, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make second circuit modules separate from the apparatus, since it has been held that constructing a formerly integral structure in various elements involves only routine skill in the art. Nerwin v. Erlichman, 168 USPQ 177, 179. Regarding claim 10, Picalausa teaches The apparatus of claim 8, wherein: the plurality of circuit modules are a first plurality of circuit modules (units 202; [0016] lines 1-2, “A system 200 (FIG. 2) has one, two, or more units or subsystems 202, 204”; [0001] Most modern digital systems spend much operating time with some or all major parts of the system idle, or nearly idle. Even fast typists rarely can provide input exceeding one character every 100 milliseconds. Although a cell phone or tablet must maintain a digital-radio listening watch while in "standby", such phones spend most of their lives with display blanked, audio processing circuitry disabled, and camera shut down to conserve battery power. Older "CRT"-based televisions and monitors had vertical and horizontal retrace intervals, during which no video is displayed.) ; the apparatus further includes memory ([0033] lines 4-9, “some or all functions of incrementing prior seed counter 340, seed counter 310, unit counter 306, and chain counter 308, along with seed memory 302, signature memory 304, and signature comparator 318 are implemented in machine-readable instructions of firmware resident in memory 228 of processor 226”) to store a list of signal chains ([0024] lines 12-14, “Control logic 314 selects 406 a scan chain of the unit by incrementing chain counter 308”) , the list including signal chains that describe a second plurality of circuit modules separate from the apparatus ([0016] lines 1-2, “A system 200 (FIG. 2) has one, two, or more units or subsystems 202, 204”; unnamed “more units” of Fig. 2) ; and to determine the set of signal chains that may be used by the programmable circuitry, the diagnostic circuitry is configured to identify signal chains within the list ([0024] lines 1-9, “Control logic 314 is configured to begin testing when the test enable bit 350 is set and at least one unit-idle flag 352, 354 is set; when this occurs the control unit is configured to select a unit from units 352, 354 for testing, in an embodiment selection is by incrementing unit counter 306 until a unit associated with a current unit count is found idle, the control logic then sets 404 the associated unit-under-test flag 356, 358 to warn the system remainder 224 that the unit is not now available”; lines 14-26, “A seed selected according to seed counter 310, chain counter 308, and unit counter 306 is read from seed memory 302 to load 408 the vector generator 316 with an initial value. Control logic 314 is configured to place the associated scan chain of the selected unit into scan mode 410, whereupon a current state of the flip-flops of the scan chain are shifted into and saved in the state memory 328 of the state memorizer. Simultaneously a first test vector is generated by vector generator 316 and shifted into the selected scan chain. The selected unit is then clocked 412 to capture an output of the associated logic units 206, 208, 210 in the scan chain, the output of the logic units is dependent on the vector.”) that exclude the second plurality of circuit modules ([0025] lines 16-21, “The control logic 314 then clears 422 the unit under test flag and re-enables normal operation of the unit; the control unit then looks to repeat the process of FIG. 5 for the next scan chain of the same unit if one exists and no unit-request flag is set, or the first chain of the next unit marked idle, or if no unit is marked idle it stops until a unit is marked idle and test is enabled.”) . The selection of the unit and scan chain includes not selecting modules not marked idle, and therefore excludes second circuit modules. Even if Picalausa does not explicitly teach the second circuit modules are separate from the apparatus, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make second circuit modules separate from the apparatus, since it has been held that constructing a formerly integral structure in various elements involves only routine skill in the art. Nerwin v. Erlichman, 168 USPQ 177, 179. Regarding claim 19, Picalausa teaches The method of claim 17, wherein: the circuit modules are first circuit modules (units 202; [0016] lines 1-2, “A system 200 (FIG. 2) has one, two, or more units or subsystems 202, 204”; [0001] Most modern digital systems spend much operating time with some or all major parts of the system idle, or nearly idle. Even fast typists rarely can provide input exceeding one character every 100 milliseconds. Although a cell phone or tablet must maintain a digital-radio listening watch while in "standby", such phones spend most of their lives with display blanked, audio processing circuitry disabled, and camera shut down to conserve battery power. Older "CRT"-based televisions and monitors had vertical and horizontal retrace intervals, during which no video is displayed.) ; and the method further includes: accessing a list of signal chains ([0024] lines 12-14, “Control logic 314 selects 406 a scan chain of the unit by incrementing chain counter 308”) , the list including signal chains that describe second circuit modules ([0016] lines 1-2, “A system 200 (FIG. 2) has one, two, or more units or subsystems 202, 204”; unnamed “more units” of Fig. 2) separate from the diagnostic circuitry; and determining the set of signal chains that may be used by the programmable circuitry by identifying signal chains within the list ([0024] lines 1-9, “Control logic 314 is configured to begin testing when the test enable bit 350 is set and at least one unit-idle flag 352, 354 is set; when this occurs the control unit is configured to select a unit from units 352, 354 for testing, in an embodiment selection is by incrementing unit counter 306 until a unit associated with a current unit count is found idle, the control logic then sets 404 the associated unit-under-test flag 356, 358 to warn the system remainder 224 that the unit is not now available”; lines 14-26, “A seed selected according to seed counter 310, chain counter 308, and unit counter 306 is read from seed memory 302 to load 408 the vector generator 316 with an initial value. Control logic 314 is configured to place the associated scan chain of the selected unit into scan mode 410, whereupon a current state of the flip-flops of the scan chain are shifted into and saved in the state memory 328 of the state memorizer. Simultaneously a first test vector is generated by vector generator 316 and shifted into the selected scan chain. The selected unit is then clocked 412 to capture an output of the associated logic units 206, 208, 210 in the scan chain, the output of the logic units is dependent on the vector.”) that exclude the second circuit modules ([0025] lines 16-21, “The control logic 314 then clears 422 the unit under test flag and re-enables normal operation of the unit; the control unit then looks to repeat the process of FIG. 5 for the next scan chain of the same unit if one exists and no unit-request flag is set, or the first chain of the next unit marked idle, or if no unit is marked idle it stops until a unit is marked idle and test is enabled.”) . The selection of the unit and scan chain includes not selecting modules not marked idle, and therefore excludes second circuit modules. Even if Picalausa does not explicitly teach the second circuit modules are separate from the apparatus, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make second circuit modules separate from the apparatus, since it has been held that constructing a formerly integral structure in various elements involves only routine skill in the art. Nerwin v. Erlichman, 168 USPQ 177, 179 . 07-22-aia AIA Claim (s) 3, 9, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Picalausa as applied to claim s 1, 8, and 17, respectfully , above, and further in view of Evans (US 20030009714 A1) . Regarding claim 3, Picalausa teaches The apparatus of claim 1, wherein the diagnostic circuitry is configured to identify the first signal chain ([0025] lines 16-22, “The control logic 314 then clears 422 the unit under test flag and re-enables normal operation of the unit; the control unit then looks to repeat the process of FIG. 5 for the next scan chain of the same unit if one exists and no unit-request flag is set, or the first chain of the next unit marked idle, or if no unit is marked idle it stops until a unit is marked idle and test is enabled.”). The control unit looking for the first chain of the next unit, iteratively, is identifying the first signal chain. Picalausa does not teach the apparatus, wherein the signal chain is identified in response to receiving a pulse in a trigger signal. Evans teaches an analogous testing apparatus, wherein the signal chain is identified in response to receiving a pulse in a trigger signal ([0049] When use_tck is high, the clock switch 10 couples the test clock 14 to the circuit 12 to be tested, as with conventional shift cycles. However, when the input pulse_gate is set high, a pre-programmed number of pulses from the PLL clock 16 is coupled through to the circuit under test in place of the test clock; [0116] lines 1-8, “Operation of the transition fault test mode is as described above with reference to the timing diagram of FIG. 6. In general the tcb_cc_use_tck signal will be high while the tst_scan_en signal (scan_en in FIG. 6) is asserted, causing TCK to be used for shifting scan chains. However, for the capture cycles we need to gate through a variable number of pulses from the PLL. This pulse stream is timed from the signal tcb_cc_pll_gate (pulse_gate in FIG. 6).”) . It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus of Picalausa to include the pulse in a trigger signal of Evans because it would yield predictable results, such as indicating a signal chain. Regarding claim 9, Picalausa teaches The apparatus of claim 8, wherein the diagnostic circuitry is configured to identify the first signal chain ([0025] lines 16-22, “The control logic 314 then clears 422 the unit under test flag and re-enables normal operation of the unit; the control unit then looks to repeat the process of FIG. 5 for the next scan chain of the same unit if one exists and no unit-request flag is set, or the first chain of the next unit marked idle, or if no unit is marked idle it stops until a unit is marked idle and test is enabled.”). The control unit looking for the first chain of the next unit, iteratively, is identifying the first signal chain. Picalausa does not teach the apparatus, wherein the signal chain is identified in response to receiving a pulse in a trigger signal. Evans teaches an analogous testing apparatus, wherein the signal chain is identified in response to receiving a pulse in a trigger signal ([0049] When use_tck is high, the clock switch 10 couples the test clock 14 to the circuit 12 to be tested, as with conventional shift cycles. However, when the input pulse_gate is set high, a pre-programmed number of pulses from the PLL clock 16 is coupled through to the circuit under test in place of the test clock; [0116] lines 1-8, “Operation of the transition fault test mode is as described above with reference to the timing diagram of FIG. 6. In general the tcb_cc_use_tck signal will be high while the tst_scan_en signal (scan_en in FIG. 6) is asserted, causing TCK to be used for shifting scan chains. However, for the capture cycles we need to gate through a variable number of pulses from the PLL. This pulse stream is timed from the signal tcb_cc_pll_gate (pulse_gate in FIG. 6).”) . It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus of Picalausa to include the pulse in a trigger signal of Evans because it would yield predictable results, such as indicating a signal chain. Regarding claim 18, Picalausa teaches The method of claim 17, further including identifying the first signal chain ([0025] lines 16-22, “The control logic 314 then clears 422 the unit under test flag and re-enables normal operation of the unit; the control unit then looks to repeat the process of FIG. 5 for the next scan chain of the same unit if one exists and no unit-request flag is set, or the first chain of the next unit marked idle, or if no unit is marked idle it stops until a unit is marked idle and test is enabled.”). The control unit looking for the first chain of the next unit, iteratively, is identifying the first signal chain. Picalausa does not teach the method, wherein the signal chain is identified in response to receiving a pulse in a trigger signal. Evans teaches an analogous testing method, wherein the signal chain is identified in response to receiving a pulse in a trigger signal ([0049] When use_tck is high, the clock switch 10 couples the test clock 14 to the circuit 12 to be tested, as with conventional shift cycles. However, when the input pulse_gate is set high, a pre-programmed number of pulses from the PLL clock 16 is coupled through to the circuit under test in place of the test clock; [0116] lines 1-8, “Operation of the transition fault test mode is as described above with reference to the timing diagram of FIG. 6. In general the tcb_cc_use_tck signal will be high while the tst_scan_en signal (scan_en in FIG. 6) is asserted, causing TCK to be used for shifting scan chains. However, for the capture cycles we need to gate through a variable number of pulses from the PLL. This pulse stream is timed from the signal tcb_cc_pll_gate (pulse_gate in FIG. 6).”) . It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Picalausa to include the pulse in a trigger signal of Evans because it would yield predictable results, such as indicating a signal chain . 07-22-aia AIA Claim (s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Picalausa as applied to claim 8 above, and further in view of Giles et al. (US 20090193303 A1) . Regarding claim 11, Picalausa teaches The apparatus of claim 8. Picalausa does not teach the apparatus, wherein the plurality of circuit modules include one or more of an analog to digital converter (ADC), a digital to analog converter (DAC), a programmable gain amplifier, and a comparator Giles teaches an analogous apparatus for testing and diagnosis (Abstract), wherein the plurality of circuit modules (Figs. 1 and 2; processor cores 102A-C; [0036] lines 1-3, “scan input data (i.e. test vectors) and commands are input into pipeline stage 200 through the SDIin and CMDin inputs, respectively”) include one or more of an analog to digital converter (ADC), a digital to analog converter (DAC), a programmable gain amplifier, and a comparator (comparator 222) . It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus of Picalausa to include the comparator of the circuit modules of Giles, because the inclusion of a comparator in the circuit module would yield predictable results. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN GEISS whose telephone number is (571)270-1248. The examiner can normally be reached Monday - Friday 7:30 am - 4:30 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Catherine Rastovski can be reached at (571) 270-0349. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /B.B.G./Examiner, Art Unit 2857 /Catherine T. Rastovski/Supervisory Primary Examiner, Art Unit 2857 Application/Control Number: 18/508,889 Page 2 Art Unit: 2857 Application/Control Number: 18/508,889 Page 3 Art Unit: 2857 Application/Control Number: 18/508,889 Page 4 Art Unit: 2857 Application/Control Number: 18/508,889 Page 5 Art Unit: 2857 Application/Control Number: 18/508,889 Page 6 Art Unit: 2857 Application/Control Number: 18/508,889 Page 7 Art Unit: 2857 Application/Control Number: 18/508,889 Page 8 Art Unit: 2857 Application/Control Number: 18/508,889 Page 9 Art Unit: 2857 Application/Control Number: 18/508,889 Page 10 Art Unit: 2857 Application/Control Number: 18/508,889 Page 11 Art Unit: 2857 Application/Control Number: 18/508,889 Page 12 Art Unit: 2857 Application/Control Number: 18/508,889 Page 13 Art Unit: 2857 Application/Control Number: 18/508,889 Page 14 Art Unit: 2857 Application/Control Number: 18/508,889 Page 15 Art Unit: 2857 Application/Control Number: 18/508,889 Page 16 Art Unit: 2857 Application/Control Number: 18/508,889 Page 17 Art Unit: 2857 Application/Control Number: 18/508,889 Page 18 Art Unit: 2857 Application/Control Number: 18/508,889 Page 19 Art Unit: 2857 Application/Control Number: 18/508,889 Page 20 Art Unit: 2857 Application/Control Number: 18/508,889 Page 21 Art Unit: 2857 Application/Control Number: 18/508,889 Page 22 Art Unit: 2857 Application/Control Number: 18/508,889 Page 23 Art Unit: 2857 Application/Control Number: 18/508,889 Page 24 Art Unit: 2857 Application/Control Number: 18/508,889 Page 25 Art Unit: 2857 Application/Control Number: 18/508,889 Page 26 Art Unit: 2857
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