DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 recites the limitation "the gate " in lines 7 and 8. There is insufficient antecedent basis for this limitation in the claim.
Claim 1 recites the limitation "the first sense resistor " in lines 7 and 8. There is insufficient antecedent basis for this limitation in the claim.
Claims 5 and 7 recites the limitation "the current source " in lines 2 and 3 respectively. There is insufficient antecedent basis for this limitation in the claim.
Claims 5 and 7 recites the limitation "the inverting output " in lines 2 and 3 respectively. There is insufficient antecedent basis for this limitation in the claim.
Claims 10 recites the limitation "the power transistor " in line 4. There is insufficient antecedent basis for this limitation in the claim.
Claim Objections
Claim 14 is objected to because of the following informalities: the phrase, “current sent conversion circuit”. Appropriate correction is required.
Claim 16 is objected to because of the following informalities: the phrase, “coupled to the current to the source of the first power transistor.”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 17 are rejected under 35 U.S.C. 103 as being unpatentable over Maetani (US 20190173297) in view of Lam (US 10090675).
Regarding claim 1, Maetani teaches a device for resistor lossless current sensing (figure 1 item 100 battery apparatus) comprising:
a first power transistor, wherein a drain of the first power transistor is conductively coupled to a current input to the device (figure 1 item 21 shows a power transistor, interpreted as discharge control FET21 wherein the drain is coupled to the input of the device item P-);
a first sense transistor, wherein the gate of the sense transistor is conductively coupled with a gate of the first power transistor and a drain of the sense transistor is conductively coupled with the drain of the first power transistor (figure 1 item 23 shows a first sense resistor defined as charge reference FET23 wherein the drain of the sense transistor is coupled to the drain of the power transistor item 21).
Maetani does not explicitly teach a current sense conversion circuit configured to convert a current output from the first sense transistor to an output voltage wherein the current output from the first sense resistor and output voltage are proportional to the current from the current input to the device and wherein the current sense conversion circuit generates the output voltage which is not in a current path through the first power transistor.
Lam teaches a current sense conversion circuit configured to convert a current output from the first sense transistor to an output voltage wherein the current output from the first sense resistor and output voltage are proportional to the current from the current input to the device and wherein the current sense conversion circuit generates the output voltage which is not in a current path through the first power transistor (column 5 lines 45 – column 6 lines 3 wherein a current sense conversion circuit, interpreted as a current switch circuit 257 which includes a current sensor/mirror circuit in which a current is input and a voltage is output. The output voltage is proportional to the current from the current sense conversion circuit).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the protection circuit of the Maetani reference with the current sensing device of the Lam reference so that the amount of inrush current is limited as the device is initially plugged into an AC-DC adapter.
The suggestion/motivation for combination can be found in the Lam reference in column 5 lines 32 - 40 wherein limiting and inrush current is taught.
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Maetani figure 1 shows an FET circuit item 20 with a first power transistor 21 and a sense transistor item 23
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Lam figure 2A shows a current sense conversion circuit item 257 defined as a current switch circuit
Regarding claim 2, Maetani teaches the device of claim 1 further comprising a second power transistor (figure 1 item 22 defined in paragraph [0018] as a charge control FET22) and a second sense transistor (figure 1 item 24 defined in paragraph [0024] as a discharge reference FET 24) wherein the gate of the second sense transistor is conductively coupled to the gate of the second power transistor and wherein the first power transistor is configured to block current from discharging to the current input to the device when in the off state and the second power transistor is configured to block power from charging from the current input to the device when in the off state (Figure 1 shows wherein the gate of the second sense transistor FET24 is conductively connected to the gate of the second power transistor item FET22 and is configured to block the current from discharging to the current input device. Paragraph [0008] discloses wherein the first power transistor, defined as a discharge control FET item FET21 controls the discharging current according to the discharging-overcurrent reference voltage. Likewise, paragraphs [0008]-[0009] discloses wherein the first power transistor, defined as a charge control FET item FET222 controls the charging current according to the charging-overcurrent reference voltage )
Regarding claim 3, Maetani teaches the device of claim 2, but does not explicitly teach wherein the current sense conversion circuit is further configured to convert a current output from the second sense transistor to the output voltage for the charging current information.
Lam teaches the current sense conversion circuit is further configured to convert a current output from the second sense transistor to the output voltage for the charging current information (column 5 lines 45 – column 6 lines 3 wherein a current sense conversion circuit, interpreted as a current switch circuit 257 which includes a current sensor/mirror circuit in which a current is input and a voltage is output).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the protection circuit of the Maetani reference with the current sensing device of the Lam reference so that the amount of inrush current is limited as the device is initially plugged into an AC-DC adapter.
The suggestion/motivation for combination can be found in the Lam reference in column 5 lines 32 - 40 wherein limiting and inrush current is taught.
Regarding claim 4, Maetani teaches the device of claim 3 but does not explicitly teach wherein the current sense conversion circuit includes one or more current mirrors for the current output from the first sense transistor and the second sense transistor.
Lam teaches wherein the current sense conversion circuit includes one or more current mirrors for the current output from the first sense transistor and the second sense transistor (column 5 lines 55 – 60 discloses wherein the current switch circuit includes a currents sensor/mirror circuit).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the protection circuit of the Maetani reference with the current sensing device of the Lam reference so that the amount of inrush current is limited as the device is initially plugged into an AC-DC adapter.
The suggestion/motivation for combination can be found in the Lam reference in column 5 lines 32 - 40 wherein limiting and inrush current is taught.
Regarding claim 5, Maetani teaches the device of claim 4, but does not explicitly teach wherein the current sense conversion circuit includes a resistor and an amplifier arranged in a transimpedance amplifier configuration wherein the current source is conductively coupled to a non-inverting input of the amplifier and an output of at least one of the one or more current mirrors is conductively coupled to the inverting output of the amplifier.
Lam teaches wherein the current sense conversion circuit includes a resistor and an amplifier arranged in a transimpedance amplifier configuration wherein the current source is conductively coupled to a non-inverting input of the amplifier and an output of at least one of the one or more current mirrors is conductively coupled to the inverting output of the amplifier (figure 3 and 15 show a resistor (figure 15 shows resistors 413 and 414) and an amplifier (figure 15 item 410) arranged in a transimpedance amplifier configuration wherein the current source is conductively coupled to an non-inverting input of the amplifier and an output of at least one or more current mirrors is conductively coupled to the inverting output of the amplifier).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the protection circuit of the Maetani reference with the current sensing device of the Lam reference so that the amount of inrush current is limited as the device is initially plugged into an AC-DC adapter.
The suggestion/motivation for combination can be found in the Lam reference in column 5 lines 32 - 40 wherein limiting and inrush current is taught.
Regarding claim 6, Maetani teaches the device of claim 1 but does not explicitly teach wherein the current sense conversion circuit includes one or more current mirrors for the current output from the first sense transistor.
Lam teaches wherein the current sense conversion circuit includes one or more current mirrors for the current output from the first sense transistor (figure 15 shows the current sense conversion circuit item 400 with one or more current mirrors items 416, 417, and 418).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the protection circuit of the Maetani reference with the current sensing device of the Lam reference so that the amount of inrush current is limited as the device is initially plugged into an AC-DC adapter.
The suggestion/motivation for combination can be found in the Lam reference in column 5 lines 32 - 40 wherein limiting and inrush current is taught.
Regarding claim 7, Maetani teaches the device of claim 6, but does not explicitly teach wherein the current sense conversion circuit includes a feedback resistor and an amplifier arranged in a transimpedance amplifier configuration wherein the current source is conductively coupled to a non-inverting input of the amplifier and an output of at least one of the one or more current mirrors is conductively coupled to the inverting output of the amplifier.
Lam teaches wherein the current sense conversion circuit includes a feedback resistor and an amplifier arranged in a transimpedance amplifier configuration wherein the current source is conductively coupled to a non-inverting input of the amplifier and an output of at least one of the
one or more current mirrors is conductively coupled to the inverting output of the amplifier (figure 15 shows a feedback resistor and an amplifier arranged in a transimpedance amplifier configuration wherein the current source is conductively coupled to a non-inverting input of the amplifier and an output of at least one of the
one or more current mirrors is conductively coupled to the inverting output of the amplifier).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the protection circuit of the Maetani reference with the current sensing device of the Lam reference so that the amount of inrush current is limited as the device is initially plugged into an AC-DC adapter.
The suggestion/motivation for combination can be found in the Lam reference in column 5 lines 32 - 40 wherein limiting and inrush current is taught.
Regarding claim 8, Maetani teaches the device of claim 7, but does not explicitly teach wherein the resistance of the feedback resistor includes a configurable resistance to scale the gain of output voltage amplitude to the current.
Lam teaches wherein the resistance of the feedback resistor includes a configurable resistance to scale the gain of output voltage amplitude to the current (defined in column 10 lines 64 wherein the resistance is configurable is interpreted as the operational amplifier within the current sense circuit, modulates the current such that the voltages output are positive).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the protection circuit of the Maetani reference with the current sensing device of the Lam reference so that the amount of inrush current is limited as the device is initially plugged into an AC-DC adapter.
The suggestion/motivation for combination can be found in the Lam reference in column 5 lines 32 - 40 wherein limiting and inrush current is taught.
Regarding claim 9, Maetani teaches the device of claim 1 further comprising a battery protection integrated circuit wherein the battery protection integrated circuit is configured to receive the output voltage and control the gate of the first power transistor based at least on the output voltage (figure 1 item 11 shows a battery protection circuit defined as a control circuit, which receives the output voltage and control the gate of the first power transistor based on the output voltage).
Regarding claim 10, Maetani teaches the device of claim 9, but does not explicitly teach wherein the current sense conversion circuit is integrated into the battery protection circuit and wherein the battery protection circuit receives the current output from the first sense transistor and a sense input coupled to a source side of the power transistor.
Lam teaches wherein the current sense conversion circuit is integrated into the battery protection circuit and wherein the battery protection circuit receives the current output from the first sense transistor and a sense input coupled to a source side of the power transistor (figure 2A shows wherein the current circuit, item 257 defined as a current switch circuit which includes a current sense circuit item 400, is integrated into the battery protection circuit).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the protection circuit of the Maetani reference with the current sensing device of the Lam reference so that the amount of inrush current is limited as the device is initially plugged into an AC-DC adapter.
The suggestion/motivation for combination can be found in the Lam reference in column 5 lines 32 - 40 wherein limiting and inrush current is taught.
Regarding claim 11, Maetani teaches the device of claim 1 wherein the first sense transistor is integrated into a component package of the first power transistor (shown in figure 1 first sense transistor item FET23 is integrated into a component package of the first power transistor item 21 within an FET circuit 20).
Regarding claim 12, Maetani teaches the device of claim 11, but does not explicitly teach wherein the current sense conversion circuit is integrated into the component package of the first power transistor.
Lam teaches wherein the current sense conversion circuit is integrated into the component package of the first power transistor (figures 3 and 15 shows wherein the current sense conversion circuit is integrated into the component package of the first power transistor).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the protection circuit of the Maetani reference with the current sensing device of the Lam reference so that the amount of inrush current is limited as the device is initially plugged into an AC-DC adapter.
The suggestion/motivation for combination can be found in the Lam reference in column 5 lines 32 - 40 wherein limiting and inrush current is taught.
Regarding claim 13, Maetani teaches the device of claim 12, but does not explicitly teach wherein the current sense conversion circuit is vertically stacked over the first sense transistor and first power transistor.
Lam teaches wherein the current sense conversion circuit is vertically stacked over the first sense transistor and first power transistor (figures 3 and 15 shows wherein the current sense conversion circuit is vertically stacked over the first sense transistor, shown as item 408 and first power transistor shown as item 92).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the protection circuit of the Maetani reference with the current sensing device of the Lam reference so that the amount of inrush current is limited as the device is initially plugged into an AC-DC adapter.
The suggestion/motivation for combination can be found in the Lam reference in column 5 lines 32 - 40 wherein limiting and inrush current is taught.
Regarding claim 14, Maetani teaches the device of claim 13 wherein the component package of the first power transistor includes a lead frame and bond wires connect the current sent conversion circuit to the lead frame (Figure 1 shows the power transistor, field effect transistor, FET 21, which are known in the art to include a lead frame and bond wires).
Regarding claim 15, Maetani teaches the device of claim 11 further comprising a second power transistor and second sense transistor integrated into the component package of the first power transistor (figure 1 items power transistors FET22 and and sense transistor FET24).
Regarding claim 16, Maetani teaches the device of claim 1 further comprising a battery conductively coupled to the current to the source of the first power transistor (figure 1 item 1 a battery).
Regarding claim 17, Maetani teaches the device of claim 1 wherein the first power transistor includes a plurality of transistor components, and the first sense transistor includes less transistors components than the first power transistor (paragraph [0019] discloses wherein,
the ratio between the channel widths of the charge-reference FET23 and the discharge control FET21 is assumed to be set at 1:1000000, thus the sense transistor FET23 is smaller and includes less components that the first power transistor FET 21 which is larger).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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ALEXIS BOATENG PACHECO
Primary Examiner
Art Unit 2859
/ALEXIS B PACHECO/Primary Examiner, Art Unit 2859
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