DETAILED ACTION
This Office action is in response to the communication filed on January 5, 2026. Claims 1-2 and 4-10 remain pending in this application. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) based on application filed in China on May 17, 2023 has been acknowledged and considered by Examiner. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d) that are placed on record in the application file.
Response to Arguments
Applicant’s arguments with respect to amended claim 1 in the Remarks section (pages 6-11) have been fully considered but are not persuasive.
Applicant argues Zhang in view of Byeon does not teach first common voltage line and the second common voltage line are disposed on the buffer layer because Byeon teaches interlayer connections of conductive layers including common lines.
However, Zhang is relied on teach that common voltage lines first common voltage line and the second common voltage line were able to have bene disposed in a same layer as the gate electrode so as to simplify the production process of the display substrate and contribute the thinning design of the display substrate, which when configured as a top gate electrode would be above the buffer layers below in Zhang paragraphs [0080]-[0081]. Similarly, Byeon teaches The common voltage was able to have been overlapped with the driving signal lines, for example, the gate lines and the data lines, but connections could have been between layers. Therefore, meeting claim limitations. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicant's arguments have been fully considered with respect to 2-10 in the Remarks section (page 11) but they are not persuasive as the claims depend upon the features recited in the amended independent claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4 and 6-10 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication 2024/0385484 A1 by Zhang in view of U.S. Patent Publication 2014/0184964 A1 by Byeon, and further in view of U.S. Patent Publication 2023/0360579 by Zhou.
Regarding claim 1, Zhang discloses a display panel, comprising:
a display area and a non-display area located at a periphery of the display area (Fig. 2; [0047], As shown in FIG. 2 , the display substrate has a display area AA and a peripheral area NA surrounding the display area AA);
wherein the display panel further comprises: a substrate (110)(See Figs. 2, 8 and [0047, 0087], At least an embodiment of the present disclosure provides a display substrate);
a functional element, disposed on the substrate and located in the non-display area (see Fig. 4, [0048], The display substrate comprises an integrated circuit IC; the integrated circuit IC is disposed in the peripheral area NA);
a first common voltage input line, disposed on the substrate and located at a side of the functional element facing away from the display area (Figs. 2 and 4; [0048], The display substrate comprises a second common voltage line C2, the second common voltage line C2 is located on a side of the first common voltage line C1 away from the display area AA and also at the binding edge B3 on a side of the IC facing away from the display area AA as shown in Fig. 4)
a second common voltage input line, disposed on the substrate and located at a side of the functional element facing away from the first common voltage input line (Fig. 2; [0048], The display substrate comprises a first common voltage line C1 and at a binding edge B1 facing away from the common voltage line C1 as shown in Fig. 4); and
a plurality of first connecting lines, passing through the functional element and electrically connected between the first common voltage input line and the second common voltage input line ([0054], the first common voltage line C1 comprises a first connection end N1 and a second connection end N2, and the second common voltage line C2 comprises a third connection end N3 and a fourth connection end N4. The first connection end N1 is electrically connected to the third connection end N3, and the second connection end N2 is electrically connected to the fourth connection end N4, so that the first common voltage line C1 is electrically connected to the second common voltage line C2)
wherein the non-display area comprises an upper frame area, a lower frame area, a left frame area and a right frame area (Fig. 2, peripheral area NA includes a top area, lower area, left area, right area framing the display area AA); the upper frame area and the lower frame area are opposite to each other, the left frame area and the right frame area are connected with the upper frame area and the lower frame area, and the left frame area and the right frame area are opposite to each other (see Fig. 2); and the first common voltage input line extends from the left frame area to the upper frame area and from the upper frame area to the right frame area (Fig. 2, second common voltage line C2 extends around left, upper and right areas of peripheral area NA; [0048], the first common voltage line C2 is disposed in the peripheral area NA and at least partially surrounds the display area A), and
wherein the functional element comprises first functional elements (Fig. 7, GOA) and a second functional element elements (Fig. 4, integrated circuits IC 7), the first functional elements are respectively located in the left frame area and the right frame area and are respectively arranged parallel to the left frame and the right frame, and (Fig. 7, GOA, [0078], As shown in FIG. 7 , in some embodiments, the display substrate can further comprise a gate scanning drive circuit GOA disposed on the third side and the fourth side of the display area AA adjacent to the first side, i.e., forming a GOA (Gate on Array) display substrate parallel to the left and right frame), and
the second functional element is located in the upper frame area and arranged parallel to the upper or lower frame ([0059], Integrated circuit IC can comprise a first sub-integrated circuit IC1 and a second sub-integrated circuit IC2 disposed in parallel on the first side of the display area AA, wherein the upper),
the display panel further comprises a buffer layer covering the substate, the first common voltage input line and the second common voltage input line are disposed on the buffer layer ([0080]-[0081], For example, in other embodiments, the thin film transistor TFT can also be top-gate type, the gate electrode 122 is disposed on a side of the active layer 121 away from the base substrate 110. For example, in some embodiments, the first common voltage line C1 and the second common voltage line C2 can be disposed in a same layer as the gate electrode 122 so as to simplify the production process of the display substrate and contribute the thinning design of the display substrate).
Zhang does not teach wherein the plurality of first connecting lines is distributed along the first common voltage input line around the display area.
In the analogous art of display panel peripheral connections, Byeon teaches common voltage applying line to transfer a common voltage VCom to the common electrode. Since an image displayed by each pixel depends on a difference between the data voltage and the common voltage, the magnitudes of common voltages applied to the pixels should be uniform. However, the magnitudes of the common voltages may not be uniform in certain portions of the display panel, due to load variations resulting from wiring transferring the common voltage to the display panel, the resistance of an electrode, parasitic capacitance, or the like (Byeon [0008]). The common voltage line 301 may include horizontal portions that extend in a row direction and vertical portions that extend in a column direction. In this case, the horizontal portions and the vertical portions are connected to each other. The common voltage line 301 may be overlapped with the driving signal lines, for example, the gate lines and the data lines (Byeon [0044]). At least one of the edge common voltage line 302 and the first common voltage transfer line 77 is formed along at least one side of the display area DA and may surround the display area DA (Byeon [0050]). An insulating layer may be interposed between the edge common voltage line 302 and the first common voltage transfer line 77. The edge common voltage line 302 may be electrically and/or physically connected with the first common voltage transfer line 77, through at least one contact hole 187 of the insulating layer or directing connecting with contact holes using connecting lines distributed along the common voltages around the display area (Byeom Fig. 1; [0054]-[0056]).
It would have been obvious before the effective filing date of the invention to have modified the first and second common lines of Zhang to have similarly connected by direct connection to a first common voltage transfer line near the integrated circuit film, and therefore to each other as taught by Zhang where that the first common voltage line C1 is electrically connected to the second common voltage line C2. One having ordinary skill in the art to have been motivated to prevent the magnitudes of the common voltages may not be uniform in certain portions of the display panel, due to load variations resulting from wiring transferring the common voltage to the display panel, and display defects caused as a result. As described above, the edge common voltage line 302 is connected with the common voltage line 301 of the display area DA and receives the common voltage from the first common voltage transfer line 77 formed along the edges of at least three sides of the display area DA. As a result, the magnitudes of the common voltages may be uniform according to position. Further, the edge common voltage line 302 is made of metal having high conductivity and contacts the first common voltage transfer line 77 to receive the common voltage from the input pads of integrated circuit film. As a result, the contact resistance may be lowered and a signal delay of the common voltage may be reduced. Since the contact resistance between the edge common voltage line 302 and the first common voltage transfer line 77 is lowered, widths of the edge common voltage line 302 and the first common voltage transfer line 77 may be decreased (Byeom [0057], [0008], and [0051]).
However, Zhang in view of Byeom did not teach limiting the integrated circuit to be located parallel to the upper frame. Zhang taught in [0004] that the integrated circuit is further configured to provide the display signals to the plurality of sub-pixels by the plurality of third common voltage lines during the display stage, and provide the touch signals to the plurality of touch electrodes by the plurality of third common voltage lines during the touch stage.
In the analogous art of display panel array substrates, Zhou teaches source driving integrated circuit that connected to data lines and was located the on the upper side of the display panel. The source drive circuit was directly integrated or connected with array substrates using a COF way. It was located on the upper side of the display panel where the gate-on-array GOA driver was located on the left and right side of the frame or the same side (Zhou Fig. 1; [0062] and [0047]). It would have been obvious before the effective filing date of the invention to have substituted the first side opposite of a second side for the integrated circuit providing pixel data voltages to the upper side of the frame as taught by Zhou modified by Byeom. One having ordinary skill in the art would have been motivated to have used a configuration for driving a conventional large-sized display panel that was dual driven by two gate drive circuits on the left and right side of the frame as taught by Zhang in view of Byeom (Zhou Fig. 1; [0046]-[0047]).
Regarding claim 2, Zhang of the combination of references further teaches the display panel of claim 1, wherein the second common voltage input line is located in the non-display area, the second common voltage input line surrounds the display area, and the first common voltage input line semi-surrounds the second common voltage input line (Fig. 2; [0048], the first common voltage line C1 is disposed in the peripheral area NA, the second common voltage line C2 is located on a side of the first common voltage line C1 away from the display area AA and at least partially surrounds the display area AA and the first common voltage line C1).
Regarding claim 4, Zhang of the combination of references further teaches the display panel of claim 1, and functions of the first functional elements is different from a function of the second functional element (Fig. 7, GOA, [0078], As shown in FIG. 7 , in some embodiments, the display substrate can further comprise a gate scanning drive circuit GOA disposed on the third side and the fourth side of the display area AA adjacent to the first side, i.e., forming a GOA (Gate on Array) display different than the integrated circuit IC)
Regarding claim 6, Zhang of the combination of references further teaches the display panel of claim 4, wherein the second functional element is a detection circuit ([0042], As shown in FIG. 1 , during the display stage DA, the integrated circuit provides a common voltage signal V1 to the plurality of sub-pixels in the display area by the signal line, and the common voltage signal V1 can be a DC voltage signal; and during the touch stage TU, the integrated circuit provides an impulse voltage signal V2 with high-frequency inversion to the touch structure by the signal line to recognize a change in capacitance caused by the touch of an operation body, e.g., a finger.), a gap is defined between the second functional element and each of the first functional elements, and the second common voltage input line is electrically connected with the first common voltage input line through the gap (Figs. 2-4, [0054], the first common voltage line C1 comprises a first connection end N1 and a second connection end N2, and the second common voltage line C2 comprises a third connection end N3 and a fourth connection end N4. The first connection end N1 is electrically connected to the third connection end N3, and the second connection end N2 is electrically connected to the fourth connection end N4, so that the first common voltage line C1 is electrically connected to the second common voltage line C2 where the part of the connections were located in a gap between GOAs as in Fig. 7 and the IC in Fig. 4).
Regarding claim 7 Zhang of the combination of references further teaches the display panel of claim 3, wherein the display panel further comprises a flexible printed circuit board located in the lower frame area and a plurality of second connecting lines located in the lower frame area (Figs. 3-4, FPC at lower half of frame where first connection lines with ends N1, N2 were also located; [0056], For example, in some embodiments, as shown in FIG. 3 , the display substrate further comprises a circuit board F. For example, the circuit board F comprises at least one of Flexible Printed Circuit (FPC)), the first common voltage input line and the second common voltage input line are electrically connected with the flexible printed circuit board (see Fig. 4), and a part of the second common voltage input line located in the lower frame area is further electrically connected with the flexible printed circuit board through the plurality of second connecting lines (Figs. 3-4, FPC at lower half of frame where first connection lines with ends N1, N2 connected to FPC using bonding edge B3).
Regarding claim 8, Zhang of the combination of references further teaches the display panel according to claim 1, wherein the display area comprises a first display area and a second display area adjacent to each other (Figs. 4-6; [0059], The first sub-integrated circuit IC1 and the second sub-integrated circuit IC2 can be configured to provide drive signals to the sub-pixels SP or the touch electrodes T in different areas so each define a display area adjacent to each other), a plurality of first common voltage lines are disposed in the first display area, and a plurality of second common voltage lines are disposed in the second display area (Figs. 4-6, plurality of second and first common voltage lines are each side where IC1 and IC2 defined display areas), and the plurality of first common voltage lines and the plurality of second common voltage lines are insulated (Figs. 4-6, plurality of second and first common voltage lines are insulated each side where IC1 and IC2 defined display areas and receive different signals for a time such as in [0048]); and wherein the first common voltage input line is disconnected at a junction of the first display area and the second display area, the second common voltage input line is disconnected at the junction of the first display area and the second display area; and a part of the first common voltage input line corresponding to the first display area and a part of the second common voltage input line corresponding to the first display area are electrically connected with the plurality of first common voltage lines ([0075], the first common voltage line C1 and the second common voltage line C2 surround the display area AA at least at the second side (e.g., the upper side of the display substrate), the third side (e.g., the left side of the display substrate), and the fourth side (e.g., the right side of the display substrate) of the display area AA disjointed at first side where IC1 and IC2 defined display areas, and the first common voltage line C1 and the second common voltage line C2 are electrically connected to the integrated circuit IC at the first side of the display area AA such for IC1 connections), and a part of the first common voltage input line corresponding to the second display area and a part of the second common voltage input line corresponding to the second display area are electrically connected with the plurality of second common voltage lines (the first common voltage line C1 and the second common voltage line C2 are electrically connected to the integrated circuit IC at the first side of the display area AA such for IC2 connections as in Figs. 4-6).
Regarding claim 9, Zhang of the combination of references further teaches the display panel of claim 8, wherein the first display area comprises a first sub-display area and a second sub-display area adjacent to each other (Fig. 6, upper side and lower side where IC1 defined the display area), and the plurality of first common voltage lines comprise a plurality of first sub-common voltage lines located in the first sub-display area and a plurality of second sub-common voltage lines located in the second sub-display area (Fig. 6, upper side of common lines C2 and lower side of common lines C2 where IC1 defined display area); and the second display area comprises a third sub-display area and a fourth sub-display area adjacent to each other, the plurality of second common voltage lines comprise a plurality of third sub-common voltage lines located in the third sub-display area and a plurality of fourth sub-common voltage lines located in the fourth sub-display area (Fig. 6, upper side of common lines C1 and lower side of common lines C1 where IC2 defined display area); wherein the part of the first common voltage input line corresponding to the first display area is disconnected at a junction of the first sub-display area and the second sub-display area (Fig. 6, see gap between upper and lower sides of common voltage lines C2 where IC1 defined display area), and the part of the second common voltage input line corresponding to the first display area is disconnected at the junction of the first sub-display area and the second sub-display area (Fig. 6, see gap between upper and lower sides of common voltage lines C1); and a part of the first common voltage input line corresponding to the first sub-display area and a part of the second common voltage input line corresponding to the first sub-display area are electrically connected with the plurality of first sub-common voltage lines (the first common voltage line C1 and the second common voltage line C2 are electrically connected to the integrated circuit IC at the first side of the display area AA such for IC1 connections as in Figs. 4-6), and a part of the first common voltage input line corresponding to the second sub-display area and a part of the second common voltage input line corresponding to the second sub-display area are electrically connected with the plurality of second sub-common voltage lines (the first common voltage line C1 and the second common voltage line C2 are electrically connected to the integrated circuit IC at the first side of the display area AA such for IC1 connections as in Figs. 4-6); and wherein the part of the first common voltage input line corresponding to the second display area is disconnected at a junction of the third sub-display area and the fourth sub-display area (Fig. 6, see gap between upper and lower sides of common voltage lines C2 where IC2 defined display area), and the part of the second common voltage input line corresponding to the second display area is disconnected at the junction of the third sub-display area and the fourth sub-display area (Fig. 6, see gap between upper and lower sides of common voltage lines C2 where IC2 defined display area); and a part of the first common voltage input line corresponding to the third sub-display area and a part of the second common voltage input line corresponding to the third sub-display area are electrically connected with the plurality of third sub-common voltage lines (the first common voltage line C1 and the second common voltage line C2 are electrically connected to the integrated circuit IC at the first side of the display area AA such for IC2 connections as in Figs. 4-6), and a part of the first common voltage input line corresponding to the fourth sub-display area and a part of the second common voltage input line corresponding to the fourth sub-display area are electrically connected with the plurality of fourth sub-common voltage lines (the first common voltage line C1 and the second common voltage line C2 are electrically connected to the integrated circuit IC at the first side of the display area AA such for IC2 connections as in Figs. 4-6).
Regarding claim 10, Zhang of the combination of references further teaches the display panel of claim 9, wherein a voltage on the part of the first common voltage input line corresponding to the first sub-display area is different from a voltage on the part of the first common voltage input line corresponding to the second sub-display area (For example, as shown in FIG. 6 , the plurality of gate leads 125 extend in the low right portion of the display substrate, e.g., to the integrated circuit IC, so that the integrated circuit IC can provide gate scanning signals to the plurality of gate leads 125. At that time, the first common voltage line C1 and the second common voltage line C2 on both sides of the plurality of gate leads 125 have a small distribution width to avoid the arrangement space for the plurality of gate leads 125, changing voltage characteristics at that region of upper and lower frame of display area defined by IC1).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication 2024/0385484 A1 by Zhang in view of U.S. Patent Publication 2014/0184964 A1 by Byeon and U.S. Patent Publication 2023/0360579 by Zhou, and further in view of U.S. Patent Publication 2025/0131895 A1 by Feng et al. (“Feng.”)
Regarding claim 5, Zhang of the combination of references further teaches the display panel of claim 4, wherein each of the first functional elements is a gate on array (GOA) circuit ([0043], For example, in the GOA (Gate on Array) products, a GOA signal and a touch signal can be inversed together at high frequency to reduce the coupling disturbance. However, for the Gate IC+TDDI products in which the gate scanning drive circuit is integrated into the IC, such coupling disturbance is inevitable).
However, Zhang in view of Byeon does not teach the GOA circuit is provided with an avoidance zone at a position corresponding to each of the plurality of first connecting lines.
While Zhang teaches in [0086], At that time, the first common voltage line C1 and the second common voltage line C2 and their associated/electrically connected first and second connecting lines on both sides of the plurality of gate leads 125 have a small distribution width to avoid the arrangement space for the plurality of gate leads 125, Zhang does not teach connecting lines that connect the first and second common voltage lines where the GOA circuit was located.
In the analogous art of common electrode wirings in the bezel of a display region, Feng teaches a gate on array (GOA) technology integrates a transistor on a display substrate to realize progressive drive of a gate line through a gate drive circuit. This saves wiring spaces for a bonding area of a gate integrated circuit (IC) similar to the integrated circuit of Zhang. 0003. Because a common electrode wire is usually arranged between the shift register and the patch panel, it is necessary to arrange a jumper across the common electrode wire to realize the electrical connection between the patch panel and the shift register through the jumper. However, because the common electrode wire and the patch panel share a common gate metal layer, and a distance between the common electrode wire and the patch panel is small due to the need for narrow bezels, electro-static discharge (ESD) is prone to generation between the common electrode wire and the patch panel, which may lead to a broken circuit (GO) in the patch panel. When the jumper (located in a source-drain metal layer) passes through a gap between the common electrode wire and the patch panel, it will be short-circuited to the common electrode wire (Gout and Com short, GCS) due to static electricity, resulting in poor display such as horizontal dark lines and horizontal stripes (Feng Figs. 1-3; [0078]-[0079]). It would have been obvious to have similar jumpers in the common electrode wires of Zhang, where one side of the common electrode wire was located on one side of the shift register and a second common electrode wire on the other side with both having connections to common gate metal layer as taught by Feng. One having ordinary skill in the art would have been motivated to a distance between the common electrode wire and the patch panel is small due to the need for narrow bezels, electro-static discharge (ESD) is prone to generation between the common electrode wire and the patch panel on either side of a shift register (GOA) circuit (Feng Figs. 1-3; [0078]-[0079]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Patent Publication 2021/0083037 by Kim et al. teaches a groove may be placed between first common voltage lines and second outer common voltage lines to prevent excessive current flow. Where the groove was not located served as a connector.
U.S. Patent Publication 2023/0402579 A1by Cheon et al. teaches common voltage wiring in the peripheral area and a division of the wiring into a first and second dummy wirings overlapping the common voltage wiring, but does not bridge the dummy wirings to the common voltage over the GOA array.
Foreign Patent Publication CN 208847999 A by Nong teaches a driving module including circuit board, wherein a circuit board for driving was connected to a control chip disposed on the lower periphery of the frame.
U.S. Patent Publication 2018/0341365 A1 by Mo et al. teaches there is a gate driving unit generating gate driving signals that formed a parasitic capacitance between the gate lines and the common lines of a display device.
U.S. Patent Publication 2021/0126017 A1 teaches active matrix substrate of a display provided with sensor wiring lines that connected to common voltage lines in the source driver located in the frame region.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MAHEEN I JAVED whose telephone number is (571)272-0825. The examiner can normally be reached on Mon-Fri 9:00 am-5:00 pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, AMR AWAD can be reached on 571-272-7764. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MAHEEN I JAVED/Examiner, Art Unit 2621
/AMR A AWAD/Supervisory Patent Examiner, Art Unit 2621
Prosecution Insights