Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment filed 12/23/25 has been entered. Claims 1, 3-11 and 13-20 are pending in the present application.
Applicant’s amendment to the title (“GRAPHICS PROCESSORS WITH A PRIMITIVE CULLING DATA STRUCTURE”) has been accepted.
Response to Arguments
Applicant argued that Sharma does not teach “Sharma does not teach the claimed "two-pass" rendering operation in which primitives are rasterized into sets of fragments in both passes, and in particular, does not teach a first, pre-pass operation in which primitives are rasterized into respective sets of fragments, and in which further processing is then performed for those fragments to determine fragment-level visibility information,” (Remarks, page 15). The argument has been fully considered, but is moot in view of the new ground of rejection, necessitated by the present amendment.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 8-11, 13 and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jeong et al. (Pub. No. US 2016/0125649).
Regarding claim 1, Jeong discloses a method of operating a graphics processor, the method comprising:
for a sequence of primitives to be rendered for a render output:
performing a first, pre-pass operation in which primitives in the sequence of primitives to be rendered are rasterised into respective sets of one or more fragments, each set of fragments associated with a respective set of one or more sampling positions within the render output, and wherein the respective sets of one or more fragments are processed to determine visibility information for the sequence of primitives, the visibility information being usable to determine whether or not fragments for primitives in the sequence of primitives should subsequently be processed further for the render output (Par. 101: “In the first pipeline 710, the vertex shader 650 performs shading on a vertex by only using a location value of the vertex, the tessellation pipeline 660 performs tessellation by only using a location value of a patch, and the rasterization unit 670 performs rasterization by only using a location value of a primitive”, par. 58: “the rasterization is performed on the primitives by dividing each of the primitives into a plurality of fragments. A fragment is a unit for forming a primitive and is used as a basic unit for performing an image process”, and par. 60: “the depth test is performed by comparing a depth value of each input fragment with a depth value pre-stored in a depth buffer and corresponding to a location of each of the input fragments. When the depth value of each of the input fragments is less than the depth value pre-stored in the depth buffer, that is, when the input fragment is visible in a final output image, the depth test is performed by updating the depth value pre-stored in the depth buffer to the depth value of each of the input fragments. Accordingly, depth values of visible fragments are stored in the depth buffer as results of performing the depth test on all input fragments”. Although Jeong does not disclose that each fragment has one or more sampling positions, it is well known in the art that a fragment has at least one sampling position);
generating a primitive culling data structure using the visibility information determination, the primitive culling data structure being usable to determine for respective sets of one or more primitives whether the sets of one or more primitives can subsequently be culled in their entirety (Par. 101: “in the first pipeline 710, the depth test unit 610 determines a visible fragment via a depth test, and the P-buffer 620 stores an ID of a primitive corresponding to the visible fragment”. See also pars. 82-83. In particular, Fig. 4 shows a primitive visibility stream 450 comprising a table indicating visibility of each primitive, with 0 = not visible and 1 = visible. A person skilled in the art would recognize that this table could be implemented as an array data structure. Since this table will be referenced by the second pipeline 720 to determine whether a primitive should be further processed, it could be viewed as a primitive culling data structure); and
thereafter performing a second, main pass operation in which at least some primitives that were processed by the first, pre-pass operation are processed again by rasterising the primitives into their respective sets of one or more fragments for processing to determine rendered output data for sampling positions associated with the fragments and in which second, main pass operation the processing of primitives that were processed during the first, pre-pass operation is controlled based on the primitive culling data structure (Par. 102: “In the second pipeline 720… the rasterization unit 670 does not perform rasterization on primitives determined to be not visible based on the generated primitive visibility stream. In other words, the rasterization unit 670 performs rasterization only on primitives determined to be visible based on the generated primitive visibility stream”), wherein
the second, main pass operation comprises a step of using the primitive culling data structure to determine whether a primitive can be culled, wherein the step of using the primitive culling data structure to determine whether a primitive can be culled is performed prior to rasterisation, such that for any primitives for which it is determined using the primitive culling data structure that the primitive can be culled, the primitive is culled prior to rasterisation (As disclosed in par. 102 cited above, the rasterization unit 670 does not perform rasterization on primitives determined to be not visible based on the generated primitive visibility stream. Therefore, it could be said that these primitives are culled prior to rasterization).
Regarding claim 3, Jeong discloses the method of claim 1, wherein primitives in the sequence of primitives are defined in terms of a set of vertices for the primitive, wherein each vertex has a corresponding set of one or more vertex attributes that are to be used when rendering the primitive (Par. 58: “A primitive includes information about a vertex”, and par. 101: “In the first pipeline 710, the vertex shader 650 performs shading on a vertex by only using a location value of the vertex”), and wherein the second, main pass operation comprises a stage of processing of one or more vertex attributes for a primitive, wherein the step of using the primitive culling data structure to determine whether a primitive can be culled is performed prior to processing the one or more vertex attributes in the second, main pass operation (Par. 102: “In the second pipeline 720, the vertex shader 650 does not perform shading on vertices that are determined to be not visible, based on the generated vertex visibility stream. In other words, the vertex shader 650 performs shading on vertices determined to be visible based on the generated vertex visibility stream”).
Regarding claim 8, Jeong discloses the method of claim 1, wherein the primitive culling data structure comprises a bit mask, each bit indicating whether a respective set of one or more primitives represented by the bit can be culled (The second row of table 450 in Fig. 4 of Jeong could be viewed as a bit mask, with a “0” indicating an associated primitive should be culled, and a “1” indicating an associated primitive should be further processed).
Regarding claim 9, Jeong discloses the method of claim 1, wherein the primitive culling data structure is generated during the first, pre-pass operation alongside the processing of fragments to determine the visibility information for the sequence of primitives (As shown in Fig. 7 of Jeong, the content of the P-buffer (from which the table 450 is derived) is generated during the operation of the first pipeline 710).
Regarding claim 10, Jeong discloses the method of claim 1, wherein the primitive culling data structure for a sequence of primitives is generated after the first, pre-pass operation has completed processing the sequence of primitives to determine the visibility information for the sequence of primitives (As shown in Fig. 7 of Jeong, the primitive visibility stream, which contains table 450, is generated after the first pipeline 710 has completed processing primitives to determine their visibility), wherein the primitive culling data structure is generated using a set of primitive identifying information determined during the first, pre-pass operation that indicates which primitive should be rendered for which sampling positions of the render output (As can be seen in table 450, each primitive identifier is associated with a bit value indicating whether the corresponding primitive should be rendered for its sampling positions of a render output).
Claims 11, 13 and 18-20 recite similar limitations as respective claims 1, 3 and 8-10, but are directed to a graphics processor configured to implement the steps recited in the respective claims 1, 3 and 8-10. Since Jeong also discloses such a graphics processor (Fig. 7 suggests the first and second pipelines are part of a graphics processor), these claims could be rejected under the same rationales set forth in the rejection of their respective claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4-5 and 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeong.
Regarding claim 4, Jeong discloses the method of claim 1, wherein the primitive culling data structure is a (In the example shown in Fig. 4 of Jeong, the data structure 450 stores a number of entries, each entry indicating whether a primitive represented by the entry can be culled (if visibility = 0) or whether the primitive represented by the entry should be processed further (if visibility = 1)).
Jeong does not explicitly disclose that the data structure 450 has a fixed size for storing a fixed number of entries.
However, it would have been obvious to a person of ordinary skill in the art at the time of the invention to configure the data structure 450 to have a fixed size because a fixed-size data structure is a routine design choice and a well-known, predictable optimization technique used to enhance performance, reduce memory allocation overhead, and simplify memory management in computing systems. Implementing the data structure 450 as having a fixed size yields predictable results (efficient memory access) and constitutes a "finite number of identified solutions" for optimizing data storage. Therefore, modifying the data structure 450 to have a fixed size is merely a matter of obvious design choice.
Regarding claim 5, Jeong discloses the method of claim 4, wherein primitives in the sequence of primitives to be rendered are allocated a respective unique primitive identifier, and wherein the corresponding entry in the primitive culling data structure for a primitive is determined based on the respective unique primitive identifier for the primitive (See table 450 in Fig. 4 of Jeong).
Claims 14 and 15 recite similar limitations as respective claims 4 and 5, but are directed to a graphics processor configured to implement the steps recited in the respective claims 4 and 5. Since Jeong also discloses such a graphics processor (Fig. 7 suggests the first and second pipelines are part of a graphics processor), these claims could be rejected under the same rationales set forth in the rejection of their respective claims.
Claim(s) 6-7 and 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeong as applied to respective claims 5 and 15, and further in view of Engh-Halstvedt et al. (Pub. No. US 2019/0012829).
Regarding claims 6 and 7, Jeong does not explicitly teach the limitations recited in these claims. However, a person skilled in the art would recognize that the way of indexing a primitive as recited in these claims could easily be implemented with a modulo operation, which is a well-known mathematic operation. As an example, Engh-Halstvedt teaches an operation (vertex ID modulo n) (where vertex ID is a vertex identifier, and n is the size of a cache) to determine whether or not the vertex is within the memory range of the cache.
In light of Engh-Halstvedt’s teaching of the modulo operation, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to further modify Jeong by using the operation (primitive ID modulo n) (where primitive ID is a primitive’s identifier, and n is the fixed-size of the data structure 450 in Fig. 4 of Jeong) when the identifier is greater than the size of the data structure 450 because the modulo operation would return a value within the size of the data structure 450. On the other hand, if the identifier is smaller than the size of the data structure 450, it could be used directly to access the primitive.
Claims 16 and 17 recite similar limitations as respective claims 6 and 7, but are directed to a graphics processor configured to implement the steps recited in the respective claims 6 and 7. Since Jeong also discloses such a graphics processor (Fig. 7 suggests the first and second pipelines are part of a graphics processor), these claims could be rejected under the same rationales set forth in the rejection of their respective claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHONG X NGUYEN whose telephone number is (571)270-1591. The examiner can normally be reached Mon-Fri 8am - 5pm EST.
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/PHONG X NGUYEN/ Primary Patent Examiner, Art Unit 2617