DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries set forth in Graham v. John Deere Co. , 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim s 1 , 3-6, 10, and 12 - 13 are rejected under 35 U.S.C. 10 3 as being unpatentable over Sijun et al. ( CN 110545082 , published on December 6, 2019 , a marked copy of the machine translation has been relied upon and is attached herewith for reference . Regarding claim s 1 and 12 , Sijun discloses in Fig s . 2 and 3 , a Class D audio amplifier (reference numeral 200 , Fig. 2) configured to receive a differential input signal comprising a positive end input signal INp and a negative end input signal INn , and to generate a differential output signal comprising a positive end output signal OUTp and a negative end output signal OUTn . See Sijun , Fig. 2; Abstract. Fig. 2 of Sijun reproduced for ease of reference. Sijun also teaches a modulation connection circuit ( 201 , Fig. 2 and Fig. 3) that functions as a PWM modulator. The modulation connection circuit receives INp and INn and generates PWM output signals PWMP and PWMN . See Sijun , Fig. 3 ; Sijun further discloses a first comparator ( 311 , Fig. 3) having its non-inverting input coupled to receive the positive end input signal INp and its inverting input coupled to a triangular wave reference (generated by triangular wave generator 313 , Fig. 3). The output of comparator 311 is signal OP , which constitutes the first comparison result. See Sijun , Fig. 3. Sijun also discloses a second comparator ( 312 , Fig. 3) having its non-inverting input coupled to receive the negative end input signal INn and its inverting input coupled to the same triangular wave reference from generator 313 . The output of comparator 312 is signal ON , which constitutes the second comparison result. See Sijun , Fig. 3. Sijun then discloses an exclusive OR gate ( 3141 , Fig. 3) receiving the outputs of comparators 311 and 312 (signals OP and ON, i.e., the first and second comparison results) and generating an intermediate logic signal at node N1/N2 . This XOR output constitutes the first control signal as claimed. See Sijun , Fig. 3. Fig. 3 of Sijun reproduced for ease of reference. Sijun also teaches a first AND gate ( 3142 , Fig. 3) receiving the output of comparator 311 (OP, the first comparison result) and the output of XOR gate 3141 (the first control signal). The output of AND gate 3142 is routed through MUX 331 to produce PWMP , the positive end PWM output. See Sijun , Fig. 3. In terms of the logic circuitry , Sijun includ es gate 3144 (Fig. 3) associated with the negative channel, receiving the output of comparator 312 (ON, the second comparison result) and a signal derived from the XOR gate (the first control signal). The resulting output is routed through MUX 332 to produce PWMN , the negative end PWM output. See Sijun , Fig. 3. Finally Sijun teaches an output stage ( 230 , Fig. 2) coupled to receive PWMP and PWMN from the modulation circuit 201 and configured to generate the positive end output signal OUTp and the negative end output signal OUTn . Filter circuits 261 and 262 are further coupled at the output stage. See Sijun , Fig. 2. Thus Sijun discloses all elements of Claim 1 except, the direct coupling of the second AND gate's second input to the first control signal, instead routing it through a multiplexer. It would have been obvious to a person of ordinary skill in the art to simplify the signal path by directly coupling the XOR output (first control signal) to the inputs of both AND gates without an intervening MUX, as the Sijun itself demonstrates that the XOR signal drives the AND gate logic, and the MUX provides only a mode-selection function that a skilled artisan would recognize as design-choice optimization. The modification would have been a routine design choice with a predictable result — namely, simplified circuitry without the mode-switching capability — and would involve no more than ordinary skill and no unexpected results. Claim 3 depends on claim 2 and additionally requires a first delay unit configured to delay the first control signal for a first preset length of time to generate a delayed first control signal, wherein the second input ends of both the first and second AND gates receive this delayed first control signal rather than the undelayed first control signal. The Sijun , as applied to claims 1 and 2, discloses AND gates and an XOR-based control signal. The Sijun further demonstrates familiarity with signal timing management in PWM modulator contexts. See Sijun , ¶ ¶[ 0014]–[0016]. To the extent a delay unit is not expressly recited in the Sijun for this specific purpose, it would have been obvious to a POSITA to introduce a delay element on the first control signal (XOR output) path to the second input of the AND gates in order to compensate for the propagation delay introduced by the flip-flops added per claim 2. Specifically, once flip-flops are clocked by the first control signal and their outputs (registered comparator results) appear at the first inputs of the AND gates, the first control signal must similarly be delayed by the same flip-flop propagation delay before it arrives at the second inputs of the AND gates. Otherwise, a timing mismatch would cause the AND gates to produce erroneous glitch outputs during the brief window between the rising edge of the first control signal and the valid settling of the flip-flop output data. Inserting a matched delay element on the control signal path to align all signals at the AND gate inputs is a routine and well-recognized timing correction technique requiring no more than ordinary skill. The combination of the Sijun and the general knowledge of a POSITA regarding delay-matched digital signal paths renders claim 3 obvious under 35 U.S.C. § 103 . Claim 4 depends on claim 3 and specifies that the first preset length of time of the delay unit equals the elapsed time for a signal to travel from the clock input ends to the output ends of the first and second flip-flops (i.e., the clock-to-Q propagation delay of the flip-flops). As discussed in the rejection of claim 3, a POSITA would have recognized that the delay introduced by the first delay unit must be matched to the clock-to-Q propagation delay of the flip-flops to ensure temporal alignment of all signals at the AND gate inputs. Setting the delay unit's delay equal to the flip-flop's clock-to-Q propagation delay is the only technically sound and logical choice; any other delay value would either fail to eliminate the timing hazard (if too short) or introduce unnecessary idle output suppression (if too long). This selection of a delay value is a straightforward engineering determination within the ordinary skill in the art and yields entirely predictable results. The Sijun , combined with ordinary design principles known to a POSITA for timing closure in digital PWM modulator circuits, renders claim 4 obvious under 35 U.S.C. § 103 . Claim 5 depends on claim 1 and alternatively requires: (a) a second delay unit that delays the first comparison result for a second preset length of time to generate a delayed first comparison result; (b) a third delay unit that delays the second comparison result for a third preset length of time to generate a delayed second comparison result; and (c) the first input ends of the first and second AND gates receive the delayed first and second comparison results, respectively. The Sijun , as applied to claim 1, discloses comparators 311 and 312 generating comparison results OP and ON, an XOR gate 3141, and AND gate 3142. See Sijun , Fig. 3, ¶[ 0015]. The Sijun does not expressly disclose delay units on the comparison result paths to the AND gate first input ends. However, it would have been obvious to a POSITA to alternatively address the same timing hazard identified above (asynchronous arrival of the comparator outputs and the XOR output at the AND gate inputs) by delaying the comparator outputs — rather than the XOR output — by an amount equal to the propagation delay of the XOR gate itself. This alternative approach achieves the same timing alignment goal as the approach recited in claim 3: ensuring that the AND gate first inputs (now carrying delayed comparison results) and the AND gate second inputs (carrying the undelayed XOR output) are temporally aligned. A POSITA would have recognized both approaches — delaying the control signal path or delaying the data paths — as equivalent and interchangeable design alternatives for achieving glitch-free AND gate output, and would have had obvious motivation and reasonable expectation of success in implementing either approach. The combination of the Sijun and the general knowledge of a POSITA regarding signal timing in digital logic circuits renders claim 5 obvious under 35 U.S.C. § 103 . Claim 6 depends on claim 5 and specifies that the second preset length of time and the third preset length of time each equal the elapsed time for a signal to pass through the exclusive OR gate. As discussed in the rejection of claim 5, a POSITA would recognize that when the comparison results are delayed to align temporally with the XOR output at the AND gates, the correct delay value is precisely the propagation delay of the XOR gate. Setting the delay equal to the XOR propagation delay is the only logically consistent choice that achieves temporal alignment between the AND gate inputs, and represents a routine engineering determination fully within the ordinary skill in the art. The Sijun , combined with the ordinary knowledge of a POSITA regarding propagation delay matching in combinational digital circuits, renders claim 6 obvious under 35 U.S.C. § 103 . Claim 10 depends on claim 8 and specifies that the synthesis circuit comprises a third AND gate, wherein the first input of the third AND gate receives the first control signal, the second input receives the second control signal, and the output provides the third control signal. The Sijun discloses an AND gate (3142) in circuit 314, and multiple AND gate implementations throughout. See Sijun , Fig. 3, ¶[ 0015]. The use of an AND gate to synthesize a combined clock signal from two individual control signals is a fundamental and routine digital logic design technique. A POSITA would have immediately recognized that the most straightforward implementation of a synthesis circuit that generates a third control signal from a first and second control signal is an AND gate, because the AND gate's output is active only when both inputs are simultaneously active — precisely the condition under which the combined quaternary modulation clock should trigger the flip-flops. This is an obvious, single-component implementation requiring no inventive step. The Sijun , combined with the general knowledge of a POSITA in digital logic gate design, renders claim 10 obvious under 35 U.S.C. § 103 . Claim 12 depends on claim 1 1 and specifies that the first preset length of time equals the elapsed time for a signal to travel from the clock input ends to the output ends of the first and second flip-flops. For the same reasons stated in the rejection of claim 4 — which is directly analogous — setting the delay to equal the clock-to-Q propagation delay of the flip-flops is the only technically correct choice for achieving timing alignment at the AND gate inputs, and is a routine engineering determination within ordinary skill in the art. The Sijun and the Toshiro , combined with ordinary design principles, render claim 12 obvious under 35 U.S.C. § 103 . Claim 13 depends on claim 1 and specifies that the first control signal is zero when the differential input signal is zero. This limitation is an inherent and mathematically necessary consequence of the structure already disclosed in the Sijun as applied to claim 1. When the differential input signal is zero, the positive end input signal equals the negative end input signal. Consequently, both comparators (311 and 312 in the Sijun ) compare identical signal levels against the same triangular wave and always produce identical comparison results at every instant (OP = ON). The XOR gate (3141), by definition, outputs a logic zero whenever its two inputs are identical. Therefore, the XOR output (first control signal) is necessarily and inherently zero whenever the differential input is zero, regardless of the triangular wave. This property is a logical tautology inherent to the disclosed XOR gate structure. To the extent this limitation is not expressly stated in the Sijun , it is inherently disclosed thereby. Claim 13 is obvious under 35 U.S.C. § 103 in view of the Sijun and the inherent mathematical properties of XOR gate logic as known to a POSITA. Claim s 2 , 7-9, 11 and 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over Sijun in view of Toshi r o (WO2005117250, a machine translation has been relied upon and is attached herewith). Claim 2 depends on claim 1 and further requires that the PWM modulator comprise: (a) a first flip-flop whose clock input receives the first control signal (XOR output) and whose data input receives the first comparison result; (b) a second flip-flop whose clock input receives the first control signal and whose data input receives the second comparison result; and (c) the first input ends of the first and second AND gates are correspondingly coupled to the output ends of the first and second flip-flops, respectively, and the second input ends of the AND gates receive the first control signal. The Sijun discloses, as applied to claim 1, an XOR gate (3141) generating an intermediate control signal at node N2, an AND gate (3142) generating a positive ternary PWM output (TP), and a NOR gate (3144) generating a negative ternary PWM output (TN). See Sijun , Fig. 3, ¶ ¶[ 0014]–[0015]. The Sijun further discloses multiple D flip-flops (3211, 3221, 3232, 3251) in its detection circuit (320), demonstrating that the skilled artisan was familiar with using D-type flip-flops to latch and synchronize digital signals in Class D amplifier PWM modulator contexts. See Sijun , Fig. 4, ¶ ¶[ 0017]–[0024]. To the extent the Sijun does not expressly position flip-flops at the inputs of the AND gates within the signal generation circuit (314) to synchronize the comparator output signals with the XOR control signal before they arrive at the AND gates, it would have been obvious to a person of ordinary skill in the art ("POSITA") at the time of the invention to insert D-type flip-flops clocked by the XOR output (first control signal) to register the comparator outputs (first and second comparison results) immediately before the AND gate inputs. This is a well-established standard digital circuit design technique for resolving timing hazards, metastability, and glitch propagation that arise when asynchronously generated logic signals — here, the comparator outputs and the XOR output — arrive at an AND gate with potentially misaligned edges. The motivation to add such synchronizing flip-flops would have been readily apparent to a POSITA, and the result would have been entirely predictable: clean, glitch-free PWM output pulses. See also Toshiro , Figs. 1–3, disclosing XOR/AND logic gate combinations for generating differential PWM pulses from comparator outputs using a shared triangular wave, confirming the state of the art in this circuit topology and the desirability of clean digital signal transitions at the output stage. The combination of the Sijun with the ordinary knowledge and skill of a POSITA regarding flip-flop synchronization circuits renders claim 2 obvious under 35 U.S.C. § 103 . Claim 7 depends on claim 1 and requires a first low-pass filter coupled between the output end of the first AND gate and the output stage, and a second low-pass filter coupled between the output end of the second AND gate and the output stage. The Sijun expressly discloses filters 261 and 262 coupled between the output stage (230) and the load, as shown in Fig. 2, ¶[ 0013]. These filters are positioned to remove high-frequency switching content from the PWM output signals, which is the standard and universally known purpose of low-pass filters in Class D amplifier designs. See also Toshiro , which discloses a motor load drive circuit in which PWM signals drive a motor (M, Fig. 1) through output buffers (11, 12), with the understanding that filtering is a conventional element of such circuits. It would have been obvious to a POSITA to couple low-pass filters between the AND gate outputs of the PWM modulator and the input of the output stage of the Class D amplifier of claim 1 to reconstruct the analog audio signal from the PWM pulses, suppress switching noise, and comply with electromagnetic interference requirements — all standard and well-understood design considerations. The placement and purpose of such low-pass filters in Class D amplifiers were well within the ordinary skill in the art at the time of the invention. The Sijun alone, or combined with the Toshiro , renders claim 7 obvious under 35 U.S.C. § 103 . Claim 8 depends on claim 1 and adds a substantially expanded set of elements: (a) a third comparator generating a third comparison result based on the positive end input signal and an inverted triangular wave; (b) a fourth comparator generating a fourth comparison result based on the negative end input signal and the inverted triangular wave; (c) the XOR gate configured to also generate a second control signal based on the third and fourth comparison results; (d) a synthesis circuit generating a third control signal based on the first and second control signals; (e) a first flip-flop whose clock input receives the third control signal and whose data input receives the first comparison result; (f) a second flip-flop whose clock input receives the third control signal and whose data input receives the second comparison result; and (g) the first and second AND gates coupled to the flip-flop outputs and the third control signal. The Sijun , as applied to claim 1, discloses comparators 311 and 312 comparing the integrator output signals (positive and negative end input signals) against a triangular wave (TRI) generated by oscillator (OSC) and comparator 313. See Sijun , Fig. 3, ¶[ 0014]. The Sijun further discloses an XOR gate (3141), an AND gate (3142), and a NOR gate (3144), establishing a signal generation circuit for producing both a positive ternary modulation signal (TP) and a negative ternary modulation signal (TN). Id. The Toshiro is additionally applied here. The Toshiro discloses a coil load drive circuit (Fig. 1, element 1) comprising: a transfer voltage generating circuit that generates two transfer voltages (V_TR1 and V_TR2) proportional to the difference between the input control voltage (V_IN) and the input reference voltage (V_REF); two comparators (14, 15) that compare V_TR1 and V_TR2 against a common triangular wave (TRI) from oscillator (13), thereby generating first and second PWM signals (PW1, PW2); an XOR gate (21) that produces an exclusive signal (EX) based on PW1 and PW2; and AND gates (22, 23) that combine PW1 and PW2 with the EX signal to generate differential output signals driving both terminals of a motor. See Toshiro , Fig. 1, Abstract, ¶¶ describing the output pulse combining circuit (16). Critically, the Toshiro further discloses in Fig. 3 a variant embodiment wherein the transfer voltage generating circuit generates two transfer voltages in a differential fashion — one derived from each polarity channel — using separate summing amplifiers (33, 34). The triangular wave (TRI) from OSC (13) is applied to both comparators (14, 15), but by virtue of the differential input stage, the effective comparison performed by comparators 14 and 15 against the triangular wave corresponds to comparing positive and negative end input signals against the same triangular carrier, which is functionally equivalent to comparing against the triangular wave and its inverted form, respectively. Furthermore, the concept of using both a triangular wave and its inverted version (or equivalently, deriving two opposing-phase comparator reference signals) to generate a four-level (quaternary) modulation output — as opposed to the three-level ternary output — was explicitly known in the art and is discussed in the background section of the Sijun . See Sijun , ¶ ¶[ 0003]–[0004] (discussing quaternary modulation using four output states and citing US 6262632). The Sijun itself discloses that its modulation selection circuit generates both a ternary modulation signal (three-level) and a quaternary modulation signal (four-level) and selects between them based on output power conditions. See Sijun , Abstract, ¶[ 0005]. The quaternary modulation signal in the Sijun (QP, QN) is inherently generated using a comparison against both polarities of the triangular wave, which is functionally equivalent to using both the triangular wave and its inverted version as claimed. It would therefore have been obvious to a POSITA to combine the Sijun 's disclosed signal generation architecture — which inherently produces both ternary and quaternary PWM signals using both polarities of the triangular wave reference — with the Toshiro 's differential comparator and XOR/AND gate output combining topology, to arrive at the PWM modulator recited in claim 8. Specifically: the use of a third and fourth comparator with an inverted triangular wave to generate additional comparison results (third and fourth comparison results), combined with a second application of the XOR gate to these results to generate a second control signal, and a synthesis circuit (AND gate) to combine the first and second control signals into a third (combined) control signal used to clock the synchronizing flip-flops, represents the logical and predictable extension of the ternary circuit of claim 1 into the quaternary domain — exactly the direction the Sijun itself motivates. A POSITA would have had clear motivation and reasonable expectation of success in making this combination. The Sijun and the Toshiro , in combination, render claim 8 obvious under 35 U.S.C. § 103 . Claim 9 depends on claim 8 and specifies that the frequency of the first comparison result equals the frequency of the second comparison result, and that during a positive input phase and a negative input phase, the frequency of the first control signal is twice the frequency of the third comparison result and twice the frequency of the fourth comparison result. These frequency relationships are inherent mathematical consequences of the XOR gate operation on the comparator output signals. When two comparators compare a positive-polarity signal and a negative-polarity signal (symmetric about a midpoint) against the same triangular wave carrier, the resulting XOR output (exclusive OR of the two comparator results) operates at twice the carrier frequency relative to the individual comparison results during non-zero input phases — this is a well-known property of differential PWM modulation with XOR-based control signal generation and was explicitly acknowledged in the prior art. See Sijun , ¶[ 0003] and the description of quaternary versus ternary modulation frequency behavior. The Sijun and the Toshiro , applied as discussed in the rejection of claim 8, combined with the inherent mathematical properties of the XOR gate in this circuit configuration known to a POSITA, render claim 9 obvious under 35 U.S.C. § 103 . Claim 11 depends on claim 8 and requires a first delay unit configured to delay the third control signal for a first preset length of time to generate a delayed third control signal, wherein the second input ends of both the first and second AND gates receive the delayed third control signal. For the same reasons stated in the rejection of claim 3 — and substituting the third control signal (the synthesized combined control signal from the synthesis circuit) for the first control signal of claim 3 — it would have been obvious to a POSITA to delay the third control signal at the second inputs of the AND gates in order to match the propagation delay introduced by the flip-flops clocked by that same third control signal. The technical motivation, the predictability of the solution, and the skill level required are identical to those discussed in claim 3. The Sijun and the Toshiro , combined with the ordinary knowledge of a POSITA regarding propagation delay matching in digital logic circuits, render claim 11 obvious under 35 U.S.C. § 103 . Claim 14 depends on claim 1 and specifies that the positive end PWM output is zero when the positive end input signal is not higher than the negative end input signal. The Sijun discloses that the positive ternary modulation signal TP is generated by AND gate 3142 receiving signals from nodes N1 and N2, which are respectively the XOR output and the AND of nodes N1 and N2. See Sijun , Fig. 3, ¶[ 0015]. When the positive end input signal is not higher than the negative end input signal, the first comparison result (OP from comparator 311) will never exceed the second comparison result (ON from comparator 312) in a manner that produces a non-zero AND gate output. This is a direct mathematical consequence of the AND gate and XOR gate logic applied to differential comparator outputs sharing a common triangular wave reference and is inherently disclosed by the Sijun 's circuit structure as applied to claim 1. The Toshiro further confirms this complementary behavior of the differential PWM output signals (PW1, PW2 in Figs. 2 and 6), showing that when V_IN is below V_REF, OUT1 carries no active pulses while OUT2 carries active pulses, and vice versa. See Toshiro , Figs. 2(f)–(g) and 6(f)–(g). Claim 14 is obvious under 35 U.S.C. § 103 in view of the Sijun , the Toshiro , and the inherent properties of the disclosed circuit structure. Claim 15 depends on claim 1 and specifies that the negative end PWM output is zero when the negative end input signal is not higher than the positive end input signal. This is the symmetric counterpart to claim 14 and is rejected for the same reasons. When the negative end input signal is not higher than the positive end input signal, the differential relationship ensures the second comparison result processed through the second AND gate produces a zero output, by the same inherent XOR/AND gate logic. See Sijun and Toshiro as applied to claim 14 above. The complementary and symmetric behavior of the differential PWM outputs is expressly illustrated in the Toshiro at Figs. 2(f)–(g) and 6(f)–(g), confirming that the two output channels are active in mutually exclusive input phase conditions. Claim 15 is obvious under 35 U.S.C. § 103 in view of the Sijun and the Toshiro . Claim 16 depends on claim 1 and requires a gate driver coupled between the PWM modulator and the output stage. Gate drivers are universally recognized as standard, essential interface components in Class D amplifier designs, positioned between the PWM logic circuitry and the power output transistors (output stage) to provide the necessary current drive capability and level shifting required to switch the output transistors efficiently and safely. The Sijun discloses an output stage (230) receiving PWM signals from the modulation selection circuit (201). See Sijun , Fig. 2. The inclusion of a gate driver between the PWM logic output and the power transistor gate terminals in such a circuit is not merely obvious but is a fundamental and mandatory design practice universally employed by those of ordinary skill in Class D amplifier design. The Toshiro further discloses output buffers (11, 12, comprising transistors 11a, 11b, 12a, 12b) receiving PWM signals directly and driving the motor terminals, with these buffer transistors constituting a combined gate driver and output stage. See Toshiro , Fig. 4. The addition of a separate gate driver between the PWM modulator and the output stage as recited in claim 16 represents nothing more than a routine design choice well within the ordinary skill in the art. Claim 16 is obvious under 35 U.S.C. § 103 in view of the Sijun and/or the Toshiro . Claim 17 depends on claim 1 and defines three operating phases: (a) a static phase in which both positive and negative end input signal amplitudes are zero; (b) a positive input phase in which both signals have equal absolute amplitudes, the positive end being greater than zero and the negative end being less than zero; and (c) a negative input phase in which both signals have equal absolute amplitudes, the positive end being less than zero and the negative end being greater than zero. These operating phase definitions describe the standard differential signal operating conditions of a fully differential Class D amplifier, which are inherent to the circuit's nature and not structural limitations of the claims. The Sijun discloses a Class D amplifier (200) receiving differential input signals INp and INn , and describes operation under conditions where the input amplitude is large (large output power) and small (small output power). See Sijun , ¶ ¶[ 0012], [0018], [0020], [0027]–[0030]. The Toshiro similarly describes differential input operation with positive and negative signal phases, as illustrated in the timing diagrams of Figs. 2 and 6, where V_IN crosses V_REF representing the transition between positive and negative input phases in a single-ended context analogous to the differential phase definitions of claim 17. The three operating phase conditions recited in claim 17 are standard differential circuit operating states that would have been immediately recognized and characterized by a POSITA designing a fully differential Class D amplifier. Claim 17 is obvious under 35 U.S.C. § 103 in view of the Sijun and the Toshiro . Claim 18 depends on claim 1 and specifies that the frequency of the first comparison result equals the frequency of the second comparison result, and that during positive and negative input phases, the frequency of the first control signal (XOR output) is twice the frequency of each of the first and second comparison results. As discussed in the rejection of claim 9, this frequency doubling is an inherent mathematical consequence of XOR gate operation on two comparator outputs generated by comparing a differential input signal against the same triangular wave carrier. When the input is non-zero, the positive and negative comparator outputs are complementary pulse trains at the carrier frequency, and their XOR produces a pulse train at twice the carrier frequency. This property was well understood in the art. See Sijun , ¶[ 0003] (discussing the difference between ternary and quaternary modulation behaviors) and Toshiro , Figs. 2(c)–(e) (illustrating PW1, PW2, and EX waveforms, wherein EX is visually demonstrably at higher frequency than PW1 or PW2 individually). A POSITA would have readily recognized and understood these frequency relationships from the disclosed circuit structures. Claim 18 is obvious under 35 U.S.C. § 103 in view of the Sijun and the Toshiro . Claim 19 recites a chip comprising the Class D amplifier of claim 1. The integration of a Class D amplifier circuit onto a single integrated circuit chip was standard practice in the art at the time of the invention, as confirmed by the Sijun (which is directed to a semiconductor circuit implementation suitable for chip integration) and the Toshiro (which discloses a coil load drive circuit similarly implemented as an integrated circuit). The implementation of the Class D amplifier of claim 1 as an integrated circuit chip would have been an obvious design choice requiring nothing more than ordinary skill in semiconductor circuit integration. Claim 19 is obvious under 35 U.S.C. § 103 for at least the reasons stated with respect to claim 1, and additionally in view of the standard practice of chip integration as reflected in the Sijun and the Toshiro . Claim 20 recites an electronic apparatus comprising the chip of claim 19. The incorporation of a Class D amplifier chip into an electronic apparatus — such as a consumer audio device, mobile phone, or other audio-capable electronics — is a straightforward and obvious system-level design choice that follows directly from the purpose of the claimed Class D amplifier. The Sijun discloses a Class D audio amplifier (200) suitable for driving audio loads, inherently implying incorporation into an audio electronic apparatus. See Sijun , Abstract, ¶[ 0002]. The Toshiro discloses incorporation of a coil load drive circuit into an optical disc device (Fig. 14, element 502), demonstrating the practice of embedding such drive circuits into complete electronic apparatus. A POSITA would have found it obvious to incorporate the chip of claim 19 into an electronic apparatus. Claim 20 is obvious under 35 U.S.C. § 103 for at least the reasons stated with respect to claim 1 and claim 19, and additionally in view of the system-level teachings of the Sijun and the Toshiro . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Enter examiner's name" \* MERGEFORMAT HAFIZUR RAHMAN whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-0659 . The examiner can normally be reached FILLIN "Work schedule?" \* MERGEFORMAT M-F: 10-6 . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached on FILLIN "SPE Phone?" \* MERGEFORMAT (571) 272-1769 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. /HAFIZUR RAHMAN/ Primary Examiner, Art Unit 2843.