Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are presented for examination.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As to claim 1, the limitation “instantiating…a first processor” renders the claim unclear. More specifically, it is unclear how an emulation software creates instances (i.e. instantiating) of a hardware component and whether applicant intents to claim the instantiation of an emulated instance of a first processor which is based on a device model representing respective emulated hardware components or simply instantiating of VM that emulates the first processor [paragraphs 29-31 and 34; paragraph 51, lines 1-3] as disclosed in applicant’s specification disclosure. For examination purpose the limitation “instantiating…a first processor” is treated in light of applicant’s specification as emulating a physical component by or for use by a VM for the remainder of this office action.
As to claims 2 and 6, these claims further recite instantiation of the second processor and are rejected for the same reason as claim 1 above.
As to claims 3-5 and 7-13, these claims depend on claim 1 and failed to cure the deficiency of claims 1 and/or 6, therefore they are rejected for the same reason.
As to claims 14-20, these claims are rejected for the same reason as claims 1-13 above.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 14-18 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by "Shared-Memory Optimizations for Inter-Virtual-Machine Communication" to Ren et al. (hereafter Ren).
As to claim 14, Ren teaches the invention as claimed including a method for inter-processor interface emulation, comprising:
instantiating, via an emulation software, a first processor based on a first model [running instance of a VM having where the VMM/KVM and/or QEMU abstracts host hardware of host(s), implicitly includes processor of particular model, p. 49:2, section 1.1. Problems of Coresident VM Communication and Related Work, lines 1-6]; and
emulating a communication interface between the first processor and a second
processor, the communication interface configured to model communication channels between the first processor and the second processor [QEMU provides I/O device model for VM, emulating devices allowing guest OSes of VMs to communicate via shared memory channels or message channels, p. 49:1; virtualized network I/O, pp. 49:6-49:7, section 2.2. QEMU/KVM – section 3.1 TCP/IP Versus Shared-Memory-Based Approaches; p. 49:8, section 3.2 Design Objectives, lines 1-17].
As to claim 15, Ren teaches the invention as claimed including further comprising: generating, via the emulation software, a first virtual machine (VM) and second VM, wherein the first processor is instantiated in the first VM, and wherein the second processor is instantiated in the second VM [running instances of VMs/Guest OSes of VMs executing in respective hardware of host(s), Fig. 2 and corresponding text].
As to claim 16, Ren teaches the invention as claimed including a wherein the emulation software comprises a quick emulator (QEMU) [QEMU, Fig. 2 and corresponding text].
As to claim 17, Ren teaches the invention as claimed including further comprising: sharing at least a portion of memory resources between the first processor and the second processor [inter-VM shared memory channels, p. 49:1].
As to claim 18, Ren teaches the invention as claimed including a wherein the portion of memory resources is shared via an inter-emulation shared memory (IESHM) device model [QEMU and/or KVM provided I/O device model for VM, virtualizes network devices of the host OS…full-virtualized network I/O, pp. 49:6-49:7, section 2.2 QEMU/KVM; Fig. 2].
As to claims 1-5, Ren teaches the method for inter-processor interface emulation in claims 14-18, therefore Ren teaches the apparatus for implementing the method.
As to claim 20, Ren teaches the method for inter-processor interface emulation in claim 14, therefore Ren teaches the non-transitory, computer-readable medium comprising computer executable code, the code when executed by one or more processors causes the one or more processors to implement the method.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6-9 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ren as applied to claims 1 and 14 above, and further in view of US PG Pub. 2020/0133704 to Habkost.
As to claim 19, Ren does not specifically teach instantiating, via the emulation software, the second processor based on a second model different from the first model. However, Habkost teaches the instantiation of different CPU models (i.e. different vCPUs for different VMs respectively) to be emulate for each VM [paragraphs 10-16, 21, 28-30]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combine Habkost with Ren to extend Ren’s teaching of inter-VM communication to VM of different machines to different machines of different architectures to achieve the predictable result of optimizing inter-VM communication.
As to claim 6, this claim is rejected for the same reason as claim 19 above.
As to claim 7, Ren and Habkost teaches the invention substantially as claimed including wherein each of the first model and the second model comprises one of a microprocessor model or a system-on-a-chip model [Habkost, paragraph 68].
As to claim 8, Ren and Habkost teaches the invention substantially as claimed including wherein the second processor is a different architecture of processor relative to the first processor [Habkost, paragraph 68].
As to claim 9, Ren and Habkost teaches the invention substantially as claimed including wherein the communication interface is agnostic to a type of processor associated with the first processor and the second processor [Ren, virtualized network I/O, such that virtualization technology including a VMM is an abstraction layer that is hardware agnostic, p. 49:2, section 1.1. Problems of Coresident VM Communication and Related Work, lines 1-25; p. 49:5, section lines 1-6; QEMU provides I/O device model for VM, emulating devices allowing guest OSes of VMs to communicate via shared memory channels or message channels, p. 49:1; pp. 49:6-49:7, section 2.2. QEMU/KVM].
Allowable Subject Matter
Claims 10-13 would be allowable by overcoming the 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph rejection above and rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Inter-VM communication via buffers at respective end of an emulated environment [VNIC buffer, section 2.2.1] was disclosed by Ren. Inter-VM communication that uses shared memory [abstract]; implementation of the system in different microprocessor systems or microprocessor-based computing devices [col. 15, lines 53-57]; use of status and control registers in facilitating inter-process communication between VMs [col. 8, lines 18-56; Fig. 4 and corresponding text] was disclosed in US Patent 8,521,966. The prior arts of record when taken individually or in combination do not expressly teach or render obvious the invention as a whole as recited in claims 10-13.
Neither a reference uncovered that would have provided a basis of evidence for asserting a motivation, nor one of ordinary skilled in the art before the effective filing date of the claimed invention, knowing the teaching of the prior arts of record would have combined them to arrive at the present invention as recited in claims 10-13 as a whole.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to QING YUAN WU whose telephone number is (571)272-3776. The examiner can normally be reached M-F 9AM-6PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lewis Bullock can be reached on 571-272-3759. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC)
at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/QING YUAN WU/Primary Examiner, Art Unit 2199