Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4, 6, 10-12, 15 and 16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wu et al., US Patent Application (20240339411), “Wu”
Regarding claim 1 Wu teaches a three-dimensional integrated circuit the three-dimensional integrated circuit (3D IC) structure [Wu para 0056] comprising: a first integrated circuit comprising at least a first transistor the first semiconductor die [Wu para 0056] and a first buried oxide layer a first silicon insulation layer 176 may be formed on an upper surface of the first semiconductor die 130 [Wu para 0099] the first silicon insulation layer 176 and the second silicon insulation layer 177 may include silicon oxide or TEOS formation oxide. [Wu para 0100]; a second integrated circuit the second semiconductor comprising at least a second transistor the second semiconductor die [Wu para 0056] and a second buried oxide layer a second insulation member disposed between the substrate and the second three-dimensional integrated circuit structure [Wu para 0021] the second silicon insulation layer 177 may be silicon nitride, silicon oxynitride, or other suitable dielectric material. [Wu para 0100]; a bond interface between an upper surface of the first integrated circuit and an upper surface of the second integrated circuit the first bonding pad 174 on the upper surface of the first semiconductor die 130 and the second bonding pad 175 of the bottom surface of the second semiconductor die 180 may be made of the same material, such that after the hybrid bonding, the interface between the first bonding pad 174 on the upper surface of the first semiconductor die 130 and the second bonding pad 175 of the bottom surface of the second semiconductor die 180 may disappear. [Wu para 0098]; a passivation layer coupled to the first buried oxide layer the first silicon insulation layer 176 and the second silicon insulation layer 177 may include SiO.sub.2. … the first silicon insulation layer 176 and the second silicon insulation layer 177 may be silicon nitride, silicon oxynitride, or other suitable dielectric material [Wu para 0100]; and a mold wafer coupled to the second buried oxide layer. The molding material 160 may cover an upper surface of the second semiconductor die 180 and extend along the sidewalls of the second semiconductor die 180 to an exposed surface of the wafer 135 around a periphery of the second semiconductor die 180. The molding material 160 may be in direct contact with a portion of the wafer 135. [Wu para 0103 and see Figs 10 and 11]
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Regarding claim 4 Wu teaches claim 1 in addition Wu teaches further comprising: a porous silicon layer interposed between the second buried oxide layer and the mold wafer. the through silicon via (TSV) 132 may be formed by forming holes penetrating an insulating material of the wafer 135 and filling the holes with a conductive material [Wu para 0074 and see Fig. 11]
Regarding claim 6 Wu teaches claim 1 in addition Wu teaches further comprising: a partially removed silicon layer interposed between the second buried oxide layer and the mold wafer, wherein the partially removed silicon layer comprises first and second crystalline silicon end portions. where the CMP process can remove a sufficient amount of molding material 160 to expose an upper surface of the semiconductor chip 183. [Wu para 0105]
Regarding claim 10 Wu teaches a three-dimensional integrated circuit the three-dimensional integrated circuit (3D IC) structure [Wu para 0056] comprising: a first integrated circuit comprising at least a first transistor the first semiconductor die [Wu para 0056] and a first buried oxide layer a first silicon insulation layer 176 may be formed on an upper surface of the first semiconductor die 130 [Wu para 0099] the first silicon insulation layer 176 and the second silicon insulation layer 177 may include silicon oxide or TEOS formation oxide. [Wu para 0100]; a second integrated circuit the second semiconductor comprising at least a second transistor the second semiconductor die [Wu para 0056] and a second buried oxide layer a second insulation member disposed between the substrate and the second three-dimensional integrated circuit structure [Wu para 0021] the second silicon insulation layer 177 may be silicon nitride, silicon oxynitride, or other suitable dielectric material. [Wu para 0100]; a bond interface between an upper surface of the first integrated circuit and an upper surface of the second integrated circuit the first bonding pad 174 on the upper surface of the first semiconductor die 130 and the second bonding pad 175 of the bottom surface of the second semiconductor die 180 may be made of the same material, such that after the hybrid bonding, the interface between the first bonding pad 174 on the upper surface of the first semiconductor die 130 and the second bonding pad 175 of the bottom surface of the second semiconductor die 180 may disappear. [Wu para 0098]; a passivation layer coupled to the first buried oxide layer the first silicon insulation layer 176 and the second silicon insulation layer 177 may include SiO.sub.2. … the first silicon insulation layer 176 and the second silicon insulation layer 177 may be silicon nitride, silicon oxynitride, or other suitable dielectric material [Wu para 0100]; and an insulating substrate layer coupled to the second buried oxide layer, wherein the insulating substrate layer comprises aluminum nitride (AlN), aluminum oxide (Al2O3), or glass. The carrier 190 may include, for example, a silicon-based material such as glass or a silicon oxide, an organic material, or another material such as an aluminum oxide, a combination of these materials, and the like. [Wu para 0087]
Regarding claim 11 Wu teaches a method for fabricating a three-dimensional integrated circuit, the three-dimensional integrated circuit (3D IC) structure [Wu para 0056] the method comprising: fabricating a first silicon wafer having a plurality of first integrated circuits a first silicon insulation layer 176 may be formed on an upper surface of the first semiconductor die 130 [Wu para 0099] the first silicon insulation layer 176 and the second silicon insulation layer 177 may include silicon oxide or TEOS formation oxide. [Wu para 0100];; fabricating a second silicon wafer having a plurality of second integrated circuits a second insulation member disposed between the substrate and the second three-dimensional integrated circuit structure [Wu para 0021] the second silicon insulation layer 177 may be silicon nitride, silicon oxynitride, or other suitable dielectric material. [Wu para 0100]; polishing an upper surface of the first silicon wafer; polishing an upper surface of the second silicon wafer chemical mechanical polishing (CMP) may be performed [Wu para 0103]; bonding the upper surface of the first silicon wafer to the upper surface of the second silicon wafer the first bonding pad 174 on the upper surface of the first semiconductor die 130 and the second bonding pad 175 of the bottom surface of the second semiconductor die 180 may be made of the same material, such that after the hybrid bonding, the interface between the first bonding pad 174 on the upper surface of the first semiconductor die 130 and the second bonding pad 175 of the bottom surface of the second semiconductor die 180 may disappear. [Wu para 0098]; removing a portion of the first silicon wafer to expose a first buried oxide layer; attaching an intermediate handling wafer to the first silicon wafer; removing a portion of the second silicon wafer to expose a second buried oxide layer chemical mechanical polishing (CMP) may be performed to remove and level the upper surface of the molding material 160. The upper surface of the molding material 160 may be planarized by applying a CMP process, where the CMP process can remove a sufficient amount of molding material 160 to expose an upper surface of the semiconductor chip 183. [Wu para 0103]; and attaching a mold wafer to the second silicon wafer. The molding material 160 may cover an upper surface of the second semiconductor die 180 and extend along the sidewalls of the second semiconductor die 180 to an exposed surface of the wafer 135 around a periphery of the second semiconductor die 180. The molding material 160 may be in direct contact with a portion of the wafer 135. [Wu para 0103 and see Figs 10 and 11]
Regarding claim 12 Wu teaches claim 11 in addition Wu teaches further comprising: removing the intermediate handling wafer; and singularization of the bonded first and second integrated circuits and the mold wafer to provide a plurality of three-dimensional integrated circuits. chemical mechanical polishing (CMP) may be performed to remove and level the upper surface of the molding material 160. The upper surface of the molding material 160 may be planarized by applying a CMP process, where the CMP process can remove a sufficient amount of molding material 160 to expose an upper surface of the semiconductor chip 183. [Wu para 0105]
Regarding claim 15 Wu teaches claim 11 in addition Wu teaches further comprising: forming a porous silicon layer interposed between the second buried oxide layer and the mold wafer, wherein the porous silicon layer comprises first and second crystalline silicon end portions. the through silicon via (TSV) 132 may be formed by forming holes penetrating an insulating material of the wafer 135 and filling the holes with a conductive material [Wu para 0074 and see Fig. 11]
Regarding claim 16 Wu teaches claim 11 in addition Wu teaches further comprising: forming a partially removed silicon layer interposed between the second buried oxide layer and the mold wafer. where the CMP process can remove a sufficient amount of molding material 160 to expose an upper surface of the semiconductor chip 183. [Wu para 0105]
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 3, 5, 13, 14 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu and Bach et al., US Patent Application (20230395572), hereinafter “Bach”.
Regarding claim 2 Wu teaches claim 1 in addition Wu does not teach but Bach teaches
further comprising: a first heat spreader layer interposed between the first buried oxide layer and the passivation layer; and a second heat spreader layer interposed between the second buried oxide layer and the mold wafer. shield/heat sink layer 588 and under & overlying dielectric layers, spreads the localized heat/light energy of the topside anneal laterally and protects the underlying layers of interconnect metallization & dielectrics, such as in the acceptor wafer 510, from harmful temperatures or damage. [Bach para 0082]
Wu discloses a semiconductor package includes a substrate, a first three-dimensional integrated circuit structure on the substrate, and a second three-dimensional integrated circuit structure on the substrate, where the first three-dimensional integrated circuit structure may include a first interposer including a first semiconductor die, and a second semiconductor die on the first interposer, where the second three-dimensional integrated circuit structure may include a second interposer including a third semiconductor die, and a fourth semiconductor die on the second interposer, where the substrate may include an electrical routing configured to relay a signal from the second semiconductor die and a signal from the fourth semiconductor die.
Bach discloses a semiconductor device, the device including: a first substrate; a first metal layer disposed over the first substrate; a second metal layer disposed over the first metal layer; a first level including a plurality of transistors, the first level disposed over the second metal layer, where the plurality of transistors each include single crystal silicon; a third metal layer disposed over the first level; a fourth metal layer disposed over the third metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 200 nm alignment error; and a via disposed through the first level, where the via has a diameter of less than 450 nm, where the fourth metal layer provides a global power distribution, and where the device includes at least one power supply circuit
At the time of the invention it would have been obvious to one of ordinary skill in the art to combine Wu and Bach in the art of semiconductor manufacturing to device a process which applies a heat spreader to a IC chip substrate and or the host IC itself to create heat spreader surfaces between the passivation layer and and the buried oxide layer and a mold wafer as it is known that one of ordinary skill can combine known technologies to produce a heat spreader to dissipate heat from the IC
Regarding claim 3 Wu and Bach teaches claim 2 in addition Bach teaches wherein at least one of the first heat spreader layer and the second heat spreader layer comprises aluminum nitride (AlN), Aluminum Oxide (Al2O3), or a diamond-like coating. Shield/heat sink layer 588 may include materials with a high thermal conductivity greater than W/m-K, for example, copper (about 400 W/m-K), aluminum (about 237 W/m-K), Tungsten (about 173 W/m-K), Plasma Enhanced Chemical Vapor Deposited Diamond Like Carbon-PECVD DLC (about 1000 W/m-K), and Chemical Vapor Deposited (CVD) graphene (about 5000 W/m-K). Shield/heat sink layer 588 may be sandwiched and/or substantially enclosed by materials with a low thermal conductivity (less than 10 W/m-K), for example, silicon dioxide (about 1.4 W/m-K). [Bach para 0082]
Regarding claim 5 Wu teaches claim 4 in addition Wu does not teach but Bach teaches
wherein the porous silicon layer comprises first and second crystalline silicon end portions. the heat conducting layer closest to the second crystalline layer or oxide layer 580 may be constructed with a different material, [Bach para 0082]
Regarding claim 13 Wu teaches claim 11 in addition Wu does not teach but Bach teaches further comprising: forming a first heat spreader layer coupled to the first buried oxide layer; and forming a second heat spreader layer coupled to the second buried oxide layer. shield/heat sink layer 588 and under & overlying dielectric layers, spreads the localized heat/light energy of the topside anneal laterally and protects the underlying layers of interconnect metallization & dielectrics, such as in the acceptor wafer 510, from harmful temperatures or damage. [Bach para 0082]
Regarding claim 14 Wu and Bach teaches claim 13 in addition Bach teaches
wherein forming at least one of the first heat spreader layer and forming the second heat spreader layer comprises forming a layer of aluminum nitride (AlN), Aluminum Oxide (Al2O3), or a diamond-like coating. Shield/heat sink layer 588 may include materials with a high thermal conductivity greater than W/m-K, for example, copper (about 400 W/m-K), aluminum (about 237 W/m-K), Tungsten (about 173 W/m-K), Plasma Enhanced Chemical Vapor Deposited Diamond Like Carbon-PECVD DLC (about 1000 W/m-K), and Chemical Vapor Deposited (CVD) graphene (about 5000 W/m-K). Shield/heat sink layer 588 may be sandwiched and/or substantially enclosed by materials with a low thermal conductivity (less than 10 W/m-K), for example, silicon dioxide (about 1.4 W/m-K). [Bach para 0082]
Regarding claim 17 Wu teaches claim 16 in addition Wu does not teach but Bach teaches wherein the partially removed silicon layer comprises first and second crystalline silicon end portions. the heat conducting layer closest to the second crystalline layer or oxide layer 580 may be constructed with a different material, [Bach para 0082]
Claim(s) 7 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu and Tischler et al., US patent Application (20150221835), hereinafter Tischler
Regarding claim 7 Wu teaches claim 1 in addition Wu does not teach but Tischler teaches further comprising a heat pipe, and wherein the heat pipe comprises a first portion extending through the first integrated circuit, and a second portion extending at least partially into the second integrated circuit. additional elements may be incorporated, for example a heat spreader, heat pipe or a connector, or multiple dies may be stacked on top of each other, [Tischler para 0306]
Wu discloses a semiconductor package includes a substrate, a first three-dimensional integrated circuit structure on the substrate, and a second three-dimensional integrated circuit structure on the substrate, where the first three-dimensional integrated circuit structure may include a first interposer including a first semiconductor die, and a second semiconductor die on the first interposer, where the second three-dimensional integrated circuit structure may include a second interposer including a third semiconductor die, and a fourth semiconductor die on the second interposer, where the substrate may include an electrical routing configured to relay a signal from the second semiconductor die and a signal from the fourth semiconductor die.
Tischler discloses an electronic devices feature a polymeric binder, a frame defining an aperture therethrough, and a semiconductor die (e.g., a light-emitting or a light-detecting element) suspended in the binder and within the aperture of the frame.
At the time of the invention, it would have been obvious to one of ordinary skill in the art to combine Wu and Tischler in the art of semiconductor manufacturing to device a process which applies a heat pipe to a IC chip substrate and or the host IC itself to create heat spreader surfaces between the portions of the IC as it is known that one of ordinary skill can combine known technologies to produce a heat pipe to dissipate heat from the IC
Regarding claim 18 Wu teaches claim 11 in addition Wu does not teach but Tischler teaches further comprising forming a heat pipe, and wherein the heat pipe comprises a first portion extending through the plurality of first integrated circuits, and a second portion extending at least partially into the plurality of second integrated circuits. additional elements may be incorporated, for example a heat spreader, heat pipe or a connector, or multiple dies may be stacked on top of each other, [Tischler para 0306]
Claim(s) 8, 9, 19 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu and Zhang et al., US Patent Application (20240170425), hereinafter “Zhang”
Regarding claim 8 Wu teaches claim 1 in addition Wu does not teach but Zhang teaches further comprising a dielectric layer interposed between the first buried oxide layer and the passivation layer. forming a pad dielectric layer on the supplemental semiconductor layer in the core region and on the remaining portion of the first substrate in the periphery region; forming a plurality of pad structures embedded in the pad dielectric layer; forming a wiring layer on the pad dielectric layer to connect with the plurality of pad structures; and forming a passivation layer to cover the wiring layer. [Zhang para 0025]
Wu discloses a semiconductor package includes a substrate, a first three-dimensional integrated circuit structure on the substrate, and a second three-dimensional integrated circuit structure on the substrate, where the first three-dimensional integrated circuit structure may include a first interposer including a first semiconductor die, and a second semiconductor die on the first interposer, where the second three-dimensional integrated circuit structure may include a second interposer including a third semiconductor die, and a fourth semiconductor die on the second interposer, where the substrate may include an electrical routing configured to relay a signal from the second semiconductor die and a signal from the fourth semiconductor die.
Zhang discloses a Three-dimensional (3D) memory devices and fabricating methods thereof are disclosed. In certain aspects, a disclosed 3D memory device comprises a first semiconductor structure including a core region, a spacer region, and a periphery region, and a second semiconductor structure including a second periphery circuit on a substrate. The first semiconductor structure comprises a memory stack on a semiconductor layer in the core region, a first periphery circuit on the semiconductor layer in the periphery region, and a spacer structure in the spacer region to separate the memory stack and the first periphery circuit. The second semiconductor structure is connected to the first semiconductor structure
At the time of the invention, it would have been obvious to one of ordinary skill in the art to combine Wu and Zhang in the art of semiconductor manufacturing. Zhang uses a dielectric and passivation layer to protect the IC circuit and provide insulating to wirings passing thru the IC.
Regarding claim 9 Wu and Zhang teaches claim 8 in addition Zhang teaches further comprising metal wiring extending through the dielectric layer. forming a pad dielectric layer on the supplemental semiconductor layer in the core region and on the remaining portion of the first substrate in the periphery region; forming a plurality of pad structures embedded in the pad dielectric layer; forming a wiring layer on the pad dielectric layer to connect with the plurality of pad structures; and forming a passivation layer to cover the wiring layer. [Zhang para 0025]
Regarding claim 19 Wu teaches claim 11 in addition Wu does not teach but Zhang teaches further comprising forming a dielectric layer coupled to a bottom surface of the first buried oxide layer. forming a plurality of pad structures embedded in the pad dielectric layer; forming a wiring layer on the pad dielectric layer to connect with the plurality of pad structures; and forming a passivation layer to cover the wiring layer. [Zhang para 0025]
Regarding claim 20 Wu and Zhang teaches claim 19 in addition Zhang further comprising metal wiring extending through the dielectric layer. forming a plurality of pad structures embedded in the pad dielectric layer; forming a wiring layer on the pad dielectric layer to connect with the plurality of pad structures; and forming a passivation layer to cover the wiring layer. [Zhang para 0025]
Conclusion
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/ROBERT J MICHAUD/Examiner, Art Unit 2622