DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/15/2023 was filed and is in
compliance with provision of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters "400" and "340" have both been used to designate molding member.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-12, 14 and 19-20, as best understood, are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20210242101 A1) in view of Lu et al. (US 20200312770 A1).
Regarding claim 1, Kim et al. teaches a semiconductor package, comprising:
a substrate (102; Kim et al. Fig. 2B) including bonding pads (108; Kim et al. Fig. 2B) on an upper edge of the substrate;
a first semiconductor chip (110; Kim et al. Fig. 2B) on the substrate;
a second semiconductor chip (130; Kim et al. Fig. 2B) on the first semiconductor chip;
a plurality of bonding wires (134; Kim et al. Fig. 2B) configured to connect the second semiconductor chip to the bonding pads;
a dam structure (Da/Db; Kim et al. Fig. 2B) on the substrate between the first semiconductor chip and the bonding pads; and
a molding member (140; Kim et al. Fig. 2B) on the dam structure, the substrate, the first semiconductor chip, and the second semiconductor chip,
wherein the dam structure includes:
a first dam structure (Dam; Kim et al. Annotated Fig. 1) having a closed loop shape that extends around the first semiconductor chip.
Kim et al. does not teach a plurality of dam structures on the substrate between the first semiconductor chip and the bonding pads, a molding member on the plurality of dam structures, and does not teach wherein the plurality of dam structures include: a second dam structure between the first dam structure and the bonding pads.
Lu et al. teach in Figs. 1A-1G a plurality of dam structures (DP1/DP2) on the substrate 10 between the first semiconductor chip S1 and the bonding pads [B12(B1)]; and the plurality of dam structures include a second dam structure (LEFT DP1) between the first dam structure (right DP1) and the bonding pads [B11(B1)].
Kim et al and Lu et al. are analogous art because they both are directed to packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kim et al. with the specified features of Lu et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Kim by forming a plurality of dam structures on the substrate between the first semiconductor chip and the bonding pads, and to form a molding member on the plurality of dam structures, wherein the plurality of dam structures include: a second dam structure between the first dam structure and the bonding pads, as taught by Lu, the motivation being the multiple dam structures would be more effective in physically blocking underfill in reaching the edge of the substrate and the bonding pads. Kim et al. already teaches one dam structure is effective for this purpose. The dam structure is configured to prevent bonding pads from being covered by the underfill (Kim et al.; [0003]-[0005]).
Regarding claim 2, Kim et al. in view of Lu teaches the semiconductor package of claim 1, further comprising a plurality of inner connection members (116; Kim et al. Fig. 2B) between the first semiconductor chip and the substrate, the inner connection members configured to connect the first semiconductor chip to the substrate.
Regarding claim 3, Kim et al. in view of Lu teaches the semiconductor package of claim 1, further comprising an adhesion layer (136; Kim et al. Fig. 2B) between the first semiconductor chip and the second semiconductor chip.
Regarding claim 4, Kim et al. in view of Lu teaches the semiconductor package of claim 1, wherein the first semiconductor chip includes a Modem chip or logic chip, ([0028], Kim et al.) and the second semiconductor chip includes a memory chip ([0028], Kim et al.)
Regarding claim 5, Kim et al. in view of Lu teaches the semiconductor package of claim 4, wherein the first semiconductor chip has a first width (110; Kim et al. Annotated Fig. 2A) in a first direction, the second semiconductor chip has a second width (130; Kim et al. Annotated Fig. 2A) in the first direction, the second width being less than the first width (Kim et al. Fig. 2A), and
one sidewall of the second semiconductor chip is vertically aligned (Kim et al. Annotated Fig. 2A), with one sidewall of the first semiconductor chip.
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Kim et al. Annotated Fig. 2A
Regarding claim 6, Kim et al. in view of Lu teaches the semiconductor package of claim 1, wherein a dam structure includes a silicon-based polymer [0045].
Kim et al. does not explicitly teach the plurality of dam structures include a silicon-based polymer.
Lu et al. teaches the plurality of dam structures (DP1/DP2) include materials taught in [0021], which do not explicitly teach these are a silicon-based polymer.
Kim et al and Lu et al. are analogous art because they both are directed to packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kim et al. with the specified features of Lu et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to further modify Kim in view of Lu wherein the plurality of dam structures includes a silicon-based polymer as taught by Kim, since Kim generally teaches the dam structures can be made of a silicon-based polymer, the motivation being it is efficient to use same material for first and second dam structures, and also the silicon-based polymer dam is suitable to physically blocking underfill in reaching the edge of the substrate and the bonding pads.
Regarding claims 7-9, Kim et al. in view of Lu teaches the semiconductor package of claim 1.
Kim et al. further teaches the first dam structure has a height of about 13 μm to about 23 μm. (claim 12; the dam structure has a height of 18 μm or less, Kim et .al).
Kim et al. does not explicitly teach wherein each of the first dam structure and second dam structure has a cross-sectional width of about 80 μm to about 120 μm and the second dam structure has a height of about 13 μm to about 23 μm (claim 7); wherein an interval between the first dam structure and the second dam structure is in a range of about 100 μm to about 150 μm (claim 8); and wherein an interval between the second dam structure and one of the bonding pads is in a range of about 130 μm to about 180 μm (claim 9).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have each of the first dam structure and the second dam structure have a cross-sectional width of about 80 μm to about 120 μm, and the second dam structure have a height of about 13 μm to about 23 μm, wherein an interval between the first dam structure and the second dam structure is in a range of about 100 μm to about 150 μm; and wherein an interval between the second dam structure and one of the bonding pads is in a range of about 130 μm to about 180 μm, the motivation being these widths and heights would be suitable to prevent the underfill from entering the area of metallization near the edge of the semiconductor substrate.
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Furthermore, it has been held that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1980). Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc., 725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art.
Regarding claim 10, Kim et al. in view of Lu teaches the semiconductor package of claim 1, wherein the substrate includes:
a first region (First region R1; Kim et al. annotated Fig. 1) on which the bonding pads are present; and
a second region (Second region R2; Kim et al. annotated Fig. 1) on which the bonding pads are absent,
wherein the first dam structure extends across the first region and the second region,
and
wherein the first dam structure has a first width (First Width; Kim et al. Annotated Fig. 1) on the first region and a second width (Second Width; Kim et al. Annotated Fig. 1) on the second region, the second width being greater than the first width.
Furthermore Kim et al. annotated Fig 1. Illustrates the second region R2 as being wider than the first region R1, and although the drawing are not to scale, they may be relied upon for what they would reasonably teach one of ordinary skill in the art when interpreted in view of the specification. (MPEP 2125(II), In re Wright, 569 F.2d 1124, 1127-28, 193 USPQ 332, 335-36 (CCPA 1977)).
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Kim et al. Annotated Fig. 1
Regarding claim 11, Kim et al. in view of Lu et al. teaches the semiconductor package of claim 10.
Kim et al. does not teach wherein the second dam structure is on the first region and extends around a portion of the first dam structure.
Lu et al. does teach wherein the second dam structure (left DP1) is on the first region and extends around a portion of the first dam structure (Fig. 1G of Lu et al.).
Kim et al. and Lu et al. are analogous art because they both are directed to packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kim et al. with the specified features of Lu et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to further modify Kim et al. in view of Lu et al. wherein the second dam structure (left DP1) is on the first region and extends around a portion of the first dam structure as taught by Lu et al. (Fig. 1G of Lu et al.), the motivation being Lu et al. generally teaches the shape of a second dam structure between the first dam structure and the bonding pads can extends around a portion of a first dam structure and would be more effective in physically blocking underfill in reaching the edge of the substrate and the bonding pads.
Regarding claim 12, Kim et al.in view of Lu et al. teaches the semiconductor package of claim 10, wherein, on the first region, an interval between the first dam structure and the first semiconductor chip is in a range of about 150 μm to about 200 μm ([0021]; interval is 200-400 μm; Kim et al.).
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Furthermore, it has been held that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1980). Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc., 725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art.
Regarding claim 14, Kim et al. in view of Lu et al. teaches the semiconductor package of claim 1, further comprising an underfill pattern (120; Kim et al. Annotated Fig. 2A) inside the first dam structure and between the substrate and the first semiconductor chip,
wherein an edge (Edge of underfill; Kim et al. Annotated Fig. 2A) of the underfill pattern is between a lateral surface of the first semiconductor chip and a lateral surface of the first dam structure.
Regarding claim 19, Kim et al. teaches a semiconductor package, comprising:
a substrate (102; Kim et al. Fig. 2B) that includes bonding pads (108; Kim et al. Fig. 2B) and upper substrate pads (104; Kim et al. Fig. 2B) on a top surface of the substrate and includes lower substrate pads (106; Kim et al. Fig. 2B) on a bottom surface of the substrate;
a plurality of external connection members (150; Kim et al. Fig. 2B) bonded to the lower substrate pads;
a first semiconductor chip (110; Kim et al. Fig. 2B) on the substrate;
a plurality of inner connection members (116; Kim et al. Fig. 2B) configured to connect the first semiconductor chip to the substrate;
an underfill pattern (120; Kim et al. Fig. 2B) between the substrate and the first semiconductor chip;
a second semiconductor chip (130; Kim et al. Fig. 2B) on the first semiconductor chip;
an adhesion layer (136; Kim et al. Fig. 2B) between the first semiconductor chip and the second semiconductor chip;
a plurality of second chip pads (132; Kim et al. Fig. 2B) on an edge of the second semiconductor chip;
a dam structures on the substrate and between the first semiconductor chip and the bonding pads;
a plurality of bonding wires (134; Kim et al. Fig. 2B) configured to connect the second chip pads to the bonding pads; and
a molding member (140; Kim et al. Fig. 2B) on the dam structures, the substrate, the first semiconductor chip, and the second semiconductor chip,
wherein the dam structures include:
a first dam structure having a closed loop (Dam; Kim et al. Annotated Fig. 1) shape that extends around the first semiconductor chip.
Kim et al. does not teach a plurality of dam structures on the substrate between the first semiconductor chip and the bonding pads and does not teach a molding member on the plurality of dam structures, the plurality of dam structures includes a second dam structure between the first dam structure and the bonding pads.
Lu et al. teach in Figs. 1A-1G and the related text a plurality of dam structures (DP1/DP2) on the substrate 10 between the first semiconductor chip S1 and the bonding pads [B12(B1)]; and the plurality of dam structures include a second dam structure (LEFT DP1) between the first dam structure (right DP1) and the bonding pads [B11(B1)].
Kim et al. and Lu et al. are analogous art because they both are directed to packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kim et al. with the specified features of Lu et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Kim by forming a plurality of dam structures on the substrate between the first semiconductor chip and the bonding pads, and to form a molding member on the plurality of dam structures, wherein the plurality of dam structures include: a second dam structure between the first dam structure and the bonding pads as taught by Lu, the motivation being the multiple dam structures would be more effective in physically blocking underfill in reaching the edge of the substrate and the bonding pads. Kim et al. already teaches one dam structure is effective for this purpose. The dam structure is configured to prevent bonding pads from being covered by the underfill (Kim et al.; [0003]-[0005]).
However, Kim et al. and Lu et al. do not teach wherein an interval between the first dam structure and the second dam structure is in a range of about 100 μm to about 150 μm.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Kim et al. and Lu et al. to have an interval between the first dam structure and the second dam structure is in a range of about 100 μm to about 150 μm, the motivation being this interval would be suitable to prevent the underfill from entering the area of metallization near the edge of the semiconductor substrate.
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Furthermore, it has been held that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1980). Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc., 725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art.
Regarding claim 20, Kim et al. in view of Lu et al. teaches the semiconductor package of claim 19, wherein
the first dam structure has a height of about 13 μm to about 23 μm. (claim 12; the dam structure has a height of 18 μm or less, Kim et .al).
Kim et al. does not explicitly teach wherein the first dam structure has a cross-sectional width of about 80 μm to about 120 μm and the second dam structure has a cross-sectional width of about 130 μm to about 170 μm and height of about 15 μm to about 25 μm.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Kim et al. and Lu et al. to have the first dam structure have a cross-sectional width of about 80 μm to about 120 μm, and the second dam structure has a cross-sectional width of about 130 μm to about 170 μm and height of about 15 μm to about 25 μm, the motivation being these widths and heights would be suitable to prevent the underfill from entering the area of metallization near the edge of the semiconductor substrate.
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Furthermore, it has been held that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1980). Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc., 725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art.
Claim 13 and 15-18, as best understood, is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20210242101 A1). in view of Lu et al. (US 20200312770 A1). and further in view of Saeki (20080237895).
Regarding claim 13, Kim et al. in view of Lu et al. teaches the semiconductor package of claim 1.
Kim et al. also teaches further comprising an underfill pattern (120; Kim et al. Annotated Fig. 2A) inside the first dam structure and between the substrate and the first semiconductor chip,
wherein an edge of the underfill pattern (120; Kim et al. Fig. 2B) extends on a lateral surface and a top surface of the first dam structure.
Kim et al. in view of Lu et al. does not disclose an edge of the underfill pattern is between the first dam structure and the second dam structure.
Saeki teaches in Fig. 1A-1B an edge of the underfill pattern (15) is between the first dam structure (right 16) and the second dam structure (left 16).
Kim et al., Lu et al. and Saeki are analogous art because they all three are directed to packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kim et al. and Lu et al. with the specified features of Saeki because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to further modify Kim et al. in view of Lu et al. and further in view of Saeki so that an edge of the underfill pattern (15) is between the first dam structure (right 16) and the second dam structure (left 16), the motivation being it is well known in the art that underfill has a significant role in protecting the circuit components from moisture, dust, and corrosion and it is general practice to have underfill to improve performance in drop tests, reducing the risk of solder joint failure in connections near the edge of the substrate, to include any bonding pad near the edge of the substrate.
Regarding claim 15, Kim et al. teaches a semiconductor package, comprising:
a substrate (102; Kim et al. Fig. 2B) that includes bonding pads (108; Kim et al. Fig. 2B) on an upper edge of the substrate;
a first semiconductor chip (110; Kim et al. Fig. 2B) on the substrate;
an underfill pattern (120; Kim et al. Fig. 2B) between the substrate and the first semiconductor chip;
a second semiconductor chip (130; Kim et al. Fig. 2B) on the first semiconductor chip;
a plurality of bonding wires (134; Kim et al. Fig. 2B) configured to connect the second semiconductor chip to the bonding pads;
a dam structure (Da/Db; Kim et al. Fig. 2B) on the substrate and between the first semiconductor chip and the bonding pads; and
a molding member (140; Kim et al. Fig. 2B) on the dam structure, the substrate, the first semiconductor chip, and the second semiconductor chip,
wherein the dam structure include:
a first dam structure having a closed loop shape (Dam; Kim et al. Annotated Fig. 1) that extends around the first semiconductor chip; and
wherein the underfill pattern extends on a top surface and a lateral surface of the first dam structure. (120; Kim et al. Fig. 2B).
Kim et al. does not teach a plurality of dam structures on the substrate between the first semiconductor chip and the bonding pads, a molding member on the plurality of dam structures, and the plurality of dam structures includes a second dam structure between the first dam structure and the bonding pads, and wherein the underfill pattern contacts one lateral surface of the second dam structure.
Lu et al. teach in Figs. 1A-1G and the related text a plurality of dam structures (DP1/DP2) on the substrate 10 between the first semiconductor chip S1 and the bonding pads [B12(B1)]; and the plurality of dam structures include a second dam structure (LEFT DP1) between the first dam structure (right DP1) and the bonding pads [B11(B1)].
Kim et al and Lu et al. are analogous art because they both are directed to packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kim et al. with the specified features of Lu et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Kim by forming a plurality of dam structures on the substrate between the first semiconductor chip and the bonding pads, and to form a molding member on the plurality of dam structures, wherein the plurality of dam structures include: a second dam structure between the first dam structure and the bonding pads, as taught by Lu, the motivation being the multiple dam structures would be more effective in physically blocking underfill in reaching the edge of the substrate and the bonding pads. Kim et al. already teaches one dam structure is effective for this purpose. The dam structure is configured to prevent bonding pads from being covered by the underfill (Kim et al.; [0003]-[0005]).
Furthermore, Saeki teaches in Fig. 1A-1B, wherein the underfill pattern (15) contacts one lateral surface of the second dam structure (left 16).
Kim et al., Lu et al. and Saeki are analogous art because they all three are directed to packaging devices with underfill and bond pads and dam structures, and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kim et al. and Lu et al. with the specified features of Saeki because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to further modify Kim et al. in view of Lu et al. further in view of Saeki so that an underfill pattern (15) contacts one lateral surface of the second dam structure (left 16), the motivation being the second dam structure is provided to protect the underfill pattern from splitting out to the edge of the substrate so it is obvious to have the underfill pattern touching the lateral surface of the second dam structure.
Regarding claim 16, Kim et al. in view of Lu et al., further in view of Saeki teaches the semiconductor package of claim 15, wherein the substrate includes:
a first region (First region R1; Kim et al. annotated Fig. 1) on which the bonding pads are present; and
a second region (Second region R1; Kim et al. annotated Fig. 1) on which the bonding pads are absent,
wherein the first dam structure (Dam; Kim et al. Annotated Fig. 1) extends across the first region and the second region, and
wherein the first dam structure has a first width (First Width; Kim et al. Annotated Fig. 1) on the first region and a second width (Second Width; Kim et al. Annotated Fig. 1) on the second region, the second width being greater than the first width.
Even though Kim et al. does not explicitly teach the claimed widths, Kim et al. annotated Fig 1. Illustrates the second region R2 as being wider than the first region R1, and although the drawings are not to scale, they may be relied upon for what they would reasonably teach one of ordinary skill in the art when interpreted in view of the specification. (MPEP 2125(II), In re Wright, 569 F.2d 1124, 1127-28, 193 USPQ 332, 335-36 (CCPA 1977)).
Regarding claim 17, Kim et al. in view of Lu et al., further in view of Saeki teaches the semiconductor package of claim 16.
Kim et al. does not teach wherein the second dam structure is on the first region and extends around a portion of the first dam structure.
Lu et al. does teach wherein the second dam structure (left DP1) is on the first region and extends around a portion of the first dam structure (Fig. 1G of Lu et al.).
Kim et al., Lu et al. and Saeki are analogous art because all three are directed to packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kim et al., Lu et al. and Saeki further with the specified features of Lu et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to further modify Kim et al. in view of Lu et al. and Saeki wherein the second dam structure (left DP1) is on the first region and extends around a portion of the first dam structure as taught by Lu (Fig. 1G of Lu et al.), the motivation being Lu generally teaches the shape of a second dam structure between the first dam structure and the bonding pads can extends around a portion of a first dam structure and would be more effective in physically blocking underfill in reaching the edge of the substrate and the bonding pads.
Regarding claim 18, Kim et al. in view of Lu et al., further in view of Saeki teaches the semiconductor package of claim 16, wherein
on the first region (First region R1; Kim et al. annotated Fig. 1), the underfill pattern (120; Kim et al. Annotated Fig. 2A) extends on the top surface and the lateral surface of the first dam structure. and
on the second region (second region R1; Kim et al. annotated Fig. 1), the underfill pattern extends on the top surface and the lateral surface of the first dam structure (120; Kim et al. Fig. 2C).
However, Kim et al. does not teach on the first region, the underfill pattern contacts a lateral surface of the second dam structure.
Saeki teaches in Fig. 1A-1B an underfill pattern (15) contacts a lateral surface of the second dam structure (left 16).
Kim et al., Lu et al. and Saeki are analogous art because they all three are directed to packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kim et al. and Lu et al. and Saeki further with the specified features of Saeki because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Kim et al. in view of Lu et al. and Saeki, further in view of Saeki so that on the first region, the underfill pattern (15) contacts a lateral surface of the second dam structure (left 16), the motivation being the second dam structure in Lu et al. is provided to protect the underfill pattern from splitting out to the edge of the substrate so it is obvious to have the underfill pattern touching the lateral surface of the second dam structure as taught in Saeki.
Conclusion
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/R.B.C./Examiner, Art Unit 2811
/LYNNE A GURLEY/ Supervisory Patent Examiner, Art Unit 2811
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