DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
2. Claims 1-8 and 11-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lai et al. CN 115513140 A, a copy of which and a Machine Translation by USPTO-PE2E is attached, but the following rejections are based on a related US patent application which is published as U.S. Patent Application Publication 20230067311, which is of record.
Lai discloses in Figs. 1A-1B, para [27] (paragraph(s) [0027]), and other text a three-dimensional stacked Field Effect Transistor as claimed.
Referring to claim 1, the reference discloses a three dimensional (3D) stacked Field Effect Transistor (FET) comprising:
a back-side wiring layer including a first back-side power line (20B, para [29]) and a second back-side power line (142B, para [30]) each extending in a first direction (X direction);
a first FET (NMOS) on the back-side wiring layer;
a second FET (PMOS) over the first FET;
a front-side wiring layer over the second FET (PMOS), the front-side wiring layer extending in the first direction (X direction), and the front-side wiring layer including a front-side power line (20F) connected to the second back-side power line (142B) (para [30]);
a first through-electrode (MDLI, para [27]) connecting the first FET to the second FET (via the drains terminals of the first FET and the second FET, para [27]); and
a second through-electrode (VTB, para [30]) connecting the front-side power line (20F) to the second back-side power line (142B), wherein
the first FET (NMOS) and the second FET (PMOS) share a gate (150, para [26]) extending in a second direction (Y direction),
the second direction is perpendicular to the first direction, and
each of the first FET and the second FET include a source (not depicted) and a drain (not depicted) (connected to respective source/drain terminals 134n, 132n, 132p and 134p, para [27]) respectively on both sides of the gate (150) in the first direction, and a channel between the source and the drain and surrounded by the gate (para [26]).
Referring to claim 2, Lai further discloses that the channel has a Multi-Bridge Channel (MBC) structure (the channel (active region portion enclosed by the gate) comprising nano-wires, para [27]), and wherein the gate (150) has a gate all around (GAA) structure (as known in the pertinent art).
Referring to claim 3, Lai further discloses:
a lower contact portion (source terminal/via 132n/VB, para [27]) connecting the drain (the source, nor depicted) of the first FET (NMOS) to the first back-side power line (20B), the drain (the source) of the first FET being a first drain (a first source) and the drain of the second FET being a second drain;
an upper contact portion (source terminal/via 132p/VD, para [27]) connecting the source (not depicted) of the second FET (PMOS) to the front-side power line (20F), the source of the second FET being a second source and the source of the first FET being a first source;
a first source contact (drain terminal 134n, para [27]) extending in the second direction and connecting the first source (the first drain) of the first FET (NMOS) to the first through-electrode (MDLI); and
a second drain contact (drain terminal 134p, para [28]), extending in the second direction (Y direction) and connecting the second drain of the second FET to the first through electrode (MDLI).
Referring to claim 4, Lai further discloses that
the lower contact portion (132n/VB) comprises a first drain contact (source terminal 132n) and a first power via (VB),
the first drain contact (source terminal 132n) extends in the second direction (the Y direction) and is connected to the first drain (the first source) of the first FET (NMOS),
the first power via (VB) connects the first drain contact (132n) to the first back-side power line (20B), and
the upper contact portion (132p/VD) comprises a second source contact (source terminal 132p) and a second power via (VD),
the second source contact extends in the second direction (the Y direction) and is connected to the second source (the second source) of the second FET (PMOS), and
the second power via (VD) connects the second source contact (132p) to the front-side power line (20F).
Referring to claim 5, Lai further discloses that
the second source contact (132p) and the front-side power line (20F) partially overlap each other in a third direction (Z direction) such that a portion of the second source contact (132p) is spaced apart from a portion of the front-side power line (20F) in the third direction, the third direction is perpendicular to the first direction and the second direction, the second power via (VD) is between the portion of the second source contact (132p) and the portion of the front-side power line (20F).
Referring to claim 6, Lai further discloses that
the first drain contact (132n) and the second source contact (132p) overlap in a third direction (Z direction), the first source contact (134n) and the second drain contact (134p) overlap in the third direction (the Z direction), the first source contact (134n) is spaced apart from the first drain contact (132n) in the first direction (the X direction), and the second source contact (132p) is spaced apart from the second drain contact (134p) in the first direction (the X direction).
Referring to claim 7, Lai further discloses that
a conductivity type (n) of the first FET (NMOS, para [26]) differs from a conductivity type (p) of the second FET (PMOS, para [26]), and a position of the source (not depicted, connected to source terminal/contact 132n (para [27])) of the first FET (NMOS) is opposite a position of the drain (not depicted, connected to drain terminal/contact 134n (para [27])) of the first FET (the NMOS) in the first direction (the X direction), a position of the source (not depicted, connected to source terminal/contact 132p (para [27])) of the second FET is opposite a position of the drain (not depicted, connected to drain terminal/contact 134p (para [27])) of the second FET (the PMOS) in the first direction, the first FET and the second FET are parts of an inverter (100, Fig. 1A, such as cell C12, Figs. 9A, 9B, 12A, 12B, para [30, 64, 67]) in a unit cell of the 3D stacked FET, the unit cell (100, C12) is defined in the first direction (the X direction) by a region between up to ½ of each of two gates (of adjacent cells C11, C13, Fig. 9B) disposed on both sides of the gate (150, Fig. 1A, not depicted (the gate of cell C12) in Figs. 9B, 12B) in the first direction, and the unit cell is among a plurality of unit cells (C11-C16) repeatedly arranged in the first direction (the X direction).
Referring to claim 8, Lai further discloses:
power tap cells (PP1-PP3, Fig. 12A, 12B, para [67]) connected to the plurality of unit cells (C11-C16), wherein the power tap cells (PP1-PP3) are disposed for each set number of the plurality of unit cells (C11-C16) in the first direction (the X direction), and the second through-electrode (VTB) is in a corresponding power tap cell among the power tap cells (PP1-PP3).
Referring to claim 11 and using the same reference characters, interpretations, and citations as detailed above for claims 1 and 7 where applicable, the reference discloses a three dimensional (3D) stacked Field Effect Transistor (FET) comprising:
a back-side wiring layer including a first back-side power line (20B, Fig. 1A) and a second back-side power line (142B) each extending in a first direction (X direction);
a first FET (NMOS) on the back-side wiring layer;
a second FET (PMOS) over the first FET (NMOS), a conductivity type (p) of the second FET being different than a conductivity type (n) of the first FET (NMOS);
a front-side wiring layer (comprising 20F) over the second FET (PMOS), the front-side wiring layer (20F) extending in the first direction (the X direction) and including a front-side power line (20F) connected to the second back-side power line (142B, para [30]);
a first through-electrode (MDLI) connecting the first FET (NMOS) to the second FET (PMOS); and
a second through-electrode (VTB) connecting the front-side power line (20F) to the second back-side power line (142B, para [30]), wherein
the first FET (NMOS) and the second FET (PMOS)share a first gate (150),
the first FET and the second FET are in a unit cell (100, Fig. 1A, such as cell C12, Figs. 9A, 9B, 12A, 12B, para [30, 64, 67]) of the 3D stacked FET,
the unit cell (100, C12) corresponds to an area between up to one-half of each of two other gates (of adjacent cells C11, C13, Fig. 9B) on opposite sides of the first gate (150, Fig. 1A, not depicted (the gate of cell C12) in Figs. 9B, 12B) in the first direction (in the X direction) and between the first back-side power line (20B, Fig. 1A, part of BPN (para [67]), Figs. 9A, 12A) and the second back-side power line (142B, Fig. 1A, the other part of BPN, Figs. 9A, 12A) in a second direction (Y direction),
in the unit cell, the first gate (150; not depicted) is between the two other gates,
the second direction (the Y direction) is perpendicular to the first direction (the X direction),
the unit cell is among a plurality of unit cells (C11-C16) repeatedly arranged in the first direction (the X direction) and the second direction (the Y direction, see Figs. 9A, 9B, 10A, 10B).
Referring to claim 12, Lai further discloses that
the first back-side power line (20B) and the second back-side power line (142B) are alternately disposed in the second direction (the Z direction) (best viewed concurrently Figs. 1A and 9B), the first through-electrode (MDLI) is at a position in the unit cell over the second back-side power line (142B) in the second direction.
Referring to claim 13, Lai further discloses:
power tap cells (PP1-PP3, Figs. 12A, 12B, para [67]; not depicted in Figs 1A, 9A, 9B) connected to the plurality of unit cells (100, Fig. 1A; C11-C16, Figs. 12A, 12B), wherein the power tap cells (PP1-PP3) are arranged for each unit cell of a set number of the plurality of unit cells (C11-C16) in the first direction (the X direction), the second through-electrode (VTB, that is connected to backside power node BPN, para [67]) is in a corresponding power tap cell among the power tap cells (PP1-PP3).
Referring to claim 14, Lai further discloses that
each of the first FET (NMOS) and the second FET (PMOS) comprises a source (not depicted) and a drain (not depicted) (connected to respective source/drain terminals 134n, 132n, 132p and 134p, para [27]) respectively on both sides of the first gate in the first direction, and a channel between the source and the drain and surrounded by the first gate (150), the channel has a Multi-Bridge Channel (MBC) structure (the channel (active region portion enclosed by the gate) comprising nano-wires, para [27]), and the first gate (150) has a gate all around (GAA) structure (as known in the pertinent art).
Referring to claim 15, Lai further discloses:
a lower contact portion (source terminal/via 132n/VB, para [27]) connecting a first drain (a first source, not depicted) of the first FET (NMOS) to the first back-side power line (20B);
an upper contact portion (source terminal/via 132p/VD, para [27]) connecting a second source (not depicted) of the second FET (PMOS) to the front-side power line (20F);
a first source contact (drain terminal 134n, para [27]) extending in the second direction and connecting a first source (a first drain, not depicted) of the first FET (the NMOS) to the first through-electrode (MDLI); and
a second drain contact (drain terminal 134n, para [27]) extending in the second direction and connecting a second drain (not depicted) of the second FET (the PMOS) to the first through-electrode (MDLI).
Referring to claim 16, Lai further discloses that
the lower contact portion (132n/VB) comprises a first drain contact (source terminal 132n) and a first power via (VB),
the first drain contact (the source terminal 132n) extends in the second direction (the Y direction) and is connected to the first drain (the first source) of the first FET (the NMOS),
the first power via (VB) connects the first drain contact (132n) to the first back-side power line (20B),
the upper contact portion (132p/VD) comprises a second source contact (source terminal 132p) and a second power via (VD),
the second source contact (132p) extends in the second direction (the Y direction) and is connected to the second source (not depicted) of the second FET (the PMOS), and
the second power via (VD) connects the second source contact (132p) to the front-side power line (20F).
Referring to claim 17, Lai further discloses that
the first drain contact (132n) and the second source contact (132p) overlap in a third direction (the Z direction),
the first source contact (134n) and the second drain contact (134p) overlap in the third direction,
the first source contact (134n) is spaced apart from the first drain contact (132n) in the first direction (the X direction), and
the second source contact (132p) is spaced apart from the second drain contact (134p) in the first direction.
Referring to claim 18 and using the same reference characters, interpretations, and citations as detailed above for claims 1, 7 and 11 where applicable, the reference discloses a three dimensional (3D) stacked Field Effect Transistor (FET) comprising:
a back-side wiring layer including a first back-side power line (20B) and a second back-side power line (142b) each extending in a first direction (X direction);
a first FET (NMOS) on the back-side wiring layer;
a second FET (PMOS) over the first FET, a conductivity type (p) of the second FET being different than a conductivity type (n) of the first FET;
a front-side wiring layer (comprising 20F) over the second FET, the front-side wiring layer extending in the first direction (the X direction), and the front-side wiring layer including a front-side power line (20F) connected to the second back-side power line;
a first through-electrode (MDLI) connecting the first FET to the second FET; and
a second through-electrode (VTB) connecting the front-side power line (20F) to the second back-side power line (142B), wherein
the first FET and the second FET share a first gate (150),
the first FET and the second FET are in a unit cell (100, Fig. 1A, such as cell C12, Figs. 9A, 9B, 12A, 12B, para [30, 64, 67]) of the 3D stacked FET,
the unit cell (100, C12) corresponds to an area between up to one-half of each of two other gates (of adjacent cells C11, C13, Fig. 9B) on opposite sides of the first gate (150, Fig. 1A, not depicted (the gate of cell C12) in Figs. 9B, 12B) in the first direction and between the first back-side power line (20B, Fig. 1A, part of BPN (para [67]), Figs. 9A, 12A) and the second back-side power line (142B, Fig. 1A, the other part of BPN, Figs. 9A, 12A) in a second direction (Y direction),
the second direction is perpendicular to the first direction,
in the unit cell, the first gate (150; not depicted) is between the two other gates,
each of the first FET and the second FET include a source (not depicted) and a drain (not depicted) (connected to respective source/drain terminals 134n, 132n, 132p and 134p, para [27]) respectively on both sides of the first gate (150) in the first direction, and a channel between the source and the drain and surrounded by the gate (para [26]).
Referring to claim 19, Lai further discloses:
power tap cells (PP1-PP3, Figs. 12A, 12B, para [67]; not depicted in Figs 1A, 9A, 9B), wherein
the first back-side power line (20B) and the second back-side power line (142B) are alternately disposed in the second direction (the Z direction) (best viewed concurrently Figs. 1A and 9B),
the first through-electrode (MDLI) is at a position in the unit cell over the second back-side power line (142B) in the second direction,
the unit cell (100, C12) is among a plurality of unit cells (C11-C16),
the power tap cells (PP1-PP3) are arranged for each unit cell of a set number in the first direction among the plurality of unit cells (C11-C16), and
the power tap cells (PP1-PP3) each include the second through-electrode (VTP, see Fig. 12A).
Referring to claim 20, Lai further discloses:
a first drain contact (source terminal 132n, para [27]) extending in the second direction (the Y direction), the first drain contact (132n) being connected to the drain (the source, not depicted) of the first FET (the NMOS), the drain of the first FET being a first drain and the drain of the second FET being a second drain;
a first power via (VB, para [27]) connecting the first drain contact (132n) to the first back-side power line (20B);
a second source contact (source terminal 132p, para [27]) extending in the second direction, the second source contact (132p) being connected to the source (not depicted) of the second FET (the PMOS), the source of the second FET being a second source and the source of the first FET being a first source;
a second power via (VD, para [27]) connecting the second source contact (132p) to the front-side power line (20F);
a first source contact (drain terminal 134n, para [27]) extending in the second direction and connecting the first source (the first drain, not shown) of the first FET to the first through-electrode (MDLI); and
a second drain contact (drain terminal 134p, para [27]) extending in the second direction and connecting the second drain (the second drain, not shown) of the second FET (the PMOS) to the first through electrode (MDLI).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. §103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claim 10 is rejected under 35 U.S.C. §103 as being unpatentable over Lai et al. CN 115513140 A, a copy of which and a Machine Translation by USPTO-PE2E is attached, but the following rejections are based on a related US patent application which is published as U.S. Patent Application Publication 20230067311, which is of record.
Referring to claim 10, Lai further discloses that the second through-electrode (VTB) is connected to the front-side power line (20F) through a third power via (VD, para [27]), which meets the claim limitation “the second through-electrode is directly connected to the front-side power line or the second through-electrode is connected to the front-side power line through a third power via”. Although Lai does not specifically disclose dimensions as claimed, the claimed dimensions (“wherein the second through-electrode has a structure in which a front-side side is wide or a back-side side is wide”) will not support the patentability of subject matter encompassed by the prior art (Lai discloses that the second through-electrode CTB is for connecting the front power line 20F to the backside power line 142B, para [31], which signifies that the second through-electrode VTB should have a structure in which a front-side side is wide or a back-side side is wide to supply enough power to the 3D stacked FET) unless there is evidence indicating such dimensions are critical. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation"; MPEP 2144.05.
Allowable Subject Matter
4. Claim 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for the indication of allowable subject matter: The cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to teach or render obvious a three dimensional (3D) stacked Field Effect Transistor (FET) with all limitations as recited in claim 9, which may be characterized in that the corresponding power tap cell includes Single Diffusion Breaks (SDBs) extending in the second direction (and) being on both sides of the second through-electrode in the first direction.
Conclusion
5. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TU TU V HO whose telephone number is (571)272-1778. The examiner can normally be reached on Monday to Thursday 6:30 - 15:00, Monday through Thursday.
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02-24-2026
/TU-TU V HO/Primary Examiner, Art Unit 2818