Prosecution Insights
Last updated: October 27, 2026
Application No. 18/510,210

APPLICATION PROGRAMMING INTERFACE TO PROVIDE COMPILER OPTIONS TO PERFORM TENSOR OPERATIONS

Non-Final OA §103
Filed
Nov 15, 2023
Priority
Nov 09, 2023 — GR 20230100930
Examiner
WHEATON, BRADFORD F
Art Unit
2193
Tech Center
2100 — Computer Architecture & Software
Assignee
NVIDIA Corporation
OA Round
3 (Non-Final)
61%
Grant Probability
Moderate
3-4
OA Rounds
11m
Est. Remaining
73%
With Interview

Examiner Intelligence

Grants 61% of resolved cases
61%
Career Allowance Rate
244 granted / 398 resolved
+6.3% vs TC avg
Moderate +11% lift
Without
With
+11.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 11m
Avg Prosecution
17 currently pending
Career history
433
Total Applications
across all art units

Statute-Specific Performance

§101
18.5%
-21.5% vs TC avg
§103
68.1%
+28.1% vs TC avg
§102
2.1%
-37.9% vs TC avg
§112
8.9%
-31.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 398 resolved cases

Office Action

§103
DETAILED ACTION Claims 1-20 are pending in the current application. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 8/27/26 has been entered. Response to Arguments Applicant’s arguments, see Remarks, filed8/27/26, with respect to the rejection(s) of claim 1 under 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new grounds of rejection is made in view of Brady et al. (Pub. No. US 2019/0392296 A1) [0049] lines 1-15, [0059] lines 1-24, [0073] lines 1-15 and [0082] lines 11-19 that shows API that can specify which compiler algorithms to use/perform specific features/operations that can be associated/correspond with managing allocation of memory where memory allocation includes tensor data and thus viewed as indicating type of tensor operations to perform with specific compiler algorithm, compiler options for how compilation is performed, this is seen through the configuration API that can receive association compilation descriptor file as input parameters where the compilation descriptor identifies algorithm to use and other additional compilation configuration parameters including operator model that represent tensors and associated operations where Chowdhury [0184] lines 1-9, [0186] lines 1-7, [0187] lines 1-13, [0188] lines 1-4 and [0194] lines 1-11 that shows the specifics of API call inputs can include specific selection of compiler option to use in operation and thus together show wherein the API call includes one or more input parameters to indicate one or more tensor operations to be performed and to indicate one or more of a plurality of identified compiler options, wherein at least one compiler option corresponds to a respective one of the one or more tensor operations and specifies how code for the respective tensor operation is to be compiled. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-2, 5, 7-9, 12, 14-16 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chowdhury et al. (Pub. No. US 2023/0205559 A1) and further in view of Brady et al. (Pub. No. US 2019/0392296 A1). As to claims 1, 8 and 15, Chowdhury discloses one or more processors, comprising: circuitry to, in response to an application programming interface (API) call, cause one or more operations to be performed using one or more tensors based, in part, on one or more of a plurality of identified compiler options, wherein the API call includes one or more input parameters to indicate one or more of a plurality of identified compiler options, wherein at least one compiler option and specifies how code is to be compiled (Chowdhury [0023] lines 1-6, [0025] lines 2-10, [0054] lines 1-3, [0055] lines 1-14, [0060] lines 1-14, [0184] lines 1-9, [0186] lines 1-7, [0187] lines 1-13, [0188] lines 1-4 and [0194] lines 1-11; which shows that inputs to the API, viewed as type of API call, can indicate specific compiler options, JIT compile selection as part of build options input into the API thus viewed as selected from a plurality of options, to be performed and based on that input where the API call can also targeted kernel source associated with GPU and its associated functionality/features where GPU includes resources for operations it can perform include tensor cores designed to perform tensor/matrix operations thus viewed as the API call instruction being able to cause GPU tensor based operations to be performed associated with the target GPU with tensor functions/features for execution performed by the specific build option compiler selected for the build thus type of compiler options that specifies how code is to be compiled). Chowdhury does not specifically disclose the specifics of wherein the API call includes one or more input parameters to indicate one or more tensor operations to be performed and to indicate one or more of a plurality of identified compiler operation, wherein at least one compiler option corresponds to a respective one of the one or more tensor operations and specifies how code for the respective tensor operation is to be compiled. However, Brady the specifics of wherein the API call includes one or more input parameters to indicate one or more tensor operations to be performed and to indicate one or more of a plurality of identified compiler operation, wherein at least one compiler option corresponds to a respective one of the one or more tensor operations and specifies how code for the respective tensor operation is to be compiled (Brady [0049] lines 1-15, [0059] lines 1-24, [0073] lines 1-15 and [0082] lines 11-19; that shows the specifics of an API that can specify which compiler algorithms to use/perform specific features/operations that can be associated/correspond with managing allocation of memory where memory allocation includes tensor data indicating type of tensor operations to perform with specific compiler algorithm and thus viewed as showing API call includes input/parameters for specific compiler option/algorithm to be used indicating how the associated data is to be compiled, where this is indicated through the received compilation descriptor file/input/parameter information the API receives, where the descriptor file identifies algorithm to use and other additional compilation configuration parameters including operator model that represent tensors and associated operations thus viewed as showing input/parameters for the API call include specific/identified compiler option/algorithm to use associated with specific/respective tensor operations identified in the operator model information and thus together with the teachings of Chowdhury above showing the specifics of the identified compiler options to be used to compile that is indicated as a parameter in the API that specifies how code/data is to be compiled can together be viewed as showing the specifics of wherein the API call includes one or more input parameters to indicate one or more tensor operations to be performed and to indicate one or more of a plurality of identified compiler operation, wherein at least one compiler option corresponds to a respective one of the one or more tensor operations and specifies how code for the respective tensor operation is to be compiled) Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Brady showing the specifics of an API for specifying specified parameters including compiler algorithm options and operator model associated with tensor operations into the API call for building and performing operations of Chowdhury for the purpose of increasing adaptability of the API to address and respond to additional and respond to additional specific information, as taught by Brady [0073] lines 1-15 and [0082] lines 11-19. As to claims 2, 9 and 16 Chowdhury discloses wherein the one or more of a plurality of identified compiler options indicated by the API call is a just-in-time compiling (Chowdhury [0187] lines 1-13; which shows that the API input includes build options that can include/identify JIT compiler selection, viewed as showing the compiler options indicated/implemented by the API include JIT/just in time compiling option/selection). As to claims 5, 12 and 19 Chowdhury discloses wherein the circuity is to cause the one or more operations to be performed using the one or more tensors based at least on one or more planning selection (Chowdhury [0054] lines 1-3, [0055] lines 1-14, [0060] lines 1-14, [0184] lines 1-9, [0186] lines 1-7, [0187] lines 1-13, [0188] lines 1-4 and [0194] lines 1-11; which shows that API input information can include compiler selection options, and other custom options and options for address of where to write of pointer to the generated kernel binary for the GPU that can be associated with and perform tensor/matrix operations, viewed as type of selection from the options for the plan for the associated API operations and associated GPU with tensor/matrix operations to be performed),. As to claims 7, 14 and 20 Chowdhury discloses wherein the circuity is to cause the one or more operations to be performed using the one or more tensors responds by causing one or more tensor operations to be just-in-time compiled and stored in a non-transitory machine readable medium (Chowdhury [0023] lines 1-6, [0054] lines 1-3, [0055] lines 1-14, [0060] lines 1-14, [0184] lines 1-9, [0186] lines 1-7, [0187] lines 1-13, [0188] lines 1-4 and [0194] lines 1-11, [0213] lines 1-5 and [0214] lines 1-19; which shows is response to the API build option selection of JIT the associated kernel source from the GPU, that can perform functions/operations with tensor/matrix usage, thus the tensor/matrix operations that are viewed as part of the kernel source of the GPU that performs the tensor/matrix functions/operations would also be JIT compiled as part of the kernel source being JIT compiled, where the generated compiled binary for the kernel source, including the tensor/matrix operations, are written to a specific address, viewed as memory address, where the embodiment of the invention can be carried out on using code and data stored on one or more electronic devices that can include non-transitory computer machine readable storage, thus viewed as being able to write and store the JIT compiled kernel source that includes the tensor/matrix operations in a non-transitory machine readable medium). Claims 3-4, 6, 10-11, 13 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Chowdhury and Brady as applied to claims 1, 8 and 15 above, and further in view of Majcher et al. (Pub. No. US 2021/0256092 A1). As to claims 3, 10 and 17 Chowdhury as modified by Brady does not specifically disclose wherein the circuity is to cause the one or more operations to be performed using the one or more tensors based at least on one or more tensor operation descriptors. However, Majcher discloses wherein the circuity is to cause the one or more operations to be performed using the one or more tensors based at least on one or more tensor operation descriptors (Majcher [0060] lines 4-10 and [0063] lines 1-6; which shows the specifics that API calls to perform matrix/tensor multiply operations can include operation description information, viewed as tensor operation descriptors). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Majcher showing the specifics of the API call operation being performed include addition description information for the operation, into the API input configuration to perform tensor operations of Chowdhury as modified by Brady for the purpose of being able to provide additional information to improve the determination of the appropriate algorithm for a given matrix operation, as taught by Majcher [0002] lines 3-6 and [0052] lines 7-22. As to claims 4, 11 and 18 Chowdhury as modified by Brady does not specifically disclose, however, Majcher discloses wherein the circuity is to cause the one or more operations to be performed using the one or more tensors based at least on one or more tensor data identification (Majcher [0058] lines 5-18, [0060] lines 4-10 and [0063] lines 1-6; which shows that parameters/attributes for API call for matrix/tensor operations can include input matrices information, viewed as type of tensor data identification). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Majcher showing the specifics of the API call operation being performed include addition description information for the operation, into the API input configuration to perform tensor operations of Chowdhury as modified by Brady for the purpose of being able to provide additional information to improve the determination of the appropriate algorithm for a given matrix operation, as taught by Majcher [0002] lines 3-6 and [0052] lines 7-22 As to claims 6 and 13 Chowdhury as modified by Brady does not specifically disclose, however, Majcher discloses wherein the circuity is to cause the one or more operations to be performed using the one or more tensors based at least on one or more operation parameters (Majcher [0058] lines 5-18, [0060] lines 4-10 and [0063] lines 1-6; which shows the specifics that API calls to perform matrix/tensor multiply operations can include parameters that define aspects of a matrix/tensor multiplication operation, viewed as type of operation parameter). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Majcher showing the specifics of the API call operation being performed include addition description information for the operation, into the API input configuration to perform tensor operations of Chowdhury as modified by Liu for the purpose of being able to provide additional information to improve the determination of the appropriate algorithm for a given matrix operation, as taught by Majcher [0002] lines 3-6 and [0052] lines 7-22 Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADFORD F WHEATON whose telephone number is (571)270-1779. The examiner can normally be reached Monday-Friday 8:00-5:00 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chat Do can be reached at 571-272-3721. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BRADFORD F WHEATON/Examiner, Art Unit 2193
Read full office action

Prosecution Timeline

Show 3 earlier events
Jan 15, 2026
Applicant Interview (Telephonic)
Jan 20, 2026
Response Filed
Apr 28, 2026
Final Rejection mailed — §103
Jul 28, 2026
Examiner Interview Summary
Jul 28, 2026
Applicant Interview (Telephonic)
Aug 27, 2026
Request for Continued Examination
Sep 03, 2026
Response after Non-Final Action
Oct 01, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
61%
Grant Probability
73%
With Interview (+11.4%)
3y 11m (~11m remaining)
Median Time to Grant
High
PTA Risk
Based on 398 resolved cases by this examiner. Grant probability derived from career allowance rate.

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