DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in the application.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement(s) (IDS), Form PTO-1449, filed 15 November 2023. The information therein was considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
►Claim(s) 1, 5, 7, 11 and 13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mizuno (US 2007/0152307).
Re: independent claim 1, Mizuno discloses in fig. 1 an integrated circuit (IC) comprising: a first metal layer (11) that provides a signal layer [0043]; and a second metal layer (12) spaced apart from the first metal layer (11) by a gap, the second metal layer providing a ground plane [0043], wherein a meshed signal line (11) comprising one or more holes (13) is disposed in the first metal layer, the meshed signal line (11) being configured to transmit a received signal between circuits on the IC.
Re: claim 5, Mizuno discloses in fig. 1 the IC of claim 1, wherein the ground plane (12) forms an upper ground plane (fig. 1 upside down) with the second metal layer (12) being located above the first metal layer (11) and wherein the upper ground plane (12) overlaps the meshed signal line (11).
Re: claim 7, Mizuno discloses in fig. 1 the IC of claim 5, wherein the upper ground plane (12) comprises a solid continuous structure (fig. 1).
Re: claim 11, Mizuno discloses in fig. 1 the IC of claim 1, wherein the ground plane (12) forms a lower ground plane with the second metal layer being located below the first metal layer (11) and wherein the lower ground plane (12) overlaps the meshed signal line (11).
Re: claim 13, Mizuno discloses in fig. 1 the IC of claim 11, wherein the lower ground plane (12) comprises a solid continuous structure (fig. 1).
►Claim(s) 1, 4-6, 8-9 and 11-12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US 2020/0013714) (hereinafter, “Lin”).
Re: independent claim 1, Lin discloses in fig. 9E an integrated circuit (IC) comprising: a first metal layer (M0) that provides a signal layer (1022); and a second metal layer (M1, MX) spaced apart from the first metal layer (M0) by a gap (fig. 6C), the second metal layer (M1, MX) providing a ground plane (1020, 1024), wherein a meshed signal line (1022) comprising one or more holes is disposed in the first metal layer, the meshed signal line being configured to transmit a received signal between circuits on the IC.
Re: claim 4, Lin discloses in fig. 9E the IC of claim 1, wherein bump bonds or posts (V0, V1, V2 in fig. 6C) coupling the first metal layer to the second metal layer define the gap.
Re: claim 5, Lin discloses in fig. 9E the IC of claim 1, wherein the ground plane forms an upper ground plane (M1, 1020) with the second metal layer being located above the first metal layer (M0) and wherein the upper ground plane overlaps the meshed signal line (fig. 6C).
Re: claim 6, Lin discloses in fig. 9E the IC of claim 5, wherein the upper ground plane (1020) is a meshed upper ground plane comprising one or more holes aligned with the one or more holes of the meshed signal line (1022).
Re: claim 8, Lin discloses in fig. 9E the IC of claim 5, furthermore comprising a third metal layer (MX) spaced apart from the first metal layer (M0) by a gap (fig. 6C), the third metal layer (MX) providing a lower ground plane (1024) with the third metal layer (MX) being located below the first metal layer (M0) and wherein the lower ground plane overlaps the meshed signal line (fig. 6C).
Re: claim 9, Lin discloses in fig. 9E the IC of claim 8, wherein the lower ground plane (1024) is a meshed lower ground plane comprising one or more holes aligned with the one or more holes of the meshed signal line (1022).
Re: claim 11, Lin discloses in fig. 9E the IC of claim 1, wherein the ground plane forms a lower ground plane (1024) with the second metal layer (MX) being located below the first metal layer (M0) and wherein the lower ground plane overlaps the meshed signal line (fig. 6C).
Re: claim 12, Lin discloses in fig. 9E the IC of claim 11, wherein the lower ground plane (1024) is a meshed lower ground plane comprising one or more holes aligned with the one or more holes of the meshed signal line (1022).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mizuno (US 2007/0152307) or Lin et al. (US 2020/0013714) (hereinafter, “Lin”) in view of Tanahashi et al. (US 6,184,477) (hereinafter, “Tanahashi”).
Re: claim 3, Mizuno and Lin independently disclose the IC of claim 1.
Mizuno and Lin do not disclose expressly wherein a dielectric layer disposed between the first metal layer and the second metal layer form the gap.
Tanahashi discloses in fig. 2 a dielectric layer (I2) disposed between a first metal layer (G1) and a second metal layer (S1) form the gap.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to separate the first metal layer from the second metal layer with a dielectric disposed therebetween since it is common and well known in the art to insulate adjacent metal layers from each other to avoid interference as exemplified by Tanahashi.
Re: claim 14, Mizuno and Lin independently disclose the IC of claim 1.
Mizuno and Lin do not disclose expressly wherein the first metal layer and the second metal layer are formed from superconductor materials.
Tanahashi discloses wherein a first metal layer and a second metal layer are formed from superconductor materials (col 17 ll. 38-43).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the first metal layer and the second metal layer from superconducting materials for the purpose of reducing the resistance so that electric signals can be propagated without attenuation as taught by Tanahashi.
Allowable Subject Matter
Claims 15-20 are allowed.
Claims 2 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record fails to teach the claimed limitations in combination namely, as recited in independent claim 15, an electronic device comprising: a first metal layer that provides a signal layer; and a second metal layer spaced apart from the first metal layer by a gap, the second metal layer providing a meshed ground plane; wherein a meshed signal line comprising one or more holes is disposed in the first metal layer, the meshed signal line being configured to transmit a received signal between circuits of the electronic device; and wherein dimensions of the one or more holes of the meshed signal line are smaller than a wavelength of the received signal transmitted through the meshed signal line; and as recited in claim 2, the IC of claim 1, wherein dimensions of the one or more holes of the meshed signal line are smaller than a wavelength of the received signal transmitted through the meshed signal line; and as recited in claim 10, the IC of claim 8, wherein the lower ground plane comprises a solid continuous structure.
Conclusion
The examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. When responding to this office action, applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALLISON BERNSTEIN whose telephone number is (571)272-9011. The examiner can normally be reached M-F 8AM-5PM.
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/ALLISON BERNSTEIN/Primary Examiner, Art Unit 2824 3/20/2026