DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note by the Examiner
For clarity, references to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and examiner explanations for 102 &/or 103 rejections are provided in parenthesis.
Election/Restrictions
Applicant’s election without traverse of Species III, drawn to claims 1-2, in the reply filed on 05/07/2026 is acknowledged.
Claims withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention or species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 05/07/2026.
Claim Objections
Claim 1 is objected to because of the following informalities: in line 10 of the claims, “wherein” should be added before “the field insulating film thicker than the gate insulating film” and “is” should be added in between “film” and “thicker” in order to make grammatical sense. In line 16 of the claims, a semicolon should replace the comma in “connected, a shoulder portion” in order to make grammatical sense. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Sugawara et al. (Pub. No.: US 20210135002 A1), hereinafter as Sugawara, in view of Onozawa (Pub. No.: JP 2001358338 A), further in view of Niimura et al. (Pub. No.: US 20240186407 A1), hereinafter as Niimura.
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Image A.1: closeup of Sugawara Fig. 9D, showcasing gate pull-up portion and end portion of trench
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Image A.2: closeup of Sugawara Fig. 9D, showcasing shoulder, sidewall, and bottom portions of trench
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Image B: closeup of Onozawa Fig. 1, showcasing shoulder, sidewall, and bottom portions of trench 5
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Image C: closeup of Onozawa Fig. 1, showcasing gate pull-up portion
With regards to claim 1, Sugawara teaches a semiconductor device (see Sugawara Fig. 9 and Sugawara [0097], Embodiment 4) comprising: a semiconductor layer (see Sugawara Fig.1, semiconductor layer 2; see Sugawara [0097] and [0022]) in which an active region (see Sugawara Fig.1, active region 20; see Sugawara [0097] and [0019]) in which a semiconductor element (see Sugawara [0022]: “Although the present invention takes the example of the case where the semiconductor device is an MOSFET, the semiconductor device may be an IGBT.”) is formed; a trench (see Sugawara Fig.9C&9D, gate trench 6; see Sugawara [0097] and [0020]) formed in the semiconductor layer in the active region (see Sugawara Fig.9C&9D); a gate insulating film (see Sugawara Fig.9C&9D, gate insulating film 7; see Sugawara [0097] and [0028]) formed on an inner surface of the trench (see Sugawara Fig.9C&9D); a gate electrode (see Sugawara Fig.9C&9D, gate electrode 8; see Sugawara [0097] and [0028]) provided on the gate insulating film and embedded in the trench (see Sugawara Fig.9C&9D); a field insulating film (see Sugawara Fig.9C&9D, field insulating film 17; see Sugawara [0097]) formed on the semiconductor layer (see Sugawara Fig.9C&9D), wherein the field insulating film thicker is than the gate insulating film (see Sugawara [0099]: “Then, as illustrated in FIGS. 9(c) and 9(d), the field insulating film 17 having a greater film thickness than the gate insulating film 7 is formed on the bottom inside the terminal trench 16,”); a gate pad (see Sugawara Fig.9C&9D, gate pad 33; see Sugawara [0097] and [0038]) formed on the field insulating film (see Sugawara Fig.9C); and a gate lead-out wiring line (see Sugawara Fig.9C&9D, gate line 18; see Sugawara [0097] and [0038]) connecting the gate pad and the gate electrode (see Sugawara Fig.9A, where gate line 18 intersects both cross-sectional views thus connecting the gate pad 33 in Fig. 9C to the gate electrode 8 in Fig. 9D.), wherein in a gate pull-up portion (see Image A.1, pull-up portion) being an end portion of the trench (see Image A.1, end portion) corresponding to a place where the gate lead-out wiring line and the gate electrode in the trench are connected (see Image A.1 and Sugawara Fig.9C&9D), and the gate lead-out wiring line is formed on the field insulating film (see Sugawara Fig.9C&9D); and a shoulder portion (see Image A.2, shoulder portion), a sidewall portion (see Image A.2, sidewall portion), and a bottom portion (see Image A.2, bottom portion) of the trench are defined.
Sugawara’s Embodiment 4 does not teach a withstand voltage holding region outside the active region are defined.
However, a variation of Sugawara’s Embodiment 1 (see Sugawara Fig. 3 and Sugawara [0046]) teaches a withstand voltage holding region (see Sugawara Figs. 3B-3D, p-type terminal field relieving layer 36; see Sugawara [0046]) outside an active region (see Sugawara Fig.1, active region 20; see Sugawara [0046] and [0019]) are defined (see Sugawara Figs. 1 and 3B-3D).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to include the withstand voltage holding region taught by Sugawara’s Embodiment 1 variant in the semiconductor device of Sugawara’s Embodiment 4 in order to “[suppress] an avalanche breakdown and further improving the withstand voltage of the semiconductor device” (see Sugawara [0049]).
Sugawara does not teach a shoulder portion, a sidewall portion, and a bottom portion of the trench are covered with the field insulating film, and wherein in the gate pull-up portion, a thickness of the field insulating film covering the shoulder portion, the sidewall portion, and the bottom portion of the trench is equivalent to or larger than a thickness of the field insulating film under the gate pad.
Onozawa teaches a shoulder portion (see Image B, shoulder portion), a sidewall portion (see Image B, sidewall portion), and a bottom portion (see Image B, bottom portion) of a trench (see Onozawa Fig. 1, trench 5; see Onozawa [0017]) are covered with a field insulating film (see Onozawa Fig. 1, field oxide film 12 and gate oxide film 3a; see Onozawa [0017] and [0018]), and wherein in a gate pull-up portion (see Image C, pull-up portion), the field insulating film covering the shoulder portion, the sidewall portion, and the bottom portion of the trench has a thickness (see Onozawa [0018]: “the thickness of the gate oxide film 3a at the trench terminal portion is about the 1500nm.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the field insulating film of Sugawara with the field insulating film taught by Onozawa in order to further improve withstand voltage and prevent breakdown of the field insulating film by extending the field insulating film down into the trench (see Onozawa [0013]: “The electric field applied to the oxide film of the terminal part is reduced by forming an insulating film thicker than that of the center part between the terminal part of the stripe trench and the third electrode.”)
However, the combined device of Sugawara and Onozawa do not teach that a thickness of the field insulating film covering the shoulder portion, the sidewall portion, and the bottom portion of the trench is equivalent to or larger than a thickness of the field insulating film under the gate pad.
Niimura teaches a field insulating film (see Niimura Figs. 1&2, field oxide film 20; see Niimura [0044]) under a gate pad (see Niimura Figs. 1, gate metal electrode 13; see Niimura [0044]) with a thickness (see Niimura Figs. 2, remaining thickness h2; and see Niimura [0049]: “A remaining thickness h2 of portions of the contact holes 121 at the bottoms thereof may be in a range of 265 nm to 296 nm.”).
By defining the thickness of the field insulating film of the combined device of Sugawara and Onozawa with the range taught by Niimura, the combined device of Sugawara, Onozawa, and Niimura teaches a thickness (about 1500nm, see Onozawa [0018]) of the field insulating film (see Onozawa Fig. 1, field oxide film 12 and gate oxide film 3a) covering the shoulder portion (see Image B, shoulder portion), the sidewall portion (see Image B, sidewall portion), and the bottom portion (see Image B, bottom portion) of the trench (see Sugawara Fig.9C&9D, gate trench 6) is equivalent to or larger than a thickness (a range of 265 nm to 296 nm, see Niimura [0049]) of the field insulating film (see Sugawara Fig.9C&9D, field insulating film 17) under the gate pad (see Sugawara Fig.9C&9D, gate pad 33).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have the thickness of a field insulating film under a gate pad be within a range of about 265 nm to 296 nm. Since it has been held that wherein the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involve only routine skill in the art. In re Aller, 105 USPQ 233
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Sugawara, Onozawa, and Niimura, in view of Kueck et al. (Patent. No.: US 9923066 B2), hereinafter as Kueck.
With regards to claim 2, Sugawara, Onozawa, and Niimura teach the semiconductor device according to claim 1.
Sugawara, Onozawa, and Niimura do not teach a trench bottom portion insulating film thicker than the gate insulating film covering the sidewall portion of the trench is formed at the bottom portion of the trench formed in the active region, and wherein a thickness of the trench bottom portion insulating film is equivalent to or greater than a thickness of the field insulating film under the gate pad.
Kueck teaches a trench bottom portion insulating film (see Kueck Fig. 2, insulator 141 (Kueck col. 9, ln. 14) in trench bottom region 14-1 (Kueck col. 9, ln. 15)) thicker than a gate insulating film (see Kueck Fig. 2, insulator 141 in top region 14-2 (see Kueck col. 9, ln. 16)) covering a sidewall portion (see Kueck Fig. 2, top region 14-2) of a trench (see Kueck Fig. 2, trench 14; see Kueck col. 9, ln. 11) is formed at a bottom portion of the trench (see Kueck Fig. 2, trench bottom region 14-1) formed in an active region (see Kueck Fig. 3C, active region 1-1; and see Kueck col. 11, ln. 59-62: “Regarding now in more detail the embodiment schematically illustrated in FIG. 3C, the semiconductor body 10 may comprise an active region 1-1 and an edge region 1-2 surrounding the active region 1-1.”, where semiconductor body 10 can be the semiconductor body 10 shown in Kueck Fig. 2.), and a thickness of the trench bottom portion insulating film (see Kueck Fig. 2, first thickness t1; and see Kueck col. 9, ln. 18-20: “For example, the first thickness t1 is greater than the second thickness t2 by a factor of at least 1.5, 2, 3, 5 or even greater or equal to a factor of 10. For example, the second thickness t2 amounts to at least 30 nm, to at least 50 nm, to at least 75 nm, to at least 0.1 μm, to at least 0.5 μm, 1.0 μm, or is even greater than 1.0 μm.” by choosing the second thickness t2 of Kueck to be about 100 nm and by choosing first thickness t1 of Kueck to be multiplied by a factor of 5 (see Kueck col. 9, ln. 18-20), the trench bottom portion insulating film of Kueck would be about 500 nm.).
By defining the thickness of the gate insulating film covering the sidewall portion of the trench of the combined device of Sugawara, Onozawa, and Niimura with the range taught by Kueck and having a thicker trench bottom portion insulating film taught by Kueck, the combined device of Sugawara, Onozawa, Niimura, and Kueck teaches a trench bottom portion insulating film (see Kueck Fig. 2, insulator 141 in trench bottom region 14-1) thicker (about 500 nm, see explanation in above paragraph 24) than the gate insulating film (see Sugawara Fig.9C&9D, gate insulating film 7; which is about 100 nm, see explanation in above paragraph 24) covering the sidewall portion (see Image A.2, sidewall portion) of the trench (see Sugawara Fig.9C&9D, gate trench 6) is formed at the bottom portion (see Image A.2, bottom portion) of the trench formed in the active region (see Sugawara Fig.1, active region 20), and wherein a thickness (about 500 nm, see explanation in above paragraph 24) of the trench bottom portion insulating film is greater than a thickness (a range of 265 nm to 296 nm, see Niimura [0049]) of the field insulating film (see Sugawara Fig.9C&9D, field insulating film 17) under the gate pad (see Sugawara Fig.9C&9D, gate pad 33).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have a thicker trench bottom portion insulating film taught by Kueck in order to adjust the electrical field present in the trench bottom portion insulating film (see Kueck col. 9, ln. 23-26: “For example, by adjusting a certain first thickness t1, also the electrical field present in the insulator 141 in the bottom region 14-1 can be adjusted.”).
Conclusion
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/E.T.B./Examiner, Art Unit 2818
/CUONG B NGUYEN/Primary Examiner, Art Unit 2818
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