DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/16/2023 was filed and is in
compliance with provision of 37 CFR 1.97. Accordingly, the information disclosure
statement is being considered by the examiner.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required: Claims 1-20 recite the term “homogeneous interconnect structure”. No where in the specification is the term mentioned or defined. It is not clear, for example, if the term as used in device claims 1 and 7 is the metal interconnect layer “130” by itself, or if the term is the metal interconnect layer “130” combined with the via or opening “112”, as shown in Figure 10. In the method claim 14, the term appears to refer to the only the opening “112”. However, it is still not clear. It appears Applicant was their own lexicographer in presenting this term in the application. However, the meaning and the metes and bounds of the term appears to change between the device structure claims and the method claims. For example, in method claim 15 the term “homogenous interconnect structure” used in the limitation “forming a first barrier layer separating the homogeneous interconnect structure from the dielectric layer” is confusing, since it suggests the interconnect structure (i.e. a metal plug) is formed in the dielectric layer opening and then a first barrier layer is formed between the interconnect structure and the dielectric. Clarification and correction of the term are requested.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-6, 8, 11-12, 15-16 and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the first region” in line 5. There is insufficient antecedent basis for this limitation in the claim. Examiner suggests replacing this limitation with “the upper region” since “an upper region” is introduced earlier in claim 1. Claims 2-6 are also rejected, since they depend on claim 1.
In claim 8, line 2, and in claim 11, line 2, the term “substantially” is a relative term which renders the claim indefinite. The term “substantially” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
Claims 5, 12 and 18, line 3 in all three claims, recites “without a barrier layer” which renders the claims indefinite for lack of clarity of where the barrier layer is placed. The examiner suggests the limitation be written as “with no barrier layer between the lower metal line and the homogenous interconnect structure” for clarity. For reference, see how the reverse limitation is phrased in claims 6, 13 and 19.
Claim 11, lines 1-2, recites “wherein the second region comprises a substantially rectangular shape” which renders the claim indefinite for lack of clarity since it is not understood how in claim 11, the second region comprises a substantially rectangular shape, wherein in the independent claim 7, the second region comprises a third width and a fourth width wherein the third width is less than the 4th width. Independent claim 7 corresponds to the trapezoid shape rather than the rectangular shape. The rectangular shape of dependent claim 11 would not have a 3rd and fourth width wherein the third width is less than the 4th width as recited in independent claim 7.
Claims 15 and 16, lines 1-3 in both method claims, recites “the homogenous interconnect structure” which renders the claim indefinite. In both method claims 15 and 16, use of the term “homogenous interconnect structure” in the context of the claim is confusing since it suggests the interconnect structure is formed in the dielectric layer opening before forming “a first barrier layer”. See the objection to the specification for lack of antecedent basis presented above. Additionally, in general, the method claims seem to be written as device claims. For example, method claims would generally begin with forming a via embedded in a dielectric layer with associated first and second regions and first to third widths and their relationships. Then the first barrier layer would be formed. Then the interconnect or plug would be formed over the first barrier layer. The barrier would then naturally separate the interconnect or plug from the dielectric layer. Clarification and Correction is requested.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6-10 and 13-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang et al. (US 10,727,178 B2; herein Chang et al.).
Regarding claim 1, Chang et al. teaches a semiconductor structure comprising:
a homogeneous interconnect structure (232 and via, annotated Fig. 2A) embedded in a dielectric layer (210, annotated Fig. 2A), wherein the homogeneous interconnect structure comprises an upper region (Upper region, annotated Fig. 2A) vertically aligned above a lower region (Lower region, annotated Fig. 2A);
the first region comprises a first width (W1, annotated Fig. 2C) at an upper horizontal surface of the upper region and a second width (W2, annotated Fig. 2C) at a lower horizontal surface of the upper region, wherein the first width is greater than (W1>W2, annotated Fig. 2C) the second width; and
the lower region comprises a third width (W3, annotated Fig. 2C), wherein the third width is greater than (W3>W2, annotated Fig. 2C) the second width.
Furthermore, the annotated Fig. 2C illustrates the width of W1 is greater than W2 and the width of W3 is greater than W2, and although the drawings are not to scale, they may be relied upon for what they would reasonably teach one of ordinary skill in the art when interpreted in view of the specification. (MPEP 2125(II), In re Wright, 569 F.2d 1124, 1127-28, 193 USPQ 332, 335-36 (CCPA 1977)).
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Regarding claim 2, Chang et al. teaches the semiconductor structure according to claim 1, further comprising:
a first barrier layer (230, annotated Fig. 2A) separating the homogeneous interconnect structure (232 and via, annotated Fig. 2A) from the dielectric layer (210, annotated Fig. 2A).
Regarding claim 3, Chang et al. teaches the semiconductor structure according to claim 1, further comprising:
a barrier layer (230, annotated Fig. 2A) separating the homogeneous interconnect structure (232 and via, annotated Fig. 2A) from the dielectric layer (210, annotated Fig. 2A), wherein the barrier layer (230, annotated Fig. 2A), comprises at least two different materials (column 6, line 20).
Regarding claim 4, Chang et al. teaches the semiconductor structure according to claim 1, wherein the lower region comprises a trapezoid shape (Trapezoid shape, annotated Fig 2A).
Regarding claim 6, Chang et al. teaches the semiconductor structure according to claim 1, further comprising:
a lower metal line (206, annotated Fig. 2A) vertically aligned below the homogeneous interconnect structure; and a barrier layer (230, annotated Fig. 2A) between the lower metal line and the homogeneous interconnect structure.
Regarding claim 7, Chang et al. teaches a semiconductor structure comprising:
a homogeneous interconnect structure (232 and via, annotated Fig. 2A) embedded in a dielectric layer (210, annotated Fig. 2A), wherein the homogeneous interconnect structure comprises a first region (Upper region, annotated Fig. 2A) vertically aligned above a second region (Lower region, annotated Fig. 2A);
the first region comprises a first width (W1, annotated Fig. 2C) at an upper horizontal surface of the first region and a second width (W2, annotated Fig. 2C) at a lower horizontal surface of the first region, wherein the first width is greater than the second width (W1 > W2, annotated Fig 2C); and
the second region (Lower region, annotated Fig. 2A) comprises a third width (W33, annotated Fig 2B) at an upper horizontal surface of the second region and a fourth width (W44, annotated Fig 2B) at a lower horizontal surface of the second region, wherein the third width (W33< W44, annotated Fig. 2B) is less than the fourth width.
Furthermore, the annotated Fig. 2B and 2C illustrates the width of W1 is greater than W2 and the width of W33 is greater than W44, and although the drawings are not to scale, they may be relied upon for what they would reasonably teach one of ordinary skill in the art when interpreted in view of the specification. (MPEP 2125(II), In re Wright, 569 F.2d 1124, 1127-28, 193 USPQ 332, 335-36 (CCPA 1977)).
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Annotated Fig. 2B
Regarding claim 8, Chang et al. teaches the semiconductor structure according to claim 7, wherein the second width (W2, annotated Fig. 2C) and the third width (W33, annotated Fig. 2B) are substantially similar.
Regarding claim 9, Chang et al. teaches the semiconductor structure according to claim 7, further comprising:
a first barrier layer (230, annotated Fig. 2A) separating the homogeneous interconnect structure from the dielectric layer (210, annotated Fig. 2A).
Regarding claim 10, Chang et al. teaches the semiconductor structure according to claim 7, further comprising:
a barrier layer (230, annotated Fig. 2A) separating the homogeneous interconnect structure from the dielectric layer (210, annotated Fig. 2A), wherein the barrier layer comprises at least two different materials (column 6, line 20).
Regarding claim 13, Chang et al. teaches the semiconductor structure according to claim 7, further comprising:
a lower metal line (206, annotated Fig. 2A) vertically aligned below the homogeneous interconnect structure; and a barrier layer (230, annotated Fig. 2A) between the lower metal line and the homogeneous interconnect structure.
Regarding claim 14, Chang et al. teaches, in Figs. 3-13, a method of forming a semiconductor structure, the method comprising:
forming a homogeneous interconnect structure (via, annotated Fig. 13 and Figs. 6-8A) embedded in a dielectric layer (410, annotated Fig. 13), wherein the homogeneous interconnect structure comprises a first region (Upper region, annotated Fig. 13), vertically aligned above a second region (Lower region, annotated Fig. 13);
the first region comprises a first width (W1, annotated Fig. 13) at an upper horizontal surface of the first region and a second width (W2, annotated Fig. 13) at a lower horizontal surface of the first region, wherein the first width is greater than (W1>W2, annotated Fig.13) the second width; and
the second region comprises a third width (W3, annotated Fig. 13) wherein the third width is greater than (W3>W2, annotated Fig. 13) the second width.
Furthermore, the annotated Fig. 13 illustrates the width of W1 is greater than W2 and the width of W3 is greater than W2, and although the drawings are not to scale, they may be relied upon for what they would reasonably teach one of ordinary skill in the art when interpreted in view of the specification. (MPEP 2125(II), In re Wright, 569 F.2d 1124, 1127-28, 193 USPQ 332, 335-36 (CCPA 1977)).
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Regarding claim 15, Chang et al. teaches the method according to claim 14, further comprising:
forming a first barrier layer (460, annotated Fig. 13) separating the homogeneous interconnect structure from the dielectric layer (410, annotated Fig. 13).
Regarding claim 16, Chang et al. teaches the method according to claim 14, further comprising:
forming a barrier layer (460, annotated Fig. 13) separating the homogeneous interconnect structure from the dielectric layer (410, annotated Fig. 13), wherein the barrier layer comprises at least two different materials (column 10, line 30).
Regarding claim 17, Chang et al. teaches the method according to claim 14, wherein the second region comprises a trapezoid shape (Trapezoid shape, annotated Fig. 13).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre- AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as
a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
Claims 5, 12 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 10,727,178 B2; herein Chang et al.) in view of Kloster et al. (US 7164206 B2; herein Kloster et al.).
Regarding claim 5, Chang et al. teaches the semiconductor structure according to claim 1, further comprising:
a lower metal line (206, annotated Fig. 2A) vertically aligned with the homogeneous interconnect structure.
However, Chang et al. does not teach a lower metal line directly contacting the homogeneous interconnect structure without a barrier layer.
Kloster et al. teaches in Fig. 1 lower metal line (14, Fig. 1) directly contacting the homogeneous interconnect structure (22 and via Fig. 1) without a barrier layer.
Chang et al. and Kloster et al. are analogous art because they are directed to semiconductor device with homogenous interconnect structure and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chang et al. with the specified features of Kloster et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to modify Chang et al. to include a lower metal line vertically aligned below the homogeneous interconnect structure without a barrier layer, as taught by Kloster et al., the motivation being the junction between metal line and via structure can be formed without barrier layer since the via structure contains conductive material which is similar to the metal line. There is no potential barrier layer required to protect from electrical or thermal diffusion, and this type of content promotes lower resistance, reduced capacitance, increased speed, and reduced power consumption (Kloster et al., col 1, lines 30-60; col 2, line 59 to col 3 line 1).
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Regarding claim 12, Chang et al. teaches the semiconductor structure according to claim 7, further comprising:
a lower metal line (206, annotated Fig. 2A) vertically aligned below the homogeneous interconnect structure.
However, Chang et al. does not teach a lower metal line directly contacting the homogeneous interconnect structure without a barrier layer.
Kloster et al. teaches in Fig. 1 lower metal line (14, Fig. 1) directly contacting the homogeneous interconnect structure (22 and via Fig. 1) without a barrier layer.
Chang et al. and Kloster et al. are analogous art because they are directed to semiconductor device with homogenous interconnect structure and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chang et al. with the specified features of Kloster et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to modify Chang et al. to include a lower metal line vertically aligned below the homogeneous interconnect structure without a barrier layer, as taught by Kloster et al., the motivation being the junction between metal line and via structure can be formed without barrier layer since the via structure contains conductive material which is similar to the metal line. There is no potential barrier layer required to protect from electrical or thermal diffusion, and this type of content promotes lower resistance, reduced capacitance, increased speed, and reduced power consumption (Kloster et al., col 1, lines 30-60; col 2, line 59 to col 3 line 1).
Regarding claim 18, Chang et al. teaches the method according to claim 14, further comprising:
However, Chang et al. does not teach forming a lower metal line vertically aligned below the homogeneous interconnect structure without a barrier layer.
Kloster et al. teaches in Fig. 5 lower metal line (14, Fig. 5) directly contacting the homogeneous interconnect structure (30, Fig. 1) without a barrier layer.
Chang et al. and Kloster et al. are analogous art because they are directed to semiconductor device with homogenous interconnect structure and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chang et al. with the specified features of Kloster et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to modify Chang et al. by forming a lower metal line vertically aligned below the homogeneous interconnect structure directly contacting the homogeneous interconnect structure without a barrier layer, as taught by Kloster et al, the motivation being the lower metal line will provide electrical contact to any device in the substrate and the junction between metal line and via structure can be formed without barrier layer since the via structure contains conductive material which is similar to the metal line. There is no potential barrier layer required to protect from electrical or thermal diffusion, and this type of content promotes lower resistance, reduced capacitance, increased speed, and reduced power consumption (Kloster et al. col 1, lines 30-60; col 2, line 59 to col 3 line 1).
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Regarding claim 19, Chang et al. teaches the method according to claim 14, further comprising:
However, Chang et al. does not teach forming a lower metal line vertically aligned below the homogeneous interconnect structure; and a barrier layer between the lower metal line and the homogeneous interconnect structure.
Kloster et al. teaches forming a lower metal line (14, Fig. 5) vertically below the homogenous interconnect structure; and a barrier layer (16, annotated Fig. 5) between the lower metal line and the homogeneous interconnect structure.
Chang et al. and Kloster et al. are analogous art because they are directed to semiconductor device with homogenous interconnect structure and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chang et al. with the specified features of Kloster et al. because they are from the same field of endeavor.
It would have been obvious to one having ordinary skill in the art before the effecting filling date of the claimed invention to modify Chang et al. by forming a lower metal line vertically aligned below the homogeneous interconnect structure; and a barrier layer between the lower metal line and the homogeneous interconnect structure, as taught by Kloster et al., with the motivation being barrier layer has greater tendency to resist the copper and other metallization materials to diffuse in the other materials (Kloster et al.; col 7, line 25).
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Regarding claim 20, Chang et al. teaches the method according to claim 14, further comprising:
However, Chang et al. does not teach forming an upper metal line vertically aligned above the homogeneous interconnect structure.
Kloster et al. teaches forming an upper metal line (Metal Line, Annotated Fig. 1) vertically aligned above the homogenous interconnect structure.
Chang et al. and Kloster et al. are analogous art because they are directed to semiconductor device with homogenous interconnect structure and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chang et al. with the specified features of Kloster et al. because they are from the same field of endeavor.
It would have been obvious to one having ordinary skill in the art before the effecting filling date of the claimed invention to modify Chang et al. by forming an upper metal line vertically aligned above the homogenous interconnect structure as taught by Kloster et al. with the motivation being the upper metal line provides electrical connection to the via structure other devices on the wafer and also it provides the physical strength to the structure. (Kloster et al., col 1, lines 30-67; col 2, lines 54-67).
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Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 10,727,178 B2; herein Chang et al.) in view of KIM JUNG GEUN [KR]; CHO WHEE WON [KR]; JEONG CHEOL MO [KR] "Contact plug of semiconductor device and method of forming the same” (KR 20110002242 A; herein Kim et al. and listed on the PTO-892 as “JEONG CHEOL MO”).
Regarding claim 11, Chang et al. teaches the semiconductor structure according to claim 7.
However, Chang et al. does not teach wherein the second region comprises a substantially rectangular shape.
Kim et al. teaches the second region comprises a substantially rectangular shape (B, Kim Fig. 1).
Chang et al. and Kim et al. are analogous art to the claimed invention because they both are directed to semiconductor device with low resistance trench or Via structure and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chang et al. in view of Kim et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to modify Chang et al. by modifying trapezoidal shape with the rectangular shape taught by Kim et al. the motivation being replacing substantially trapezoidal shape with a substantially rectangular shape is a similar structure with slight change in area in the cutting portion to reduce material usage, lower construction and maintenance costs, simplify fabrication.
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Furthermore, it has been held that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir.1980). Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc.,725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art.
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Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RUDRA B CHAUDHARY whose telephone number is (571)272-9292. The examiner can normally be reached Mon-Fri 7:30-5:00 p.m.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/R.B.C./Examiner, Art Unit 2811
/LYNNE A GURLEY/Supervisory Patent Examiner, Art Unit 2811
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