Prosecution Insights
Last updated: July 17, 2026
Application No. 18/510,825

SEMICONDUCTOR DEVICE

Non-Final OA §102
Filed
Nov 16, 2023
Priority
Mar 23, 2023 — provisional 63/491,784
Examiner
SENGDARA, VONGSAVANH
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
MediaTek Inc.
OA Round
1 (Non-Final)
72%
Grant Probability
Favorable
1-2
OA Rounds
7m
Est. Remaining
90%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allowance Rate
669 granted / 931 resolved
+3.9% vs TC avg
Strong +19% interview lift
Without
With
+18.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
62 currently pending
Career history
1009
Total Applications
across all art units

Statute-Specific Performance

§101
1.3%
-38.7% vs TC avg
§103
83.7%
+43.7% vs TC avg
§102
12.2%
-27.8% vs TC avg
§112
2.1%
-37.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 931 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant's election with traverse of Species 6, illustrated in Fig. 8, claims 1, 2, 7, 8, 9, 10, 11, 12, 13, and 18 read on this elected Species in the reply filed on 04/21/2026 is acknowledged. The traversal is on the ground(s) that examination of these Species together in one application would not place a serious burden. This is not found persuasive because MPEP 808.02 identifies 3 options to support the burden requirement:  different field of search  separate classification with separate field of search  separate status with separate field of search Each of these requirements includes a separate field of search component. Separate field of search means it is necessary to search for one of the inventions in a manner that is not likely to result in finding art pertinent to the other invention(s) The requirement is still deemed proper and is therefore made FINAL. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 2, 8, 9, 10, 11, 12, 13, and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kubo 20060113105. PNG media_image1.png 539 773 media_image1.png Greyscale Regarding claim 1, fig. 6 of Kubo discloses a semiconductor device, comprising: a substrate 110; a semiconductor die (local silicon interconnect - LSI 102) disposed on the substrate; a lid 152/130 disposed on the substrate and covering the semiconductor die, wherein the lid has an opening 152b (hollow – par [0054]) to expose the semiconductor die; and a liquid metal 160 disposed on the semiconductor die; a gel 170B (par [0066] - 170B is made, for example, of buffer rubber or gel) disposed between the semiconductor die and the lid; and a thermal dissipation structure 154 disposed on the lid and covering the liquid metal, wherein the semiconductor die, the gel and the thermal dissipation structure form a closed space for accommodating the liquid metal. Regarding claim 18, fig. 6 of Kubo discloses a semiconductor device, comprising: a substrate 110; a semiconductor die (local silicon interconnect - LSI 102) disposed on the substrate; a molding compound 106 surrounding the semiconductor die; a lid 152 disposed on the substrate and covering the semiconductor die and the molding compound; a gel 170B arranged between the molding compound and the lid; and a liquid metal 160 arranged between an entire top surface of the semiconductor die and the lid, wherein the semiconductor die, the lid and the gel form a closed space for accommodating the liquid metal. Regarding claim 2, Kubo discloses wherein the lid comprises an extending portion 152c extending towards the semiconductor die, and the gel is in contact with the extending portion of the lid to seal a gap (region occupied by 170B is a gap) between the semiconductor die and the extending portion. Regarding claim 7. The semiconductor device as claimed in claim 2, wherein a bottom surface of the extending portion is lower than the top surface of the semiconductor die, and the top surface of the semiconductor die is lower than or flush with a top surface of the extending portion. Regarding claim 8, fig. 6 of Kubo discloses wherein the gel is affixed to the thermal dissipation structure. Regarding claim 9, fig. 6 of Kubo discloses wherein the thermal dissipation structure covers a top surface of the extending portion, and the gel fills a gap between the thermal dissipation structure and the top surface of the extending portion. Regarding claim 10, fig. 6 of Kubo discloses wherein the gel fills a recess of the thermal dissipation structure, wherein the recess is recessed from a bottom surface of the thermal dissipation structure. Regarding claim 11, fig. 6 of Kubo discloses wherein the gel is arranged on an edge of a top surface of the semiconductor die. Regarding claim 12, fig. 6 of Kubo discloses wherein the lid is arranged on the substrate by an adhesive 140. Regarding claim 13, fig. 6 of Kubo discloses wherein the thermal dissipation structure 154 is arranged on the lid by an adhesive 140. Claims 1, 2, 7 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hung et al. 20230075909. PNG media_image2.png 481 758 media_image2.png Greyscale Regarding claim 1, fig. 1C of Hung discloses a semiconductor device, comprising: a substrate 118; a semiconductor die (104/102/104/106 combination) disposed on the substrate; a lid 126/138/134 disposed on the substrate and covering the semiconductor die, wherein the lid has an opening (region between bottom of 126b and left and right 134) to expose the semiconductor die; and a liquid metal 130 (par [0129]) disposed on the semiconductor die; a gel 132 (par [0129] - gel thermal interfacial material (TIM) 132) disposed between the semiconductor die and the lid; and a thermal dissipation structure 140 disposed on the lid and covering the liquid metal, wherein the semiconductor die, the gel and the thermal dissipation structure form a closed space for accommodating the liquid metal. Regarding claim 18, fig. 6 of Kubo discloses a semiconductor device, comprising: a substrate 118; a semiconductor die (104/102/104/106 combination) disposed on the substrate; a molding compound 122/116 surrounding the semiconductor die; a lid 126/138/134 disposed on the substrate and covering the semiconductor die and the molding compound; a gel 132 arranged between the molding compound and the lid; and a liquid metal 130 arranged between an entire top surface of the semiconductor die and the lid, wherein the semiconductor die, the lid and the gel form a closed space for accommodating the liquid metal. Regarding claim 2, fig. 1C of Hung discloses wherein the lid comprises an extending portion 134 extending towards the semiconductor die, and the gel is in contact with the extending portion of the lid to seal a gap (region occupied by 132 is a gap) between the semiconductor die and the extending portion. Regarding claim 7, fig. 1C of Hung discloses wherein a bottom surface of the extending portion (that of 34) is lower than the top surface of the semiconductor die, and the top surface of the semiconductor die is lower than or flush with a top surface of the extending portion. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VONGSAVANH SENGDARA whose telephone number is (571)270-5770. The examiner can normally be reached 9AM-6PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, PURVIS A. Sue can be reached on (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VONGSAVANH SENGDARA/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Nov 16, 2023
Application Filed
Jun 02, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
72%
Grant Probability
90%
With Interview (+18.6%)
3y 3m (~7m remaining)
Median Time to Grant
Low
PTA Risk
Based on 931 resolved cases by this examiner. Grant probability derived from career allowance rate.

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