Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on September 11, 2025, is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on July 10, 2026, has been entered.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Response to Amendment
The Amendment filed June 9, 2026, has been entered. Claims 1-20 remain pending in the application. Claims 1-9, 11-18, & 20 have been amended. Applicant’s amendments to the Claims have overcome each and every 112(a) and 112(b) rejection(s) previously set forth in the Final Office Action mailed February 10, 2026, hereinafter referred to as the Final Office Action.
Response to Arguments
Applicant’s arguments, see Applicant’s remarks pp. 8-19, filed June 9, 2026, with respect to the rejection(s) of independent claim(s) 1, 5, 9, & 11 under Betser (US 2008/0094127) in view of Walter (US 6438005), as cited by the Applicant, have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new grounds of rejections are made in view of Betser (US 2008/0094127) in view of Walter (US 6438005), in view of Rader (US 2016/0268899), and further in view of Mehas (US 2010/0327825).
Applicant in their submitted response, please refer to pp. 10-11 of Applicant's remarks, presents the first argument, stating ''Betser's current consumption equation lcp_in = 11 + N*l2 does not teach the claimed output current estimation equation IOUT = (IIN X N) - Offset," in amended independent claims 1, 5, 9, & 11. The Examiner finds the Applicant's interpretation of Betser's Equation 4 persuasive and agrees that the variable N does not match the claimed multiplication/division factor. Reliance on Betser's Equation 4 is withdrawn. Corrected Mapping: IOUT = Betser's IOUT (Estimated output current); IIN = Betser's I1 (Measured input current of the pipe); N = Walter's mode conversion factor (e.g., 1.5 in a 3-to-2 mode, or in a 2-to-1 mode); Offset= Betser's !parasitic [0126] and Walter's "quiescent current losses" ([Col. 2, II. 11-19], [Col. 4, II. 34-67], & [Col. 5, II. 27-42]). The rejection of claim 1 (amended independent claims 5, 9, & 11 contain similar claim language) under 35 U.S.C. § 103 stands, as Betser and Walter together make the calculation obvious. Betser outlines estimating output current (IOUT) from input current (IIN), noting practical losses ("Offset"). The base equation (IOUT = I1) uses a factor of 1 for a 1 :1 charge pump. Walter teaches modes with different multiplication/division factors (e.g., "3-to-2 mode" where IOUT= IIN x 1.5) and addresses quiescent current losses affecting the output. A POSITA would find it obvious to modify Betser's input current estimation method by incorporating Walter's mode factors (N) and quiescent current offsets, resulting in IOUT = (IIN x N) - Offset. The motivation is to enhance device performance using established techniques (MPEP § 2143). Integrating Walter's conversion ratios and offsets into Betser's logic allows accurate micro-controller estimation of output current for various voltage modes without direct output measurement.
Further, the algorithmic estimation of the output current is taught by Rader, in combination with the digital calculation execution taught by Mehas below. The combination of Bester, Walter, and Rader teach the limitation of calculation an estimated output current as IOUT = (IIN X N) – Offset. While Betser discloses the foundational switched capacitor architecture and input current measurement, Rader teaches calculating the estimated output current using a hardware processor 110 via the mathematical formula IOUT = IIN/D – (ISWLOSS + IRIPPLE_LOSS) ([0052]-[0054] & [0089]). This relationship corresponds to the claimed calculation where the current input is modified by a division factor (1/D) and reduced by an offset accounting for parasitic losses. This represents the application of a known technique to a known device under MPEP § 2143 to incorporate Rader’s specific algorithmic hardware processor calculation into the switched capacitor circuit of Betser and Walter. A POSITA would have been motivated to make this modification to accurately calculate output current digitally without the need for a dedicated, lossy output current sensory, reducing component area and power dissipation while maintaining high efficiency over broad current ranges.
Applicant in their submitted response, please refer to pp. 11-12 of Applicant's remarks, presents the second argument, stating "Betser does not teach calculating an estimated output current," in amended independent claims 1, 5, 9, & 11. The Examiner accepts the Applicant's argument that Betser's Equation 4 calculates supply consumption, not output current, and withdraws reliance on it for this limitation. However, Betser does teach estimating output current using a processor based on measured input current (see Betser [0130] & [0161]), with the foundational equation IOUT = 11 ([0123]). The rejection under 35 U.S.C. § 103 is sustained, as the claimed equation IOUT = (IIN X N) - Offset is made obvious by Betser and Walter. Betser demonstrates a 1 :1 conversion ratio, noting parasitic current losses ([0126]), while Walter teaches multi-mode conversion ratios (e.g., "3-to-2 mode" with IOUT = IIN X 1.5, see Walter ([Col. 5, II. 1-42]) and accounts for quiescent current as an offset ([Col. 2, II. 11-19], [Col. 4, II. 34-67], & [Col. 5, II. 27-42]). It would have been obvious to combine Betser's calculation with Walter's multiplication factors (N) and subtracting the known quiescent/parasitic losses (Offset; recognized by both references) to enable accurate output current estimation across modes without direct output measurement. The motivation to combine is to apply a known technique to improve similar devices (MPEP § 2143), specifically to allow the estimation method of Betser to accurately calculate output current across the varying, multi-mode voltage conversion ratios taught by Walter without requiring direct measurement at the output node.
Further, the updated rejection below does not rely on Betser for the calculation limitation but rather relies on Rader. Rader teaches calculating the output current using a processor via the algorithmic formula IOUT = IIN/D – (ISWLOSS + IRIPPLE_LOSS) ([0052]-[0054] & [0089]). Rader provides a 1-to-1 match for the claimed variables, where IIN maps to the measured input current, 1/D maps to the multiplication/division factor N, and the combined parasitic loss (ISWLOSS + IRIPPLE_LOSS) maps to the Offset. Mehas is further cited to disclose the hardware processor, teaching a digital calculation circuit 380 that receives digitized signals to compute the current of the power conversion circuit ([0038]-[0040], [0043], & [0045]). It would have been obvious to a POSITA to incorporate Rader’s specific algorithmic output current calculation and Meha’s hardware processor into the switched capacitor of Betser and Walter to accurately calculate output current digitally without the need for a lossy output current sensor.
Applicant in their submitted response, please refer to pg. 12 of Applicant's remarks, presents the third argument, stating "Betser does not teach calculating an estimated output current using an Offset," in amended independent claims 1, 5, 9, & 11. The Examiner finds the Applicant's interpretation of N X 12 in Betser's Equation 4 persuasive, agreeing that it represents driver current consumption rather than an output-current offset. Therefore, the assertion that N X 12 maps to the claimed "Offset" is withdrawn, as is reliance on Betser's Equation 4. Corrected Mapping for "Offset": Betser teaches that the base calculation (IOUT = I1) is an idealization and identifies that the circuits suffer from "parasitic current" ([0126]); Walter provides stronger secondary support teaching that switched capacitor regulators suffer from "quiescent current losses" and "switch losses" that reduce the effective power transferred to the output ([Col. 2, II. 11-19], [Col. 4, II. 34-67], & [Col. 5, II. 27-42]). A Person of Ordinary Skill in the Art (POSIT A) formulating an accurate estimation equation would naturally subtract these known parasitic/quiescent losses (Offset) from the theoretically converted current (IIN X N) to determine the true estimated output current. The rejection under 35 U.S.C. § 103 remains. The calculation IOUT = (IIN X N) - Offset is considered obvious based on Betser and Walter. Betser's calculation, IOUT = I1 ([0123] & [0126]), is idealized; both Betser and Walter acknowledge inefficiencies like parasitic and quiescent current losses that offset actual output current. It would have been obvious to modify Betser's estimation method to incorporate the multi-mode multiplication/division factors (N) taught by Walter. Furthermore, it would have been obvious to a POSITA to mathematically account for the "parasitic current" (Betser) and "quiescent current losses" (Walter), and to subtract these losses as an output current "Offset" from the theoretical current (IIN X N). The motivation to incorporate this subtraction into the calculation is to apply a known technique to improve similar devices (MPEP § 2143). Specifically, subtracting known parasitic and quiescent offsets from the theoretical mode-converted current allows the micro-controller of Betser to generate a highly accurate, real-world estimation of the output current, fulfilling Betser's stated goal of precise current monitoring without requiring direct, lossy measurement at the output node.
Further, Rader teaches calculating the output current via the mathematical formula IOUT = IIN/D – (ISWLOSS + IRIPPLE_LOSS) ([0052]-[0054] & [0089]). Where IIN maps to the measured input current IIN; 1/D maps to the multiplication/division factor N; The combined parasitic loss (ISWLOSS + IRIPPLE_LOSS) maps to the claimed Offset. Rader defines (ISWLOSS + IRIPPLE_LOSS) as calculation error corrections representing parasitic power lost as heat (switching and conduction/ripple losses) that do not contribute to the output current ([0008], [0047], & [0094]). Therefore, Rader’s term is used as an output-current offset to correct the estimated output calculation. It would have been obvious to a POSITA to incorporate Rader’s specific algorithmic offset and Meha’s hardware processor into the multi-mode switched capacitor circuit of Betser and Walter, where the combination would accurately estimate output current digitally by accounting for parasitic loss offsets, eliminated the need for a dedicated, lossy output current sensor and improving overall power efficiency across broad current ranges.
Applicant in their submitted response, please refer to pp. 12-13 of Applicant's remarks, presents the fourth argument, stating "Betser's teachings of IOUT = I1 do not teach IOUT = (IIN X N) - Offset," in amended independent claims 1, 5, 9, & 11. Applicant's remarks asserting that Betser's Equation 5 (IOUT = I1) is an ideal case that does not, by itself, teach the generalized claimed equation IOUT = (IIN X N) - Offset have been fully considered. The Examiner agrees that Betser's Equation 5 represents an estimation for a 1 :1 charge pump and withdraws the previous assertion that this "special trivial case" alone teaches the general equation. However, the Examiner respectfully disagrees, and Applicant's arguments are unpersuasive because they address the references separately rather than their combined teachings. The test for obviousness is not whether the features of a secondary reference can be bodily incorporated into the structure of the primary reference, nor whether the primary reference alone teaches every limitation, but whether the combination of teachings would have suggested the claimed invention to a person of ordinary skill in the art. (See In re Keller, 642 F.2d 413,208 USPQ 871 (CCPA 1981)). The rejection is maintained as Betser, in view of Walter, renders the claimed equation obvious. Betser demonstrates using a hardware processor to calculate an estimated output current (IOUT) based on input current (IIN or 11), (see Betser [0161]), primarily in a standard 1 :1 pump. Walter expands on this by teaching multiple modes that alter the ratio between input/output currents and highlights quiescent current losses ("Offset"). Walter teaches a "3-to-2 mode" where input current is multiplied by a division factor of 1.5 to correlate to the output current (i.e., IOUT = IIN X 1.5), as well as a "2-to-1 mode" (See Walter [Col. 2, II. 11-19], [Col. 4, II. 34-67], [Col. 5, II. 27-42], & [Col. 6, II. 4-26]). Combining Betser's measurement method with Walter's multi-mode architecture and loss offsets would lead a POSITA to modify the baseline mathematical calculation taught by Betser(IOUT = IIN) to accommodate the multi-mode architectures taught by Walter. A POSITA applying Beter's measuring technique to Walter's multi-mode converter would predictably and obviously modify the algorithm to multiply the measured input current by Walter's specific mode factor (N, such as 1.5 or 2) and subtract Walter's known quiescent current losses (Offset) to arrive at the accurate, estimated output current calculation: IOUT = (IIN x N) - Offset. The motivation to combine is to apply a known technique to improve similar devices (MPEP § 2143). Incorporating Walter's mode ratios and loss offsets into Betser's estimation logic provides the predictable benefit of allowing the microcontroller to accurately estimate the true output current across various voltage step-down/step-up configurations without requiring physical measurement at the output node.
Further, the updated rejections below shift the reliance for the active variables N and Offset to Walter and Rader, where these values are non-trivial. Formally withdrawing Betser’s equation satisfies the generalized IOUT = (IIN X N) – Offset via a special case where N=1 and Offset = 0. The claimed multiplication/division factor N is taught by Walter. Walter discloses a multi-mode switched capacitor circuit that operates at distinct step-down conversion rations, detailing a “3-to-2” mode and a “2-to-1” mode. In these modes the average input current is a fraction of the average output current, proving that Walter teaches a non-trivial multiplication/division factor N that actively scales the input current. The claimed Offset is taught by Rader and discloses estimating the output current using the formula IOUT = IIN/D – (ISWLOSS + IRIPPLE_LOSS). Establishing a non-trivial, non-zero offset comprised of calculated parasitic losses that are subtracted from the scaled input current to determine the output. While Betser teaches the foundational circuit and input current measurement, it would have been obvious to a POSITA to modify this baseline architecture. Incorporating Walter’s varying multiplication factors to optimize efficiency across different voltage levels and apply Rader’s hardware-processed mathematical offset to accurately estimate the final output current digitally by accounting for physical parasitic losses. This combination yields the generalized calculation IOUT = (IIN x N) – Offset.
Applicant in their submitted response, please refer to pp. 13-14 of Applicant's remarks, presents the fifth argument, stating "Walter's N cannot be combined with Equation (4) of Betser because the combination of Betser and Walter results in an incorrect equation," in amended independent claims 1, 5, 9, & 11. Applicant's remarks asserting that Walter's ratio (N) cannot be inserted into Betser's Equation 4 (lcp_in = I1 + N x 12) because it violates the branch current analysis of Betser's circuit have been fully considered and are deemed persuasive. The Examiner agrees that modifying Betser's Equation 4 with Walter's conversion ratio creates an incorrect mathematical relationship. Accordingly, the Examiner withdraws any reliance on Betser's Equation 4, as well as any assertion that the combination requires altering the variables within that specific equation. The Applicant's assertion that the rejection relies on an improper hindsight reconstruction of disparate teachings is not persuasive. The rejection under 35 U.S.C. § 103 does not propose forcing Walter's variables into Betser's total current consumption equation. Rather, the combination applies the estimation methodology of Betser to the advanced circuit architecture of Walter. Betser teaches the foundational methodology of using a hardware processor to estimate the output current of a charge pump without measuring the output directly, but rather by measuring the input current (IIN or I1) and using a mathematical relationship (See Betser [0123], Eq. 5: IOUT = 11). In Betser's 1-to-1 charge pump, the multiplication factor (N) is inherently 1. Betser acknowledges this is an idealization and that "parasitic current" losses exist (See Betser [0126]). Walter introduces a switched capacitor architecture capable of multiple operating modes (e.g., 1-to-1, 3-to-2, 2-to-1) for efficient operation across varying input voltages. The input-to-output current relationship depends on the mode's conversion factor (N): for example, in the 3-to-2 mode, input current equals 1.5 times the output current (i.e., IOUT = IIN x 1.5) in ([Col. 2, II. 11-19], [Col. 4, II. 34-67], [Col. 5, II. 1-42], & [Col. 6, II. 4-26]). Applying Betser's input-based, output current estimation to Walter's multi-mode charge pump, a POSITA would predictably formulate the estimation algorithm to reflect Walter's circuit, specifically, the processor would multiply the input current by the active mode conversion factor (N of Walter, e.g., 1.5 or 2), subtract the quiescent current losses (Offset), and calculate output current as IOUT = (IIN X N) - Offset. Mathematical relationship is based on Betser's input-sensing estimation technique, implemented with Walter's multi-mode power conversion circuit. The combination is not about modifying Betser's current consumption equation, but applying Betser's methodology (estimating output current by sensing input current) to Walter's multi-mode switched capacitor converter with losses, to yield the predictable mathematical expression. The motivation to combine these teachings is to apply a known technique to improve similar devices (MPEP § 2143), yielding the predictable benefit of accurate, mode-aware output current estimation without requiring additional lossy sensing components at the output node.
Further, Betser’s equations, are withdrawn from the updated rejections below. No mathematical reconstruction is necessary because Rader explicitly discloses the exact mathematical relationship in its entirety. Rader teaches calculating the output current via the operation IOUT = IIN/D – (ISWLOSS + IRIPPLE_LOSS). There is no rearrangement; Rader’s singular formula directly maps to the claimed IOUT = (IIN x N) – Offset. Walter is cited to demonstrate the switched capacitor circuits inherently utilize various multiplication/division factors (like “3-to-2” or “2-to-1” modes) to dictate the ratio between average input current and average output current. Walter establishes that the 1/D factor in Rader’s equation is known in the arts as a multiplication or division factor N for switched capacitor power conversion. The rejection does not reconstruct an equation; it applies a known algorithmic estimation technique (Rader) to a known multi-mode circuit architecture (Betser and Walter) using known digital hardware (Mehas). A POSITA would be motivated to integrate Rader’s specific algorithmic calculation into the multi-mode switched capacitor systems of Betser and Walter to digitally estimate output current without requiring a physical lossy output current sensor, improving efficiency measurement and load balancing.
Applicant’s arguments, see Applicant’s remarks pp. 8-19, filed June 9, 2026, with respect to the rejections of dependent claims 2, 3, & 7 under Betser (US 2008/0094127) in view of Walter (US 6438005), as cited by the Applicant, have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new grounds of rejections are made in view of Betser (US 2008/0094127) in view of Walter (US 6438005), in view of Rader (US 2016/0268899), in view of Mehas (US 2010/0327825), and further in view of Meyvaert (US 2020/0144908).
Applicant in their submitted response, please refer to pp. 16-17 of Applicant's remarks, presents the seventh argument, stating that Figure 2B and paragraphs [0144]-[0145] of Betser teach limiting parameters based on charge pump current consumption, rather than ''wherein the hardware processor is configured to execute computer-readable instructions to calculate the estimated output current. .. ," of amended dependent claims 2, 3, & 7, have been considered and are deemed persuasive. The Examiner agrees and withdraws reliance on Figure 2B and paragraphs [0144]-[0145] as the basis for teaching the calculation of the estimated output current. However, the claim that Betser entirely fails to teach a hardware processor configured to execute computer-readable instructions to calculate the estimated output current is unconvincing. The rejection under 35 U.S.C. § 103 stands, supported by relevant Betser disclosures. Betser teaches the calculation of the estimated output current (see paragraph [0161]: states" the charge pump's output current (IOUT) can be calculated as: IOUT= I1 ... ") and references a microcontroller to handle logical operations and system control ([0045]-[0046] & [0094]-[0097]), noting that signals are "sent to a microcontroller." It is well known and inherent in the art that a micro-controller is an integrated circuit comprising a processor core and memory, and that it performs calculations and logical operations by executing programmed firmware or software, which constitute "computer-readable instructions." As detailed earlier, combining Betser and Walter makes the claimed method obvious, as a POSITA would configure the firmware (computer-readable instructions) executed by Betser's micro-controller to incorporate the multi-mode multiplication/division factors (N) and quiescent current losses (Offset) taught by Walter, to compute/calculate the estimated output current for the combined multi-mode power conversion circuit.
Further, the Examiner withdraws the reliance on Betser for the “computer-readable instructions” limitations. The updated rejections below rely on Meyvaert and Mehas for the execution of computer-readable instructions. Meyvaert discloses a “hardware processor” used to estimate the current provided to the load and specifies that this hardware processor “can be controlled by a program stored in the memory” and utilizes “computer readable media… for storing instructions for performing the functions and/or processes herein” ([0031] & [0033]). Further, Mehas discloses electronic circuitry 1302 “executing specific software to perform specific calculations or tasks” ([0060]). This establishes that the use of software-driven hardware processors to calculate power conversion metrics is well-known in the art. It would have been a substitution to upgrade the hardwired analog control circuit of Betser with the software-driven hardware processors of Meyvaert and Mehas. A POSITA would be motivated to do so because executing current estimation calculations via computer-readable instructions allows the algorithms (like Rader’s offset formula) to be easily updated, scaled, or modified without requiring inflexible physical hardware redesigns.
Applicant’s arguments, see Applicant’s remarks pp. 17-18, filed June 9, 2026, with respect to the rejections of dependent claims 4, 8, 10, & 14 under Betser (US 2008/0094127) in view of Walter (US 6438005), as cited by the Applicant, have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new grounds of rejections are made in view of Betser (US 2008/0094127) in view of Walter (US 6438005), in view of Rader (US 2016/0268899), and further in view of Mehas (US 2010/0327825).
Applicant in their submitted response, please refer to pp. 17-18 of Applicant's remarks, presents the ninth argument, stating that the previous Office Action, Walter does not teach “wherein the output current offset is determined based on the measured input offset”, and improperly mapped Betser's N x I2 term to the output current offset, and utilized an improper "inherently obvious" rationale, for amended dependent claim 6, has been fully considered and deemed persuasive. Examiner agrees that N x I2 represents the driver current drawn from the supply, not an output offset and withdraws the concluding statement that the modification was "inherently obvious." The rejection of the claim under 35 U.S.C. § 103 is maintained, as the limitation is rendered obvious by the combination of Betser and Walter under a corrected, technically supported rationale. Established in previous earlier responses of this document, the claimed "Offset" properly corresponds to the "quiescent current losses" and "switch losses" explicitly taught by Walter (See Walter [Col. 2, II. 11-19], [Col. 4, II. 34-67], [Col. 5, II. 1-42], & [Col. 6, II. 4-26]). Furthermore, Walter teaches a mode control circuit (a second sensing circuit) that continuously measures the input voltage to determine the appropriate operating mode for the switches (See Walter [Claim 20]). In switched capacitor converters, Offset varies with input voltage and switch configuration. Since Walter shows measuring input voltage to control switches, configuring the processor to determine output current offset from measured input voltage would be apparent to someone skilled in the art. The motivation to combine these teachings is to apply a known technique to improve similar devices (MPEP § 2143). Specifically, configuring the estimation algorithm of the combined system to determine the Offset based on Walter's dynamically measured input to improve device accuracy by allowing the estimation algorithm to account for voltage-dependent parasitic losses that occur during power supply discharges during operation.
Furthermore, reliance on Betser and Walter is withdrawn and shifted to Rader, who teaches the limitation without requiring any logical leaps. The rejection is maintained because Rader teaches utilizing a second, distinct sensing circuit (voltage sensor 134) dedicated to measuring the input voltage (Vin) entering the power conversion circuit. The offset is actively determined by this measured voltage. Rader teaches that the output current offset comprises parasitic switching loss (ISWLOSS) and ripple loss (IRIPPLE_LOSS). Rader’s formulas show that both losses are mathematically calculated using the measured input voltage: the switching loss formula is ISWLOSS = C x V x F (where V is the measured input voltage), and the ripple loss formula inherently relies on Vin to calculate the parasitic resistance ratio (Fig. 1; [0049], [0074]-[0075], [0080], & [0089]). Therefore, Rader’s offset is explicitly and dynamically determined based on the measured input voltage. It would have been the application of a known technique to a known device to incorporate Rader’s dedicated input voltage sensor and voltage-dependent offset calculation into the switched capacitor circuits of Betser and Walter. A POSITA would be motivated to make this combination to determine true parasitic loss offsets that inherently fluctuate with the supply voltage, significantly improving power efficiency calculations and maintaining accurate output current estimation across a broad range of operating conditions.
Applicant’s arguments, see Applicant’s remarks pp. 17, filed June 9, 2026, with respect to the rejection of dependent claim 6, under Betser (US 2008/0094127) in view of Walter (US 6438005), as cited by the Applicant, have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, in light of the amended limitations, new grounds of rejections are made in view of Betser (US 2008/0094127) in view of Walter (US 6438005), in view of Rader (US 2016/0268899), and further in view of Mehas (US 2010/0327825). Please refer to the updated rejections below.
Applicant’s arguments, see Applicant’s remarks pp. 15-16, filed June 9, 2026, with respect to the rejections of independent claim 11 under Betser (US 2008/0094127) in view of Walter (US 6438005), as cited by the Applicant, have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new grounds of rejections are made in view of Betser (US 2008/0094127) in view of Walter (US 6438005), in view of Rader (US 2016/0268899), and further in view of Mehas (US 2010/0327825).
Applicant in their submitted response, please refer to pp. 15-16 of Applicant's remarks, presents the sixth argument, stating that the cited art does not disclose: "measuring ... an input current into a switched capacitor power conversion circuit," "measuring ... an output current from the switched capacitor power conversion circuit," and "calculating ... a first output current offset for the switched capacitor power conversion circuit according to an equation: IOUT = (IIN X N) - Offset," ... " of amended independent claim 11, and requires further search and/or consideration, due to proposed new amended claim language. Applicant's remarks asserting that the previous Office Action misinterpreted the method of estimating output current (Claim 1) with the method of calculating an output current offset and improperly mapped the Offset to Betser's N x I2 term, have been fully considered and are deemed persuasive. The Examiner agrees that N x I2 represents total driver current consumption, not an output current offset. The Examiner withdraws reliance on Betser's Equation 4, as well as the assertion that Betser alone teaches calculating this offset. The rejection under 35 U.S.C. § 103 is maintained, as the claimed method for determining the output current offset is rendered obvious by the combination of Betser and Walter under a corrected rationale. The claim requires measuring both the input current and the output current to calculate the Offset. Betser teaches measuring the input current using a first sensing circuit (e.g., resistor R 1) (See Betser [0131 ]). While Betser focuses on subsequently estimating the output without measuring it, Walter, in the exact same field of endeavor, teaches a multi-mode switched capacitor converter that utilizes an "output current feedback circuit" coupled to the output node to physically monitor the output current (See Walter [Claim 20]). Furthermore, as established in the earlier rejection of Claim 1 (above), Walter teaches that these conversion circuits utilize specific multiplication/division factors (N) based on the operating mode, and suffer from "quiescent current losses" (Offset) (See Walter [Col. 2, II. 11-19], [Col. 4, II. 34-67], [Col. 5, II. 1-42], & [Col. 6, II. 4-26]). It would have been obvious to a POSITA to modify the system of Betser, incorporating the output current feedback circuit (second sensing circuit) taught by Walter to physically measure the actual output current. A POSIT A would recognize that in order to accurately utilize the ideal mathematical relationship IOUT = (IIN x N) - Offset, the system must first know the value of the quiescent losses (Offset). By measuring both the actual input current and the actual output current at least once (a one-time estimation) utilizing the combined sensing circuits of Betser and Walter, it is a predictable, basic algebraic operation for the hardware processor to calculate the exact Offset of the circuit. The motivation to combine these teachings is to apply a known technique to improve similar devices (MPEP § 2143). Specifically, utilizing Walter's output feedback circuit to perform a one-time initial measurement of the actual output current allows Betser's micro-controller to characterize the precise parasitic and quiescent current losses (the Offset) of the specific hardware. This yields the predictable benefit of an accurate, calibrated current estimation for all subsequent operations.
Further, the Examiner withdraws the assertion that Betser and Walter teach these specific limitations in light of the amendments in independent claim 11. The rejection is maintained because Radar explicitly teaches the missing limitations. Rader teaches performing a “characterization mode (or setup mode)” prior to operational “mission mode” specifically to characterize the losses (the offset) of the converter using a ”one-time estimation” ([0006], [0103], & [0119]). Further, Rader teaches an alternate implementation where distinct sensing circuits are used to measure both the input current and the output current simultaneously ([0063]). During this one-time characterization mode, with both IIN and IOUT measured, Rader’s hardware processor utilizes the explicit algebraic formula IOUT = IIN/D – (ISWLOSS + IRIPPLE_LOSS) to calculate and isolate the true physical offset. There is no improper reconstruction of disparate variables; Rader’s singular formula directly maps to the claimed equation, where 1/D maps to N, and the combined parasitic loss maps to the calculated Offset. The updated rejection relies on applying a known algorithmic characterization technique (Rader) to a known multi-mode circuit architecture (Betser and Walter). A POSITA would be motivated to integrate Rader’s dual-measurement characterization mode and specific algebraic formula into the multi-mode switched capacitor systems of Betser and Walter to calculate and store the true parasitic loss offsets during an initial calibration phase. This ensures accurate current estimation during subsequent mission-mode operations without relying on continuous lossy output current sensing.
Applicant’s arguments, see Applicant’s remarks pp. 18-19, filed June 9, 2026, with respect to the rejections of dependent claim 15 under Betser (US 2008/0094127) in view of Walter (US 6438005), and further in view of Meyvaert (US 2020/0144908), as cited by the Applicant, have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new grounds of rejections are made in view of Betser (US 2008/0094127) in view of Walter (US 6438005), in view of Rader (US 2016/0268899), and further in view of Mehas (US 2010/0327825).
Applicant in their submitted response, please refer to pp. 18-19 of Applicant's remarks, presents the tenth argument, stating that determining the difference between the measured actual output current and the scaled measured input current does not yield Betser's N x I2 term, has been fully considered and deemed persuasive. The Examiner agrees that N x I2 represents driver current consumption and that calculating the difference between the input and output currents of the pipe does not isolate this specific driver current value. Accordingly, the Examiner formally withdraws the previous assertion that Betser's N x I2 term corresponds to the claimed "Offset." The rejection of the claim under 35 U.S.C. § 103 is maintained. The claimed method of determining the Offset is rendered obvious by the combination of Betser, Walter, and Meyvaert under a corrected rationale that relies on the proper definition of the system's current offset. As established in the corrected rejections of the previous claims, the claimed " Offset" properly corresponds to the "quiescent current losses" and "switch losses" of the conversion circuit, as explicitly taught by Walter (See Walter [Col. 2, II. 11-19], [Col. 4, II. 34-67], [Col. 5, II. 1-42], & [Col. 6, II. 4-26]). Betser and Walter establish the mathematical relationship governing the multi-mode charge pump: IOUT = (IIN x N) - Offset. Meyvaert teaches a calibration process wherein both the input current (IIN) and the output current (IOUT) are measured to determine the efficiency and current losses (Offset) of the circuit (See Meyvaert [0012]-[0014]). It would have been obvious to a POSITA to configure the hardware processor of the combined system to determine the value of the quiescent/switch losses (Offset) by measuring/calculating the difference between the measured output current (IOUT) and the measured input current scaled by the mode factor (IIN x N), and following the relationship of the circuit, Offset= (IIN x N) -IOUT. A POSITA performing Meyvaert's calibration measurements would predictably use standard algebraic rearrangement to solve for the unknown loss variable, resulting in the calculation: IOUT = (IIN x N) - Offset. The motivation to combine these teachings is to apply a known technique to improve similar devices (MPEP § 2143). Specifically, programming the hardware processor to calculate the difference between the measured mode current and the measured output current during a calibration phase provides the predictable benefit of accurately quantifying the parasitic and quiescent losses (Offset) of the hardware, enabling precise current estimation during subsequent standard operations.
Furthermore, the Examiner has updated the rejection below and is now maintained by relying on Rader, teaching an alternate implementation where dedicated sensing circuits measure both the input current and the output current during a one-time characterization mode ([0063] & [0089]). The Examiner agrees that the prior art fails to teach calculating the offset via a difference between the scaled input current and the measured output current. Rader’s mathematical formula executed by the hardware processor: IOUT = IIN/D - (ISWLOSS + IRIPPLE_LOSS), can be rearranged to yield the claimed difference calculation: (ISWLOSS + IRIPPLE_LOSS) = IIN/D - IOUT, the variables are mapped: Offset: (ISWLOSS + IRIPPLE_LOSS); difference calculation (-): the subtraction operator isolating the parasitic loss; (IIN x N): IIN/D where the measured input current is scaled by the division factor 1/D; and IOUT is the measured output current IOUT. A POSITA would be motivated to apply Rader’s one-time dual-measurement characterization mode and algebraic difference calculation to the multi-mode switched capacitor circuit of Betser and Walter. This allows the system to determine and store the true parasitic loss offset across varying conversion modes during an initial calibration phase, yielding accurate sensorless current estimation during mission-mode operations.
Therefore, Applicant’s arguments are unconvincing and the rejections of amended independent claims 1, 5, 9, & 11, and dependent claims 2-4, 6-8, 10, & 12-20, which depend from and incorporate the limitations of independent claims 1, 5, 9, & 11, are respectively maintained. Updated rejections based on the new prior art reference(s) follow below.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites the limitation "a measured input current" in line 8, which was previously disclosed in line 3 ”measure an input current”. The repeated recitation of “a measured input current”, introduces indefiniteness, for this limitation in the claim. For examination purposes, Examiner interprets “a measured input current”, to refer to the previously disclosed “measure an input current” in claim 5. Claims 6-8, which do not rectify the defect, are rejected in virtue of dependence on claim 5.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-5, 8, 11, 15, & 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Betser et al. (US 2008/0094127 A1, Pub. Date Apr. 24, 2008, hereinafter, Betser), in view of Walter (US 6438005 B1, Pat. Date Aug. 20, 2002, hereinafter, Walter), in view of Rader et al. (US 2016/0268899 A1, Pub. Date Sep. 15, 2016, hereinafter, Rader), and further in view of Mehas et al. (US 2010/0327825 A1, Pub. Date Dec. 30, 2010, hereinafter, Mehas).
Regarding independent claim 1, Betser, teaches:
A method for estimating an output current of a switched capacitor power conversion circuit ([Title], [Abstract], [0003], [0083], [0097], & [0130]-[0132]: discloses a switched capacitor power conversion circuit (charge pump)), the method comprising ([Abstract], [0003], [0083], & [0130]: discloses a method for estimating/measuring the output current based on the input current):
measuring, using a first sensing circuit (Fig. 2A; [0083], [0130]-[0131], & [0148]: measures the input current I1 flowing into the charge pump (switched capacitor circuit) using a sensing circuit (resistor R1)), an input current into the switched capacitor power conversion circuit (Figs. 1A & 2A; [0083], [0085], [0118], [0130]-[0132], [0148], [0161], & [Claim 1]: the switched capacitor power conversion circuit is the “Conventional Control Circuit” in the charge pump); and
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Betser, is silent in regard to:
calculating, using a hardware processor, an estimated output current from the switched capacitor power conversion circuit as:
IOUT = (IIN x N) – Offset
wherein IOUT is the estimated output current, IIN is the measured input current, N is a multiplication or division factor of the switched capacitor power conversion circuit, and Offset is an output current offset.
However, Rader, further teaches:
The Examiner is combining Betser and Walter in view of Rader and Mehas, by implementing Mehas’s digital calculation circuit (hardware processor) to execute the algorithmic current estimations (Fig. 3b; [0038]-[0040], [0043], & [0045]).
calculating, using a hardware processor, an estimated output current from the switched capacitor power conversion circuit as (Fig. 4; [0089]: teaches calculating an estimated output current using the algebraic structure, dividing the measured input current by a factor and subtracting an offset):
IOUT = (IIN x N) – Offset (Fig. 4; [0089])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the digital calculation circuit taught by Mehas as the hardware processor in the combined system to execute the output current estimation formula of Rader. The addition of Mehas to the combination of Betser, Walter, and Radar addresses executing the calculation using a hardware processor. Rader discloses the algorithmic formula for current estimation, Mehas teaches a digital calculation circuit 380 equipped with memory 382 that receives digitized signals from analog-to-digital converters (365/370) to algorithmically compute the current of the power conversion circuit. A POSITA would be motivated to include this digital calculation hardware as a substitution to execute the algorithms digitally, eliminating systematic errors from second-order effects and transients via digital filtering, which increases overall measurement accuracy (KSR).
However, Walter, further teaches:
The Examiner is combining Betser and Walter in view of Rader by implementing Rader’s 1-to-1 match for the equation variables: IOUT maps to the estimated output current, IIN maps to the measured input current, 1/D maps to the division factor N, and the combined parasitic loss (ISWLOSS + IRIPPLE_LOSS) maps to the current offset ([0005]-[0006], [0008], [0012]-[0016], [0020], [0023]-[0025], [0027], [0047], [0049], [0052], [0060]-[0065], [0077]-[0081], [0084], [0089], [0092], [0094]-[0095], [Claim 3]-[Claim 7], [Claim 12], [Claim 15]-[Claim 16], & [Claim 21]-[Claim 23]).
wherein IOUT is the estimated output current, IIN is the measured input current, N is a multiplication or division factor of the switched capacitor power conversion circuit ([Col. 2, ll. 13-19 & 43-49] & [Col. 4, ll. 34-40 & 56-67]: teaches the relationship N, multiple modes with different conversion factors, where a switched capacitor is operable in a plurality of modes, such as “operates in a “3-to-2” mode wherein the average input current is approximately two-thirds (2/3) the average output current”, rearranging the formula to IOUT = IIN * 1.5, or 1-to-1 mode, or 2-to-1 mode), and Offset is an output current offset.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Betser’s baseline switched capacitor charge pump and input current measurement by incorporating Walter’s multi-mode step-down charge pump 18 and Rader’s mathematical current estimation formula, which represents the application of known techniques to a known device. Walter cures Betser’s lack of varied operating modes by teaching that a switched capacitor circuit operates at fixed multiplication or division factors (N), such as a 3-to-2 mode yielding an average input current that is approximately two-thirds (2/3) of the average output current. Rader teaches calculating an estimated output current using the algebraic structure claimed, where the processor 110 computes IOUT = IIN/D - (ISWLOSS + IRIPPLE_LOSS), mapping the measured input current to IIN, the division factor 1/D to N, and the combined parasitic loss to the output current Offset. A POSITA would be motivated to combine these teaches to accurately estimate output current computationally by accounting for parasitic loss offsets across varying step-down conversion ratios. This combination would eliminate the need for a dedicated lossy output current sensor, reducing component area, lowering power dissipation, and improving the overall power efficiency of the voltage regulator across broad current ranges (KSR).
Regarding dependent claim 4, Betser, teaches:
The method of claim 1 ([Title], [Abstract], [0003], [0083], [0097], & [0130]-[0132]), further comprising:
Betser, is silent in regard to:
measuring, using a second sensing circuit, an input voltage into the switched capacitor power conversion circuit;
wherein the output current offset is determined based on the measured input voltage.
However, Rader, further teaches:
measuring, using a second sensing circuit, an input voltage into the switched capacitor power conversion circuit (Fig. 1; [0049]: teaches utilizing a second, distinct sensing circuit (voltage sensor 134) dedicated to measuring the input voltage (VIN) entering the power conversion circuit);
wherein the output current offset is determined based on the measured input voltage ([0074]-[0075], [0080]-[0081], & [0089]: teaches that the output current offset (comprising the parasitic switching loss ISWLOSS and ripple loss IRIPPLE_LOSS) is calculated mathematically using the measured input voltage (Vin), therefore the offset used to estimate the final output current is determined based on the measured input voltage).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Rader’s dedicated input voltage sensor and voltage-dependent offset calculation into the switched capacitor circuit of Betser, representing the application of a known technique to a known device. The combination of Betser and Rader teaches measuring an input voltage using a second sensing circuit and determining the output current offset based on the measured input voltage. While Betser discloses a switched capacitor architecture and input current sensing, Rader teaches utilizing a secondary sensing circuit consisting of a voltage sensor 134 to measure the input voltage (Vin) and subsequently using this measured input voltage to directly calculate the switching and ripple loss offsets (ISWLOSS + IRIPPLE_LOSS). A POSITA would be motivated to make this combination to determine the true parasitic loss offsets that inherently fluctuate with the supply voltage. Making this modification yields the benefit of improved power efficiency calculations and highly accurate output current estimation across a broad range of operating conditions (KSR).
Regarding independent claim 5, Betser, teaches:
An apparatus for estimating an output current of a switched capacitor power conversion circuit (Fig. 2A; [Title], [Abstract], [0003], [0083], [0085]-[0086], [0097], [0130]-[0132], & [Claim 17]: discloses the foundational apparatus of a switched capacitor power conversion circuit (charged pump) and a system for estimating/measuring the output current based on the input circuit), the apparatus comprising ([Abstract], [0003], [0083], [0085]-[0086], & [0130]):
a first sensing circuit is configured to measure an input current into the switched capacitor power conversion circuit (Figs. 1A & 2A; [0085], [0118]-[0119], [0130]-[0132], [0148], [0161], [Claim 1], & [Claim 17]: teaches an apparatus with a “means for measuring a first current (I1) coming into the charge pump”, where the charge pump is a sensing circuit and the “Conventional Control Circuit” is the switched capacitor power conversion circuit in the charge pump); and
Betser, is silent in regard to:
a hardware processor is configured to calculate an estimated output current from the switched capacitor power conversion circuit as:
IOUT = (IIN x N) – Offset
wherein IOUT is the estimated output current, IIN is a measured input current, N is a multiplication or division factor of the switched capacitor power conversion circuit, and Offset is an output current offset.
However, Rader, further teaches:
The Examiner is combining Betser and Walter in view of Rader and Mehas, by implementing Mehas’s digital calculation circuit (hardware processor) to execute the algorithmic current estimations (Fig. 3b; [0038]-[0040], [0043], & [0045]).
a hardware processor is configured to calculate an estimated output current from the switched capacitor power conversion circuit as (Fig. 4; [0089]: teaches an apparatus utilizing a processor configured to calculate an estimated output current using the algebraic structure, dividing the measured input current by a factor and subtracting an offset):
IOUT = (IIN x N) – Offset (Fig. 4; [0089])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the digital calculation circuit taught by Mehas as the hardware processor in the combined system to execute the output current estimation formula of Rader. The addition of Mehas to the combination of Betser, Walter, and Radar addresses executing the calculation of the estimated output current using a hardware processor. Rader discloses the algorithmic formula for current estimation, Mehas teaches an apparatus utilizing a digital calculation circuit 380 equipped with memory 382 that receives digitized signals from analog-to-digital converters (365/370) to algorithmically compute the current of the power conversion circuit. A POSITA would be motivated to include this digital calculation hardware as a substitution to execute the algorithms digitally, eliminating systematic errors from second-order effects and transients via digital filtering. This hardware substitution yields the benefit of increasing overall measurement accuracy without requiring physical output sensing elements (KSR).
However, Walter, further teaches:
The Examiner is combining Betser and Walter in view of Rader by implementing Rader’s 1-to-1 match for the equation variables: IOUT maps to the estimated output current, IIN maps to the measured input current, 1/D maps to the division factor N, and the combined parasitic loss (ISWLOSS + IRIPPLE_LOSS) maps to the output current offset ([0005]-[0006], [0008], [0012]-[0016], [0020], [0023]-[0025], [0027], [0047], [0049], [0052], [0060]-[0065], [0077]-[0081], [0084], [0089], [0092], [0094]-[0095], [Claim 3]-[Claim 7], [Claim 12], [Claim 15]-[Claim 16], & [Claim 21]-[Claim 23]).
wherein IOUT is the estimated output current, IIN is the measured input current, N is a multiplication or division factor of the switched capacitor power conversion circuit ([Col. 2, ll. 13-19 & 43-49] & [Col. 4, ll. 34-40 & 56-67]: teaches the relationship N, multiple modes with different conversion factors, where a switched capacitor is operable in a plurality of modes, such as “operates in a “3-to-2” mode wherein the average input current is approximately two-thirds (2/3) the average output current”, rearranging the formula to IOUT = IIN * 1.5, or 1-to-1 mode, or 2-to-1 mode), and Offset is an output current offset.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Betser’s baseline switched capacitor charge pump and input current measurement by incorporating Walter’s multi-mode step-down charge pump 18 and Rader’s mathematical current estimation formula, which represents the application of known techniques to a known device. Walter cures Betser’s lack of conversion factors(varied operating modes) by teaching that a switched capacitor operates at fixed multiplication or division factors (N), such as a 3-to-2 mode yielding an average input current that is approximately two-thirds (2/3) of the average output current. Rader teaches an apparatus configured to calculate an estimated output current using the algebraic structure claimed, where the processor 110 computes IOUT = IIN/D - (ISWLOSS + IRIPPLE_LOSS), mapping the measured input current to IIN, the division factor 1/D to N, and the combined parasitic loss to the output current Offset. A POSITA would be motivated to combine these teaches to accurately estimate output current computationally by accounting for parasitic loss offsets across varying step-down conversion ratios. Implementing this combination would eliminate the need for a dedicated lossy output current sensor, reducing component area, lowering power dissipation, and improving the overall power efficiency of the voltage regulator across broad current ranges (KSR).
Regarding dependent claim 8, Betser, teaches:
The apparatus of claim 5 (Fig. 2A; [Title], [Abstract], [0003], [0083], [0085]-[0086], [0097], [0130]-[0132], & [Claim 17]), further comprising:
Betser, is silent in regard to:
a second sensing circuit is configured to measure an input voltage into the switched capacitor power conversion circuit,
wherein the output current offset is determined based on the measured input voltage.
However, Rader, further teaches:
a second sensing circuit is configured to measure an input voltage into the switched capacitor power conversion circuit (Fig. 1; [0049]: teaches configuring a second, distinct sensing circuit (voltage sensor 134) dedicated to measuring the input voltage (VIN) entering the power conversion circuit apparatus),
wherein the output current offset is determined based on the measured input voltage ([0074]-[0075], [0080]-[0081], & [0089]: teaches that the output current offset (comprising the parasitic switching loss ISWLOSS and ripple loss IRIPPLE_LOSS) is calculated mathematically using the measured input voltage (Vin), therefore the offset used to estimate the final output current is determined based on the measured input voltage).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Rader’s dedicated input voltage sensor and voltage-dependent offset calculation into the switched capacitor circuit of Betser, representing the application of a known technique to a known device. The combination of Betser and Rader teaches configuring a second sensing circuit to measure an input voltage and determining the output current offset based on the measured input voltage. While Betser discloses a switched capacitor apparatus capable of input current sensing, Rader teaches an electronic device utilizing a secondary sensing circuit (voltage sensor 134) configured to measure the input voltage (Vin) and subsequently uses this measured input voltage to calculate the switching and ripple loss offsets (ISWLOSS + IRIPPLE_LOSS). A POSITA would be motivated to make this modification to determine the true parasitic loss offsets that inherently fluctuate with the supply voltage. Implementing this predictable variation yields the benefit of improved power efficiency calculations and maintains highly accurate output current estimation across a broad range of operating conditions (KSR).
Regarding independent claim 11, Betser, teaches:
A method for one-time estimation of an output current offset for a switched capacitor power conversion circuit ([Title], [Abstract], [0083], [0085]-[0086], [0097], & [0130]-[0132]: discloses the foundational switched capacitor power conversion circuit), the method comprising ([Abstract] & [0083]):
The Examiner is combining Betser and Walter in view of Rader, by implementing Rader’s of performing a one-time “characterization mode” (or setup mode) to characterize the losses, which represent the output current offset, prior to operational/mission mode (Fig. 8; [0004], [0110], & [0119]).
measuring, using a first sensing circuit (Fig. 2A; [0083], [0130]-[0131], & [0148]: measures the input current I1 flowing into the charge pump (switched capacitor circuit) using a sensing circuit (resistor R1)), an input current into the switched capacitor power conversion circuit (Figs. 1A & 2A; [0083], [0085], [0118], [0130]-[0132], [0148], [0161], & [Claim 1]: the switched capacitor power conversion circuit is the “Conventional Control Circuit” in the charge pump);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the baseline switched capacitor charge pump of Betser by incorporating Rader’s dual current measurement and one-time characterization mode implementation, which represents the application of a known technique to a known device. While Betser establishes input current sensing, Rader teaches an alternate implementation utilizing dedicated sensing circuits to measure both the input current and the output current to perform a one-time estimation of an output current offset during a setup phase (characterization mode). Rader further teaches calculating this isolated offset using the explicit algebraic formula IOUT = IIN/D - (ISWLOSS + IRIPPLE_LOSS), which corresponds to calculating the offset according to the equation IOUT = (IIN x N) – Offset by mapping the measured currents to Iin and Iout, the division factor 1/D to N, and the combined parasitic loss to the calculate Offset. A POSITA would be motivated to combine these teachings to calculate and store the true parasitic loss offsets during an initial calibration phase. Making this combination yields the benefit of improving the overall power efficiency of the voltage regulator and ensuring highly accurate current estimation during subsequent mission-mode operations (KSR).
While Rader discloses the algorithmic formula for current estimation, Meyvaert teaches estimating the current provided to the load using a hardware processor 224 controlled by a program stored on computer-readable media containing instructions for performing these processes. A POSITA would be motivated to implement this software-based execution to ensure the complex offset and current estimation equations can be easily updated, scaled, or modified. This substitution provides the benefit of reducing manufacturing costs and improving overall system adaptability by avoiding inflexible physical hardware logic redesigns (KSR).
Betser, is silent in regard to:
measuring, using a second sensing circuit, an output current from the switched capacitor power conversion circuit; and
calculating, using a hardware processor, a first output current offset for the switched capacitor power conversion circuit according to an equation:
IOUT = (IIN x N) – Offset
wherein IOUT is the measured output current, IIN is the measured input current, N is a multiplication or division factor of the switched capacitor power conversion circuit, and Offset is the calculated first output current offset.
However, Rader, further teaches:
measuring, using a second sensing circuit, an output current from the switched capacitor power conversion circuit ([0061] & [0063]-[0064]: teaches an alternate implementation where distinct sensing circuits measure both the input current and the output current of the power conversion circuit); and
The Examiner is combining Betser and Walter in view of Rader and Mehas, by implementing Mehas’s digital calculation circuit (hardware processor) to execute the algorithmic characterizations (Fig. 3b; [0038]-[0040], [0043], & [0045]).
calculating, using a hardware processor, a first output current offset for the switched capacitor power conversion circuit according to an equation (Fig. 4; [0089] & [0094]-[0095]: teaches algebraic relationship (IOUT = IIN/D - (Offset), by measuring IIN and IOUT during characterization mode, the hardware processor mathematically calculates the isolated Offset (parasitic losses) according to this equation, dividing the measured input current by a factor and subtracting an offset):
IOUT = (IIN x N) – Offset (Fig. 4; [0089] & [0094]-[0095])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the digital calculation circuit taught by Mehas as the hardware processor in the combined system to execute the one-time offset estimation calculations of Rader, as a substitution, according to known methods. The addition of Mehas to the combination of Betser, Walter, and Radar addresses a hardware processor calculates the output current offset. While Rader discloses the algorithmic formula and characterization mode for offset current estimation, Mehas teaches utilizing a digital calculation circuit 380 equipped with memory 382 to algorithmically compute the currents and efficiency of the power conversion circuit, that receives digitized signals from analog-to-digital converters (365/370). A POSITA would be motivated to substitute analog calculation logic with this digital calculation hardware to execute the algorithms digitally, eliminating systematic errors from second-order effects and transients via digital filtering, yielding increased overall measurement and characterization accuracy (KSR).
However, Walter, further teaches:
The Examiner is combining Betser and Walter in view of Rader by implementing Rader’s 1-to-1 match for the equation variables: IOUT maps to the estimated output current, IIN maps to the measured input current, 1/D maps to the division factor N, and the combined parasitic loss (ISWLOSS + IRIPPLE_LOSS) maps to the calculated output current Offset ([0005]-[0006], [0008], [0012]-[0016], [0020], [0023]-[0025], [0027], [0047], [0049], [0052], [0060]-[0065], [0077]-[0081], [0084], [0089], [0092], [0094]-[0095], [Claim 3]-[Claim 7], [Claim 12], [Claim 15]-[Claim 16], & [Claim 21]-[Claim 23]).
wherein IOUT is the measured output current, IIN is the measured input current, N is a multiplication or division factor of the switched capacitor power conversion circuit ([Col. 2, ll. 13-19 & 43-49] & [Col. 4, ll. 34-40 & 56-67]: teaches that switched capacitor circuits operate with strict multiplication/division factors (N) for current ratios, the relationship N, multiple modes with different conversion factors, where a switched capacitor is operable in a plurality of modes, such as “operates in a “3-to-2” mode wherein the average input current is approximately two-thirds (2/3) the average output current”, rearranging the formula to IOUT = IIN * 1.5, or 1-to-1 mode, or 2-to-1 mode), and Offset is the calculated first output current offset.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Betser’s baseline switched capacitor charge pump by incorporating Walter’s multi-mode step-down charge pump 18 and Rader’s one-time characterization mode and dual current measurement implementation, which represents the application of known techniques to a known device. Walter cures Betser’s lack of varied operating modes by teaching that a switched capacitor circuit operates at fixed multiplication or division factors (N), such as a 3-to-2 mode yielding an average input current that is approximately two-thirds (2/3) of the average output current. Furthermore, Rader teaches an alternate implementation measuring both input and output currents to perform a one-time estimation of an output current offset during a setup phase, calculating offset using the explicit algebraic formula, where the processor 110 computes IOUT = IIN/D - (ISWLOSS + IRIPPLE_LOSS). This corresponds to calculating the offset according to the equation IOUT = (IIN x N) - Offset, mapping the measured input and output currents to Iin and Iout, the division factor 1/D to N, and the combined parasitic loss to the calculated output current Offset. A POSITA would be motivated to combine these teachings to accurately calculate and store true parasitic loss offsets across varying multiplication and division modes (step-down conversion ratios) during an initial calibration phase. Making this combination improves the overall power efficiency of the voltage regulator and ensures accurate current estimation during subsequent mission-mode operations, reducing component area, and lowering power dissipation (KSR).
Regarding dependent claim 15, Betser, teaches:
The method of claim 1 ([Title], [Abstract], [0003], [0083], [0097], & [0125]-[0132]), further comprising determining a value of Offset by measuring a difference between a measured current corresponding with lOUT and a measured current corresponding with IIN x N.
Betser, is silent in regard to:
further comprising determining a value of Offset by measuring a difference between a measured current corresponding with lOUT and a measured current corresponding with IIN x N.
However, Walter, further teaches:
The Examiner is combining Betser and Walter in view of Rader, by implementing Rader’s teachings of measuring both the input current (IIN) and the output current (IOUT) during characterization., algebraically rearranging Rade’s equation yields: (ISWLOSS + IRIPPLE_LOSS) = IIN/D - IOUT, therefore Rader teaches determining the offset (parasitic loss) by taking the mathematical difference between the measured current corresponding to IIN scaled by a factor (N = 1/D) and the measured current corresponding to IOUT (Fig. 4; [0063] & [0089]).
further comprising determining a value of Offset by measuring a difference between a measured current corresponding with lOUT and a measured current corresponding with IIN x N ([Col. 4, ll. 34-45]: establishes that switched capacitor circuits operate with conversion factors (N)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the multi-mode switched capacitor circuit of Betser and Walter by incorporating Rader’s characterization mode to determine a value of Offset by measuring a difference between a measured current corresponding with IOUT and a measured current corresponding with IIN x N, as the application of a known technique to a known device to improve similar devices. While Walter establishes that switched capacitor circuits operate with set conversion factors (N), Rader teaches a one-time characterization mode that measures both the input and output currents to algebraically isolate parasitic loss offsets. By rearranging Rader’s explicit current estimation equation IOUT = IIN/D - (ISWLOSS + IRIPPLE_LOSS), the calculated offset (ISWLOSS + IRIPPLE_LOSS) is mathematically determined by calculating the difference between the measured input current scaled by a factor corresponding to N(1/D) and the measured output current IOUT. A POSITA would be motivated to combine these teachings to calculate and store the true parasitic loss offsets across varying step-down or step-up conversion modes during an initial calibration phase. Making this combination yields the benefit of improving the overall power efficiency tracking of the voltage regulator and ensuring accurate sensorless current estimation during subsequent mission-mode operations (KSR).
Regarding dependent claim 17, Betser, teaches:
The method of claim 1 ([Title], [Abstract], [0003], [0011], [0083], [0097], & [0125]-[0132]), and receiving the input current from a DC input voltage supply (Fig. 2A; [Abstract], [0002], [0006]-[0007], [0011]-[0016], [0025], [0034], [0050], [0083], [0085]-[0086], [0119], [0121]-[0123], [0131]-[0132], [0135]-[0136], [0145], [0148], [0153], [0163]-[0164], [0167]-0167], [Claim 1], [Claim 3], [Claim 10], [Claim 13]-[Claim14], [Claim 16]-[Claim 17], [Claim 20]: teaches that the switched capacitor charge pumps receive their measured input current (I1) from a foundational direct current (DC) power supply voltage (e.g., Vdd)).
Betser, is silent in regard to:
further comprising determining the Offset through a one-time evaluation of the switched capacitor power conversion circuit,
However, Rader, further teaches:
further comprising determining the Offset through a one-time evaluation of the switched capacitor power conversion circuit (Fig. 8; [0110] & [0119]: teaches evaluating the power conversion circuit to determine the output current offset (parasitic switching and ripple losses) by performing a one-time evaluation during an initial “characterization mode” (or setup mode) prior to standard mission-mode operations),
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the charge pump apparatus of Betser by incorporating Rader’s one-time characterization mode to evaluate the circuit and determine the true offset, by the application of a known technique to a known device to improve similar devices. The combination of Betser and Rader teach determining the Offset through a one-time evaluation of the switched capacitor power conversion circuit and receiving the input current from a DC input voltage supply. While Betser discloses a baseline switched capacitor power conversion circuit that receives an input current from a standard DC voltage supply, Rader teaches performing a one-time evaluation during a dedicated “characterization mode” (or setup mode) prior to mission-mode operations to calculate and characterize parasitic losses. By mapping Rader’s characterized combined parasitic losses to the Offset, this one-time evaluation determines the baseline output current offset prior to execution. A POSITA would be motivated to make this combination to isolate non-linear parasitic behaviors across various DC input voltage levels before standard continuous operations. Implementing this predictable variation provides the benefit of accurate baseline dataset, improving the precision of the algorithm-based output current estimation during subsequent mission-mode operations (KSR).
Regarding dependent claim 18, Betser, teaches:
The method of claim 17 ([Title], [Abstract], [0003], [0011], [0083], [0097], & [0125]-[0132]), wherein the switched capacitor power conversion circuit ([0002]-[0004]: describes a “charge pump (CP)” which is a switched capacitor conversion circuit) is configured to provide a voltage conversion ([0002]-[0004], [0006], & [0011]-[0013]: the core function of the Betser circuit is voltage conversion) of a voltage of the DC input voltage supply to an output voltage node (Figs. 1A & 2A; [Abstract], [0002]-[0004], [0006]-[0007], [0010]-[0016], [0019], [0083]-[0086], [0096], [0104]-[0105], [0110]-[0111], [0119], [0121], [0132], [0135]-[0136], [0145], [0150], [0153], [0163]-[0164], [Claim 3], [Claim 10], [Claim 13]-[Claim 14], [Claim 17], & [Claim 20]: teaches that its switched capacitor circuit (charge pump) is configured to provide a direct voltage supply to create a higher or lower voltage at an output node)
Regarding dependent claim 19, Betser, teaches:
The method of claim 18 ([Title], [Abstract], [0003], [0011], [0083], [0097], & [0125]-[0132]), wherein the switched capacitor power conversion circuit ([0003]-[0004]) is configured to provide the output current (Figs. 1A & 2A; [0010]-[0017] & [0121]-[0123]: circuit is designed to deliver IOUT) to the output voltage node (Figs. 1A & 2A; [Abstract], [0043], [0083]-[0086], [0097], [0110]-[0112], [0121], [0130], [0132], [Claim 4], [Claim 13], [Claim 14], & [Claim 17]: current is delivered to the node labeled VOUT, figures further illustrate the arrow for IOUT leaving the node labeled VOUT).
Claims 2, 6, & 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Betser, in view of Walter, in view of Rader, in view of Mehas, and further in view of Meyvaert et al. (US 2020/0144908 A1, Pub. Date May 7, 2020, hereinafter, Meyvaert).
Regarding dependent claim 2, Betser, teaches:
The method of claim 1 (Fig. 2A; [Title], [Abstract], [0003], [0083], [0097], & [0130]-[0132]),
Betser, is silent in regard to:
wherein a value of Offset is non-zero,
However, Rader, further teaches:
wherein a value of Offset is non-zero ([0051], [0078]-[0080], [0089], [0094], & [0096]: teaches that the output current offset comprises physical switching and ripple losses (ISWLOSS + IRIPPLE_LOSS), these represent actual parasitic power lost as heat during the circuit’s operation, the value of the combined offset inherently represents a non-zero value),
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Betser’s charge pump to incorporate Rader’s non-zero offset calculation as a predictable variation. The combination of Betser and Rader teaches a value of Offset is non-zero. Betser discloses a baseline switched capacitor charge pump in Fig. 2A, Radar cures Betser’s lack of an explicit output current offset by teaching a formula where the offset comprises switching and ripple losses (ISWLOSS + IRIPPLE_LOSS). Since Rader’s offset accounts for real physical parasitic power lost as heat during the circuit’s operation ([0078]-[0080]), it inherently represents a non-zero value. A POSITA would be motivated to modify Betser’s charge pump to incorporate Rader’s non-zero offset calculation to accurately estimate the output current computationally by dynamically correcting for inevitable physical power losses, improving overall accuracy at low load conditions as noted by Rader ([0094]) (KSR).
Betser, and Rader, are silent in regard to:
wherein the hardware processor is configured to execute computer-readable instructions to calculate the estimated output current from the switched capacitor power conversion circuit.
However, Meyvaert, further teaches:
The Examiner is combining Betser in view of Mehas and Meyvaert, by implementing Mehas’s hardware processor utilized for current calculations configured to execute computer-readable instructions (software, programs, or instructions stored in memory or on computer-readable media) to perform the current estimation calculations ([0060]-[0061])
wherein the hardware processor is configured to execute computer-readable instructions to calculate the estimated output current from the switched capacitor power conversion circuit ([0030]-[0033]: teaches that the hardware processor utilized for current calculations configured to execute computer-readable instructions (software, programs, or instructions stored in memory or on computer-readable media) to perform the current estimation calculations).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the hardware processors executing Rader’s current estimation algorithms to utilize computer-readable instructions as taught by Meyvaert and Mehas as a substitution. Meyvaert and Mehas address wherein the hardware processor is configured to execute computer-readable instructions to calculate the estimated output current. Meyvaert teaches a hardware processor 224 that estimates output current and specifies that the processor is controlled by a program stored on computer-readable media containing instructions for performing the processes. This is further supported by Mehas, which teaches an electronic system 1300 executing specific software to perform specific calculations. A POSITA would be motivated to make this substitution to allow the complex current estimation calculations to be easily updated, scaled, or modified via software rather than requiring inflexible physical hardware redesigns, reducing manufacturing costs and improving system adaptability (KSR).
Regarding dependent claim 6, Betser, teaches:
The apparatus of claim 5 (Fig. 2A; [Title], [Abstract], [0003], [0083], [0085]-[0086], [0097], [0130]-[0132], & [Claim 17]),
Betser, is silent in regard to:
wherein a value of Offset corresponds with a current of the switched capacitor power conversion circuit when IOUT = 0,
However, Rader, further teaches:
wherein a value of Offset corresponds with a current of the switched capacitor power conversion circuit when IOUT = 0 ([0008], [0030], [0073]-[0074], [0078], & [0096]: teaches that the offset comprises switching losses (ISWLOSS) which do not contribute to the output current),
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Rader’s load independent parasitic offset calculation into the multi-mode switched capacitor circuit of Betser and Walter as an application of a known technique to a known device. The combination of Betser, Walter, and Rader teaches a value of Offset corresponds with a current of the switched capacitor power conversion circuit when IOUT = 0. Rader teaches that the offset comprises parasitic switching losses which are drawn independently of the load, meaning this offset inherently corresponds to the scaled input current consumed by the conversion circuit when the output current is zero (IOUT = 0). A POSITA would be motivated to use this specific offset to ensure the estimation algorithm accurately reflects the quiescent and switching currents inherently drawn during no-load states. Making this modification yields the benefit of accurate output current estimations and improved overall efficiency monitoring across the spectrum of different load conditions (KSR).
Betser, and Rader, are silent in regard to:
wherein the hardware processor is configured to execute computer-readable instructions to calculate the estimated output current from the switched capacitor power conversion circuit.
However, Meyvaert, further teaches:
The Examiner is combining Betser in view of Mehas and Meyvaert, by implementing Mehas’s hardware processor utilized for current calculations configured to execute computer-readable instructions (software, programs, or instructions stored in memory or on computer-readable media) to perform the current estimation calculations ([0060]-[0061])
wherein the hardware processor is configured to execute computer-readable instructions to calculate the estimated output current from the switched capacitor power conversion circuit ([0030]-[0033]: teaches that the hardware processor utilized for current calculations configured to execute computer-readable instructions (software, programs, or instructions stored in memory or on computer-readable media) to perform the current estimation calculations).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the hardware processors executing Rader’s current estimation algorithms to utilize computer-readable instructions as taught by Meyvaert and Mehas as a substitution. Meyvaert and Mehas address wherein the hardware processor is configured to execute computer-readable instructions to calculate the estimated output current. Meyvaert teaches a hardware processor 224 controlled by a program stored on computer-readable media to estimate output current, which is further supported by Mehas, teaching electronic circuitry executing specific software to perform power calculations. A POSITA would be motivated to implement this software-based execution to ensure complex offset and current estimation equations can be easily updated, scaled, or modified. This substitution provides the benefit of reducing manufacturing costs and improving overall system adaptability by avoiding inflexible physical hardware logic redesigns, reducing manufacturing costs and improving system adaptability (KSR).
Regarding independent claim 9, Betser, teaches:
A computer-readable medium storing processor-executable instructions for estimating an output current of a switched capacitor power conversion circuit (Figs. 2A & 2B; [Title], [Abstract], [0003], [0008], [0011], [0083], [0085]-[0086], [0096]-[0097], [0118]-[0119], [0121], [0130]-[0132], [0140]-[0148], [0161], & [0170]: discloses a “Control Circuit” which is a processor that performs the control functions with a “program” in the flash memory cells (computer-readable medium), containing/storing “processor-executable instructions” using the measured input current to determine the estimated output current from the switched capacitor power conversion circuit (Conventional Control Circuit in the charge pump), which requires a calculation by a processor),
The Examiner is combining Betser, Walter, and Rader in view of Meyvaert, by implementing Meyvaert’s the processing steps for estimating output current are stored as instructions on a computer-readable medium ([0030]-[0033]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the processing hardware executing Rader’s current estimation algorithms to utilize computer-readable instructions stored on a medium as taught by Meyvaert. The addition of Meyvaert addresses a computer-readable medium that stores processor-executable instructions for estimating the output current. While Rader discloses the algorithmic formula for current estimation, Meyvaert teaches estimating the current provided to the load using a hardware processor 224 controlled by a program stored on computer-readable media containing instructions for performing these processes. A POSITA would be motivated to implement this software-based execution to ensure the complex offset and current estimation equations can be easily updated, scaled, or modified. This substitution provides the benefit of reducing manufacturing costs and improving overall system adaptability by avoiding inflexible physical hardware logic redesigns (KSR)
Betser, is silent in regard to:
the processor-executable instructions comprising instructions to: calculate an estimated output current from the switched capacitor power conversion circuit as:
IOUT = (IIN x N) – Offset
wherein IOUT is the estimated output current, IIN is an input current into the switched capacitor power conversion circuit that is measured using a first sensing circuit, N is a multiplication or division factor of the switched capacitor power conversion circuit, and Offset is an output current offset.
However, Rader, further teaches:
The Examiner is combining Betser and Walter in view of Rader and Meyvaert, by implementing Meyvaert’s teachings of executing the programmatic calculations via instructions ([0030]-[0033]).
the processor-executable instructions comprising instructions to: calculate an estimated output current from the switched capacitor power conversion circuit as (Fig. 4; [0089]: teaches an algorithmic formula to calculate an estimated output current using the precise algebraic structure, dividing the measured input current by a factor and subtracting an offset):
IOUT = (IIN x N) – Offset (Fig. 4; [0089])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Rader’s specific algebraic output current calculation algorithm into the multi-mode switched capacitor circuit of Betser and Walter. The combination of Betser and Walter in view of Rader teaches calculating an estimated output current estimation formula as IOUT = (IIN x N) – Offset using measured input current and an output current offset. Rader teaches calculating an estimated output current using the mathematical formula IOUT = IIN/D - (ISWLOSS + IRIPPLE_LOSS), which maps input current IIN to Iin, the division factor 1/D to N, and the combined parasitic loss to the output current Offset. A POSITA would be motivated to make this combination to accurately estimate output current computationally by dynamically accounting for parasitic loss offsets. Implementing this calculation eliminates the need for a dedicated lossy output current sensor, reducing component area and overall power dissipation while maintaining high efficiency and increasing overall measurement accuracy (KSR).
However, Walter, further teaches:
The Examiner is combining Betser and Walter in view of Rader by implementing Betser’s teachings of measuring the input current using a first sensing circuit (resistor R1) (Fig. 2A; [0085]-[0086] & [0130]-[0131]) and Rader’s 1-to-1 match for the equation variables: IOUT maps to the estimated output current, IIN maps to the measured input current, 1/D maps to the division factor N, and the combined parasitic loss (ISWLOSS + IRIPPLE_LOSS) maps to the output current offset ([0005]-[0006], [0008], [0012]-[0016], [0020], [0023]-[0025], [0027], [0047], [0049], [0052], [0060]-[0065], [0077]-[0081], [0084], [0089], [0092], [0094]-[0095], [Claim 3]-[Claim 7], [Claim 12], [Claim 15]-[Claim 16], & [Claim 21]-[Claim 23]).
wherein IOUT is the estimated output current, IIN is an input current into the switched capacitor power conversion circuit that is measured using a first sensing circuit, N is a multiplication or division factor of the switched capacitor power conversion circuit ([Col. 2, ll. 13-19 & 43-49] & [Col. 4, ll. 34-40 & 56-67]: teaches the relationship N, multiple modes with different conversion factors, where a switched capacitor is operable in a plurality of modes, such as “operates in a “3-to-2” mode wherein the average input current is approximately two-thirds (2/3) the average output current”, rearranging the formula to IOUT = IIN * 1.5, or 1-to-1 mode, or 2-to-1 mode), and Offset is an output current offset.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the charge pump of Betser to incorporate the varying current multiplication and division factors of Walter and Rader’s mathematical current estimation formula as a predictable variation. The combination of Bester and Walter address that N is a multiplication or division factor of the switched capacitor power conversion circuit. While Betser discloses a baseline switched capacitor charge pump with input current measurement, Walter teaches a multi-mode switched capacitor step-down charge pump 18 where the ratio of average input current to average output current operates at a fixed multiplication or division factors, such as a 3-to-2 mode or a 2-to-1 mode. Rader teaches calculating an estimated output current using the algebraic structure claimed, where the processor 110 computes IOUT = IIN/D - (ISWLOSS + IRIPPLE_LOSS), mapping the measured input current to IIN, the division factor 1/D to N, and the combined parasitic loss to the output current Offset. A POSITA would be motivated to combine these teachings to accurately estimate output current computationally by accounting for parasitic loss offsets across varying step-down conversion rations. This combination would eliminate the need for a dedicated lossy output current sensor, reducing component area, lowering power dissipation, and improving the overall power efficiency of the voltage regulator across varying input voltage levels and low output current ranges (KSR).
Regarding dependent claim 10, Betser, teaches:
The computer-readable medium of claim 9 (Figs. 2A & 2B; [Title], [Abstract], [0003], [0008], [0011], [0083], [0085]-[0086], [0096]-[0097], [0118]-[0119], [0121], [0130]-[0132], [0140]-[0148], [0161], & [0170]),
The Examiner is combining Betser, Walter, and Rader in view of Meyvaert, by implementing Meyvaert’s the processing steps for estimating output current are stored as instructions on a computer-readable medium ([0030]-[0033]). Please refer back to independent claim 9 for motivation to combine rationale.
Betser, is silent in regard to:
wherein the output current offset is determined based on an input voltage into the switched capacitor power conversion circuit that is measured using a second sensing circuit.
However, Rader, further teaches:
wherein the output current offset is determined based on an input voltage ([0074]-[0075], [0080]-[0081], & [0089]: teaches that the output current offset (comprising the parasitic switching loss ISWLOSS and ripple loss IRIPPLE_LOSS) is calculated mathematically using the measured input voltage (Vin), therefore the offset used to estimate the final output current is determined based on the measured input voltage) into the switched capacitor power conversion circuit that is measured using a second sensing circuit (Fig. 1; [0049]: teaches utilizing a second, distinct sensing circuit (voltage sensor 134) dedicated to measuring the input voltage (VIN) entering the power conversion circuit).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Rader’s dedicated input voltage sensor and voltage-dependent offset calculation into the switched capacitor circuit of Betser, representing the application of a known technique to a known device. The combination of Betser and Rader teaches measuring an input voltage using a second sensing circuit and determining the output current offset based on the measured input voltage. While Betser discloses a switched capacitor charge pump architecture capable of input current sensing, Rader teaches utilizing a secondary sensing circuit consisting of a voltage sensor 134 configured to measure the input voltage (Vin) and subsequently using this measured input voltage to directly calculate the switching and ripple loss offsets (ISWLOSS + IRIPPLE_LOSS). A POSITA would be motivated to make this combination to determine the true parasitic loss offsets that inherently fluctuate with the supply voltage. Implementing this predictable variation yields the benefit of improved power efficiency calculations and highly accurate software-executed output current estimation across a broad range of operating conditions (KSR).
Claims 3, 7, & 16 are rejected under 35 U.S.C. 103 as being unpatentable over Betser, in view of Walter, in view of Rader, in view of Mehas, and further in view of de Cremoux (US 2023/0155471 A1, Fil. Date Nov. 16, 2021, hereinafter, de Cremoux).
Regarding dependent claim 3, Betser, teaches:
The method of claim 1 ([Title], [Abstract], [0003], [0083], [0097], & [0130]-[0132]),
Betser, is silent in regard to:
wherein a value of Offset corresponds with a mean value of a plurality of values each corresponding with one of range of input voltage values,
However, de Cremoux, further teaches:
The Examiner is combining Betser and Rader in view of de Cremoux, by implementing Rader’s offset representing parasitic loss that is directly dependent on the input voltage (VIN) ([0077] & [0079]-[0081]).
wherein a value of Offset corresponds with a mean value of a plurality of values each corresponding with one of range of input voltage values (Fig. 12; [0167], [0183]-[0184], & [0218]: teaches calibrating and extracting an offset digitally across a range of input voltages (VIN from 2.7 V to 5.5 V) and computing a mean value from the plurality of captured sampled values),
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the characterized offset algorithm of Rader by calculating and storing a mean value of the offset across an operating input voltage range as taught by de Cremoux as a predictable variation. The combination of Betser, Rader, and de Cremoux teach wherein a value of Offset corresponds with a mean value of a plurality of values each corresponding with one of a range of input voltage values. While Rader teaches an offset calculation that is directly dependent on individual voltage values, de Cremoux teaches extracting an offset in the digital domain across a range of input voltages (VIN from 2.7 V to 5.5 V) to capture a history of samples and derive a mean value. A POSITA would be motivated to use this pre-calculated mean offset value across the voltage range to reduce real-time computational load on the processor and improve offset calibration accuracy. This combination yields the benefit of improved efficiency and maintained power measurement accuracy across varying supply conditions without requiring complex analog averaging hardware (KSR).
Betser, and de Cremoux, are silent in regard to:
and wherein the hardware processor comprises an integrated circuit configured to calculate the estimated output current from the switched capacitor power conversion circuit.
However, de Mehas, further teaches:
The Examiner is combining Betser and Rader in view of Mehas, by implementing Rader’s teaching of utilizing a voltage regulator integrated circuit 402 coupled with a processor for estimating output current (Fig. 4; [0083]-[0089]).
and wherein the hardware processor comprises an integrated circuit configured to calculate the estimated output current from the switched capacitor power conversion circuit ([0024] & [0039]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement Rader’s hardware processor physically as a consolidated integrated circuit as taught by Mehas as a substitution. The combination of Betser, Rader, and Mehas addresses the limitation wherein the hardware processor comprises an integrated circuit configured to calculate the estimated output current from the switched capacitor power conversion circuit. While Rader discloses using a hardware processor to execute calculations for the estimated output current, Mehas teaches that a digital calculation circuit 380 used to determine currents is formed within an integrated circuit containing regulator circuitry. A POSITA would be motivated to integrated the digital processing hardware and the switched capacitor power conversion circuit onto a single integrated circuit to reduce overall manufacturing costs. Furthermore, this hardware consolidation minimizes the physical device footprint and decreases parasitic signal delays between components, yielding improved power conversion efficiency (KSR).
Regarding dependent claim 7, Betser, teaches:
The apparatus of claim 5 (Fig. 2A; [Title], [Abstract], [0003], [0083], [0085]-[0086], [0097], [0130]-[0132], & [Claim 17]),
Betser, is silent in regard to:
wherein the output current offset is related to current consumption associated with one or more components of the switched capacitor power conversion circuit,
wherein the hardware processor comprises an integrated circuit configured to calculate the estimated output current from the switched capacitor power conversion circuit.
However, Rader, further teaches:
wherein the output current offset is related to current consumption associated with one or more components of the switched capacitor power conversion circuit ([Abstract], [0005]-[0009], [0012], [0014]-[0016], [0018], [0022]-[0024], [0026]-[0034], [0047], [0056]-[0064], [0073]-[0075], [0077]-[0079], [0081], [0089], [0094]-[0095], [0107]-[0108], [0117], [0120]-[0121], [Claim 2], [Claim 3], [Claim 6]-[Claim 7], [Claim 10], [Claim 15], [Claim 17], [Claim 19]-[Claim 23], [Claim 25], & [Claim 27]-[Claim 30]: teaches that the calculated offset inherently relates to the power and current consumed by specific physical components within the circuit (the parasitic switching loss associated with the internal switches)),
The Examiner is combining Betser, Walter, Rader, and de Cremoux in view of Mehas, by implementing Mehas’s teachings that the digital calculation circuit (hardware processor) used to algorithmically determine estimated currents is formed within an integrated circuit ([0024], [0026], [0039], & [0056])
wherein the hardware processor comprises an integrated circuit configured to calculate the estimated output current from the switched capacitor power conversion circuit (Fig. 4; [0083]-[0089]: teaches utilizing a voltage regulator integrated circuit 402 coupled with a processor for estimating current).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the algorithmic hardware processor of Rader physically as an integrated circuit as taught by Mehas, as a substitution, according to known methods. The addition of Mehas to the combination addresses wherein the hardware processor comprises an integrated circuit configured to calculate the estimated output current. While Rader discloses using a processor to calculate output current computationally, Mehas teaches that a digital calculation circuit used to determine currents is formed directly within an integrated circuit containing the regulator circuitry. A POSITA would be motivated to consolidate the digital processing hardware and the switched capacitor conversion circuit onto a single integrated circuit to reduce manufacturing costs, minimize physical device footprint, and decrease parasitic signal delays between discrete components (KSR).
Betser, and Rader, are silent in regard to:
when a ratio of a value of Offset to a value of IIN is about 1% or less, and
However, de Cremoux, further teaches:
when a ratio of a value of Offset to a value of IIN is about 1% or less ([0182], [0185]: teaches that the current consumption (offset) associated with the system’s components is nominally 7 µA against a 3.5 A input/output current. Calculating this ratio yields 7 µA / 3.5 A = 0.0002%, and 0.0002% is lower than 1%), and
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the parasitic offset estimation algorithms of Rader to account for the highly efficient, low-consumption component parameters taught by de Cremoux as a predictable variation. The combination of Betser, Rader, and de Cremoux teaches wherein the output current offset relates to component current consumption, with a ratio of Offset to IIN being about 1% or less. While Rader teaches that the offset comprises parasitic power losses associated with internal circuit components like FETs, de Cremoux teaches minimizing this component current consumption such that the system only consumes 7 µA nominally against a 3.5 A full-scale current. This nominal consumption establishes the mathematical ratio of 0.0002%, satisfying the limitation of being 1% or less. A POSITA would be motivated to make this combination to reduce quiescent power loss and optimize overall power efficiency while maintaining accurate current estimation at full load conditions (KSR).
Regarding dependent claim 16, Betser, teaches:
The method of claim 1 ([Title], [Abstract], [0003], [0083], [0097], & [0125]-[0132]),
Betser, is silent in regard to:
further comprising determining the Offset through computer simulation,
However, de Cremoux, further teaches:
further comprising determining the Offset through computer simulation (Fig. 12; [0167], [0175]-[0176], [0179], [0181]-[0185], [0216]-[0220], & [0222]: teaches determining and extracting precise offset and deviation values for the system’s baseline characterization by executing a computer simulation on the full transistor implementation),
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the offset characterization method of Rader by determining the offset through computer simulation prior to programming it into the memory circuit, as taught by de Cremoux, as the application of a known technique to a known device to improve similar devices. The combination of Betser and Rader in view of de Cremoux teach determining the Offset through computer simulation. While Rader discloses determining and storing the baseline offset representing parasitic losses, de Cremoux teaches determining and extracting offset and deviation values by running a computer simulation on the full transistor implementation of the system. A POSITA would be motivated to utilize computer simulations to extract nominal offset values across varying voltages because it models parasitic non-linearities without requiring physical test benches for every individually manufactured unit. This substitution yields the benefit of reducing manufacturing calibration time and costs while ensuring accurate baseline values are programmed into the memory (KSR).
Betser, and de Cremoux, are silent in regard to:
and programming a value of Offset in a memory for subsequent access.
However, Rader, further teaches:
and programming a value of Offset in a memory for subsequent access (Fig. 8; [0087], [0094], & [0119]-[0120]: teaches that the characterized values representing the output current offset (switching loss and ripple loss) are programmed and saved into a memory circuit 108 during the initial setup mode, allowing the processor to subsequently access these values during operational mission mode to estimate the output current).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the charge pump apparatus of Betser by incorporating Rader’s memory circuit 108 to program and store the offset value as a predictable variation. The combination of Betser and Rader teach programming a value of the Offset in a memory circuit for subsequent access. Betser discloses the foundational switched capacitor power conversion circuit, while Rader teaches characterizing the parasitic switching and ripple losses ( which act as the Offset) and saving this characterized information in a memory 108 for subsequent access by the processor 110. A POSITA would be motivated to make this modification to ensure that baseline parasitic loss data is available for rapid sensorless output current estimation algorithms during subsequent mission-mode operations. Implementing this pre-programmed memory access provides the benefit of reducing real-time computational overhead and component count on the circuit (KSR).
Claims 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Betser, in view of Walter, in view of Rader, in view of Mehas, in view of de Cremoux, and further in view of Cousineau (US 2015/0326021 A1 Pub. Date Nov. 12, 2015, hereinafter, Cousineau).
Regarding dependent claim 12, Betser, teaches:
The method of claim 11 ([Title], [Abstract], [0083], [0085]-[0086], [0097], & [0130]-[0132]), further comprising:
The Examiner is combining Betser and Walter in view of Rader, by implementing Rader’s of performing a one-time “characterization mode” (or setup mode) to characterize the losses, which represent the output current offset, prior to operational/mission mode (Fig. 8; [0004], [0110], & [0119]). Please refer back to independent claim 11 for motivation to combine rationale.
Betser, is silent in regard to:
calculating, using the hardware processor, a second output current offset for the switched capacitor power conversion circuit
However, Rader, further teaches:
The Examiner is combining Betser, Walter, and Rader in view of Mehas and Cousineau, by implementing Mehas’s teachings utilizing a hardware processor (digital calculation circuit 380) to algorithmically execute calculations to determine finalized (averaged) parameters (Fig. 3(b); [0024], [0026], [0038]-[0039], [0044], & [0056]) and Cousineau’s teachings of utilizing a hardware processor (digital calculation circuit or local modular balancing unit) to algorithmically execute repetitive calculations on averaged values to determine finalized operation corrections (offsets) ([0152], [0156], & [0161]).
calculating, using the hardware processor, a second output current offset for the switched capacitor power conversion circuit (Fig. 4; [0083]-[0089]: teaches utilizing a processor to compute the offset)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Rader’s one-time characterization mode by calculating a plurality of first offsets at different input currents and mathematically averaging them to determine a finalized second offset as taught by de Cremoux. The combination of Betser, Rader, and de Cremoux teaches calculating a second output current offset by averaging a plurality of calculated first output current offsets each corresponding to a different measured input current. While Rader discloses calculating a baseline offset during a one-time characterization mode, representing parasitic losses, de Cremoux explicitly teaches extracting accurate offset values by testing and capturing multiple sample points (representing different operational current loads) to compute a finalized mean value. Mehas teaches utilizing a digital calculation circuit to algorithmically average sampled parameters and Cousineau teaches local control values modules containing dedicated hardware units configured to average operational data to output cyclic ratio corrections. A POSITA would be motivated to make this modification to smooth out random signal noise and account for parasitic non-linearities that fluctuate across the entire operating current range. Implementing this combination yields the benefit of establishing an accurate generalized baseline offset, improving the overall precision of the output current estimation during subsequent mission-mode operations (KSR).
Betser, and Rader, are silent in regard to:
by averaging a plurality of calculated first output current offsets each corresponding with a different measured input current.
However, de Cremoux, further teaches:
The Examiner is combining Betser, Walter, and Rader in view of Mehas, de Cremoux, and Cousineau, by implementing Mehas’s teachings utilizing the digital sampling and averaging multiple data points to compute finalized values (Fig. 3(b); [0024], [0026], [0038]-[0040]) and Cousineau’s teaching the digital sampling and mathematical averaging of multiple measured data points to compute finalized values (0152], [0156], & [0161]) .
by averaging a plurality of calculated first output current offsets each corresponding with a different measured input current ([Abstract], [0005], [0038], [0042], [0055], [0129], [0145], [0167] & [0182]-[0185], [0227], [0241], [0248], [0253]-[0254], [Claim 1], [Claim 2], [Claim 5], [Claim 15], [Claim 17]-[Claim18], & [Claim 24]: teaches that extracting a highly accurate offset requires testing multiple “points” (which inherently represent different operation currents/loads). Applying this to Rader’s characterization mode yields calculating a finalized (“second”) offset by averaging a plurality of individual (“first”) offsets captured at different input currents).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the digital calculation and balancing circuits taught by Mehas and Cousineau as the hardware processor to execute the offset sampling and mathematical averaging calculations as an application of a known technique to a known device to improve similar devices. The addition of Mehas and Cousineau to the combination addresses a hardware processor is used to calculate the second output current offset by averaging the plurality of calculated first offsets. While Rader and de Cremoux disclose characterizing the offset across multiple sample points in the digital domain, Mehas teaches an apparatus utilizing a digital calculation circuit 380 (hardware processor) equipped with memory to algorithmically average sampled parameters, and Cousineau teaches local control modules containing dedicated hardware units configured to average operational data to output cyclic ratio corrections. A POSITA would be motivated to implement this digital hardware substitution to rapidly process multiple data points and automatically eliminate systematic errors or transients via digital filtering. This hardware substitution yields the benefit of increasing overall measurement and characterization accuracy without relying on complex analog averaging circuits (KSR).
Regarding dependent claim 13, Betser, teaches:
The method of claim 11 ([Title], [Abstract], [0083], [0085]-[0086], [0097], & [0130]-[0132]), further comprising:
The Examiner is combining Betser and Walter in view of Rader, by implementing Rader’s of performing a one-time “characterization mode” (or setup mode) to characterize the losses, which represent the output current offset, prior to operational/mission mode (Fig. 8; [0004], [0110], & [0119]). Please refer back to independent claim 11 for motivation to combine rationale.
Betser, is silent in regard to:
calculating, using the hardware processor, a set of second output current offsets, each calculated second output current offset being calculated for a different input voltage; and
However, Rader, further teaches:
The Examiner is combining Betser, Walter, and Rader in view of Mehas, de Cremoux, and Cousineau, by implementing Mehas’s teachings utilizing a hardware processor (digital calculation circuit 380) to algorithmically execute these calculations (Fig. 3(b); [0024], [0026], [0038]-[0039], [0044], & [0056]), de Cremoux’s teachings of extracting an accurate offset requiring testing multiple points across a varying range of input voltages (VIN from 2.7 V to 5.5 V) ([0167] & [0182]-[0183]), and Cousineau’s teachings of utilizing a hardware processor (e.g., a digital calculation circuit or local hardware module) to algorithmically execute these corrective parameter calculations ((0152], [0156], & [0161]).
calculating, using the hardware processor, a set of second output current offsets, each calculated second output current offset being calculated for a different input voltage (Fig. 4; [0080] & [0083]-[0089]: teaches utilizing a processor to compute the offset based on the input voltage (VIN)); and
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Rader’s offset characterization by using Mehas’s hardware processor to calculate a set of multiple offsets at different individual input voltages as taught by Cremoux. The combination of Betser, Rader, De Cremoux, and Mehas teaches calculating, using the hardware processor, a set of second output current voltages, each calculated second output current offset being calculated for a different input voltage. While Rader discloses using a processor to calculate a baseline offset representing parasitic losses based on an input voltage during a characterization mode, de Cremoux teaches extracting accurate offset data by capturing samples across a varying range of input voltages (VIN from 2.7 V to 5.5 V). Furthermore, Mehas teaches utilizing a digital calculation circuit 380 (hardware processor) equipped with memory to algorithmically execute repetitive sampled calculations. A POSITA would be motivated to make this modification to account for parasitic non-linearities and dynamic component behaviors that fluctuate across the entire operating voltage range, increasing the overall accuracy of the baseline characterization (KSR).
Betser, and Rader, are silent in regard to:
calculating, using the hardware processor, a third output current offset as an average of the set of second output current offsets.
However, de Cremoux, further teaches:
The Examiner is combining Betser, Walter, and Rader in view of Mehas, de Cremoux, and Cousineau, by implementing Mehas’s teachings utilizing a hardware processor (digital calculation circuit 380) to mathematically average multiple sampled data points to computer finalized values (Fig. 3(b); [0024], [0026], [0038]-[0040], [0044], & [0056]) and Cousineau’s hardware units configured to “determine the locally averaged” parameters (currents or voltages) to output finalized cyclic corrections/offsets ([0152], [0156], [0161], & [0327]).
calculating, using the hardware processor, a third output current offset as an average of the set of second output current offsets (Fig. 12; [Abstract], [0005], [0038], [0042], [0055], [0129], [0145], [0167] & [0182]-[0185], [0227], [0241], [0248], [0253]-[0254], [Claim 1], [Claim 2], [Claim 5], [Claim 15], [Claim 17]-[Claim18], & [Claim 24]: teaches capturing multiple sample data points across the tested voltage range to compute a “mean” (average) value).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the digital hardware calculation circuits as taught by Mehas and Cousineau as the hardware processor to mathematically average the set of calculated second output current offsets to generate a finalized third output current offset, representing the application of a known technique to a known device to improve similar devices. The combination of Betser, Rader, de Cremoux, Mehas, and Cousineau teaches calculating, using the hardware processor, a third output current offset as an average of the set of second output current offsets. Building upon the multiple offsets calculated above, de Cremoux teaches computing a mean (average) value from a plurality of captured sample points, while Mehas teaches utilizing the digital calculation circuit 380 to algorithmically average sampled parameters. Cousineau reinforces this by disclosing control modules containing dedicated hardware units (such as local units 264, 266, 1266) configured to determine “locally averaged” parameters to calculate corrected cyclic ratios and offsets. A POSITA would be motivated to implement this digital hardware averaging technique to rapidly process multiple data points, smooth out random signal noise and automatically eliminate systematic errors or transients via digital filtering. Implementing this hardware configuration yields the benefit of increasing overall measurement accuracy without relying on complex analog averaging circuits (KSR).
Regarding dependent claim 14, Betser, teaches:
The method of claim 11 ([Title], [Abstract], [0083], [0085]-[0086], [0097], & [0130]-[0132]), further comprising:
The Examiner is combining Betser and Walter in view of Rader, by implementing Rader’s of performing a one-time “characterization mode” (or setup mode) to characterize the losses, which represent the output current offset, prior to operational/mission mode (Fig. 8; [0004], [0110], & [0119]). Please refer back to independent claim 11 for motivation to combine rationale.
Betser, is silent in regard to:
calculating, using the hardware processor, a set of second output current offsets, each calculated second output current offset being calculated for a different input voltage; and
calculating, using the hardware processor, a set of third output current offsets, each third output current offset corresponding to a different range of input voltage.
However, Rader, further teaches:
The Examiner is combining Betser, Walter, and Rader in view of Mehas, de Cremoux, and Cousineau, by implementing de Cremoux’s teachings that extracting an accurate offset requires capturing data points across a varying range of individual input voltages (e.g., VIN from 2.7 V to 5.5 V) ([0167] & [0182]-[0183]), Mehas’s teachings of utilizing a hardware processor (digital calculation circuit 380) to algorithmically execute these calculations (Fig. 3(b); [0024], [0026], [0038]-[0040], [0044], & [0056]), and Cousineau’s teachings utilizing a hardware processor (e.g., a digital calculation circuit or local hardware module) to algorithmically execute these corrective parameter calculations and disclosing hardware units configured to determine “locally averaged” parameters to output finalized cyclic corrections/offsets ([0152], [0156], [0161], & [0327]).
calculating, using the hardware processor, a set of second output current offsets, each calculated second output current offset being calculated for a different input voltage (Fig. 4; [0080] & [0083]-[0089]: teaches utilizing a processor to compute the offset based on the input voltage (VIN)); and
calculating, using the hardware processor, a set of third output current offsets, each third output current offset corresponding to a different range of input voltage ([0094]: teaches saving the characterized offset data. By grouping the point-specific (second) offsets into bins, the hardware processor mathematically calculates and stores generalized (third) offsets to different operational voltage ranges).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the one-time characterization mode of the switched capacitor apparatus of Betser and Radar by capturing samples across a varying range of individual input voltages (e.g., VIN from 2.7 V to 5.5 V) as taught by de Cremoux, and utilizing the digital hardware calculation circuits taught by Mehas and Cousineau to group and mathematically average these point-specific offsets into distinct input voltage ranges. While Rader discloses calculating a baseline offset using processor 110, modifying this using de Cremoux satisfies calculating, using the hardware processor, a set of second output current offsets, each calculated second output current being calculated for a different input voltage. Furthermore, utilizing the digital calculation circuit 380 of Mehas and the local hardware units (264, 266. 1266) of Cousineau enables calculating, using the hardware processor, a set of third output current offsets, each third output current offset corresponding to a different range of input voltage. A POSITA would be motivated to combine these teachings to implement this digital binning and averaging technique to optimize lookup table efficiency and automatically eliminate random signal noise via digital filtering. This hardware configuration yields the benefit of reducing the memory and computational burden on the hardware processor while ensuring rapid, accurate baseline offset retrieval across varying operational supply nodes during mission mode (KSR).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Betser, in view of Walter, in view of Rader, in view of Mehas, in view of Meyvaert, in view of Cousineau, and further in view of Kojima et al. (US 2012/0300501 A1, Pub. Date, hereinafter, Kojima).
Regarding dependent claim 20, Betser, teaches:
The method of claim 19 ([Title], [Abstract], [0003], [0011], [0083], [0097], & [0125]-[0132]),
Betser, is silent in regard to:
controlling operation of the switched capacitor power conversion circuit based at least in part on the estimated output current;
detecting a fault in operation of the switched capacitor power conversion circuit based at least in part on the estimated output current; and/or
controlling another electrical component based at least in part on the estimated output current.
However, Kojima, further teaches:
The Examiner is combining Betser in view of Rader and Kojima, by implementing Rader’s teachings of algorithmic output current estimation, the control logic inherently controls the circuit’s operation based at least in part on the estimated output current ([0089]).
controlling operation of the switched capacitor power conversion circuit based at least in part on the estimated output current ([Abstract], [0015]-[0018], [0021], [0033]-[0034], [0054], [0060]-[0062], [0066], [Claim 1], [Claim 3]-[Claim 4], & [Claim 6]-[Claim 7]: teaches estimating the load (output) current and actively controlling the operation of the power conversion circuit (by adjusting the supplied power via converter turn-on times or frequency) based on that estimated output current condition);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Kojima’s load-based control logic into the power conversion circuit of Betser and Rader, representing the application of a known technique to a known device to improve similar devices. The combination of Betser, Rader, and Kojima teaches controlling the operation of the switched capacitor power conversion circuit based at least in part on the estimated output current. While Betser and Rader establish a switched capacitor circuit with algorithmic output current estimation, Kojima teaches estimating a load current and subsequently utilizing a controller to adjust the supplied power by modifying the turn-on time or operating frequency on the converter based on that estimated current. A POSITA would be motivated to make this combination to dynamically adapt the circuit’s power delivery to real-time load conditions, such as automatically reducing power output when the estimated load is light. Implementing this predictable variation provides the benefit of establishing an efficient closed-loop control system that minimizes power dissipation without relying on lossy physical current sensors (KSR).
However, Cousineau, further teaches:
The Examiner is combining Betser in view of Rader and Cousineau, by implementing Rader’s teachings of algorithmic output current estimation, the control logic inherently controls the circuit’s operation based at least in part on the estimated output current ([0089]).
detecting a fault in operation of the switched capacitor power conversion circuit based at least in part on the estimated output current ([0219], [0249]-[0250], & [0388]: teaches monitoring module branch currents and altering operation in the event a defect (fault) appears in a switching cell. Applying this fault detection and reconfiguration logic to the estimated output current of Rader teaches detecting a fault in the operation of the circuit based on the estimated current); and/or
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Cousineau’s fault detection and reconfiguration logic into the control scheme of Betser and Rader, utilizing the estimated output as the threshold metric for identifying abnormal operating conditions. The addition of Cousineau to the combination teaches detecting a fault in the operation of the switched capacitor power conversion circuit based at least in part on the estimated output current. While Rader teaches algorithmically estimating the output current, Cousineau teaches monitoring current values across converter branches to detect defects or faults in switching cells and subsequently bypassing the faulty modules. A POSITA would be motivated to implement this combination to automatically identify short circuits, overcurrent states, or component defects in real time. This predictable variation yields the benefit of improving the safety, reliability, and fault-tolerance of the power conversion circuit during mission-mode operations (KSR).
However, Meyvaert, further teaches:
The Examiner is combining Betser in view of Rader and Meyvaert, by implementing Rader’s teachings of algorithmic output current estimation, the control logic inherently controls the circuit’s operation based at least in part on the estimated output current ([0089]).
controlling another electrical component based at least in part on the estimated output current ([0030]-[0031]: teaches estimating the current provided on the downstream electrical component (load). Applying this downstream hardware processor regulation to Rader ensures that the power provided to another electrical component is subsequently controlled based on the estimated output current).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the hardware processor executing Rader’s current estimation algorithms to subsequently control the power delivery to another downstream electrical component as taught by Meyvaert, representing a substitution. The combination of Betser, Rader, and Meyvaert teaches controlling another electrical component based at least in part on the estimated current. While Rader discloses calculating the estimated output current, Meyvaert teaches estimating the current provided to a downstream electrical component, specifically the load, using a hardware processor. A POSITA would be motivated to make this modification to ensure that connected load devices are not damaged by excessive power dissipation or overcurrent conditions. This combination yields the benefit of enabling strict load regulation and protecting sensitive downstream electrical components from unexpected power surges (KSR).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUGO NAVARRO whose telephone number is (571)272-6122. The examiner can normally be reached Monday-Friday 08:30-5:00 pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eman Alkafawi can be reached at 571-272-4448. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HUGO NAVARRO/ Examiner, Art Unit 2858 September 30, 2026
/EMAN A ALKAFAWI/Supervisory Patent Examiner, Art Unit 2858 9/30/2026
