DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending for examination
This office is FINAL
Response to Arguments
Applicants’ arguments filed [ have been fully considered but they are not persuasive.
Applicants argue against the references individually. The Examiner respectfully disagrees because one cannot show non-obviousness by arguing against references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicant argues that Hoekstra does not teach "a second memory controller that is connected in a data path between the first memory controller and an interface," because Hoekstra's FIG. 1 shows memory controller 104 directly coupled to secondary memory 108. The Examiner respectfully disagrees. Applicants address Hoekstra in isolation and do not account for the combination. Kalyanasundharam PP 0012 teaches a port controller including a light-weight memory protocol controller to send requests to and receive responses from a memory through the CCIX port, and the port controller 412 (FIG. 4) is connected in the data path between system memory controller 405 (via data interconnect fabric 404) and the CCIX port. See also Kalyanasundharam FIG. 5, where light-weight memory protocol controller 570 is situated between the data interconnect fabric and CCIX port 522, which connects to external bus 529. This is "a second memory controller that is connected in a data path between the first memory controller and an interface."
Applicant further argues that Hoekstra does not teach "an interface to receive a request, from a first memory controller associated with a primary memory, for information comprising a recovery code," because Hoekstra PP 0034 describes method processes, not an interface receiving a request. The Examiner respectfully disagrees. Hoekstra PP 0017 teaches: "Memory Controller 104 is coupled to communicate with flash memory 106, secondary memory 108, RAM 110 and ROM 112 via one or more buses." This bus coupling is the interface. Hoekstra PP 0027 teaches that error correction bits are placed in secondary memory 108, and Hoekstra PP 0034 teaches that process 608 attempts to correct errors using the ECC information in secondary memory 108. For process 608 to use ECC information from secondary memory 108, memory controller 104 must request and receive that information over the bus interface. Applicant's distinction between a method process and an interface is not commensurate with the claim scope. Criss PP 0025 teaches that the recovery code is used for modifying an error on the primary memory.
Applicant further argues that claims 2-15 and 17-19 depend from claims 1 or 16 and therefore incorporate all of the terms and features of their base claims. The Examiner respectfully disagrees for the reasons set forth above, because the base claims are unpatentable over the combination of Hoekstra, Criss, and Kalyanasundharam.
With respect to the amendment to claim 1, the Examiner notes that original claim 7 recited a data path between the first and second memory controllers, while amended claim 1 recites a data path between the first memory controller and an interface, with the second controller situated in that path. These are not the same limitation verbatim, and the amendment changed the scope of the claimed data path. The new ground of rejection is therefore necessitated by the amendment. See MPEP 706.07(a).
Applicant's remaining arguments, including the reservations of right, no-waiver statements, and characterizations of claim scope, do not overcome the rejections. The rejections of claims 1-20 are maintained.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or
nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) [ 1-20 ] are rejected under 35 U.S.C. 103 as being unpatentable over [ Hoekstra et al (US Pub No. 20150318871), hereinafter "Hoekstra", In view of Criss et al. (US Pub No. 201900042358), hereinafter "Criss" in further view of Kalyanasundharam et al. (US Pub No. 2020226081), hereinafter " Kalyanasundharam"].
As per claim 1, Hoekstra significantly teaches A method for memory recovery, the method comprising (Embodiments of the present invention provide systems and methods for using different error correction codes [Hoekstra PP 0016]):
detecting, by a first memory controller, an error associated with a primary memory (Data processing system 100 includes a processor 102 , a memory controller 104 with error correction code (ECC) control 116 , non-volatile memory 106 [Hoekstra PP 0017],In process 602, a message containing a memory read access address is received by memory controller 104. Process 604 detects whether one or more errors are encountered or detected [Hoekstra PP 0034]);
receiving, by the first memory controller, information comprising a recovery code from a source that is external to the first memory controller (Information for the codes used for another set of subsection sizes of the memory array can be stored in a secondary memory outside the memory array … The secondary memory can be implemented using a volatile memory device that is external to the NVM where the data is stored. [Hoekstra PP 0016])
Hoekstra does not explicitly teach “via a second memory controller that is connected in a data path between the first memory controller and an interface; and modifying, by the first memory controller, the error on the primary memory based on the information.”
However, Criss, in an analogous art, teaches and modifying, by the first memory controller, the error on the primary memory based on the information (Memory controller ECC component 114 detects and corrects these miss-corrections and produces corrected data 206 [Criss PP 0023], all of the bits are sent as SEC corrected data 204 to memory controller 104 where memory controller ECC component 114 checks for inconsistencies between the data and the memory controller ECC check bits and, if required, performs a correction … If the error is correctable by the memory controller ECC component then the original code word can be found and the data is recovered. [Criss PP 0025])
Therefore, it would have been obvious for one of ordinary skill in the at before the effective filing date of the claimed invention to have modified the memory system disclosed by Hoekstra to incorporate Criss’s teachings of improved error correction, in order to improve reliability and correction performance (improved error detection and correction capabilities may be provided. [Criss PP 0017], increase the reliability of HBM3 or similar memory devices and reduce the cost and latency of error corrections. [Criss PP 0018]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
Hoekstra in view of Criss do not explicitly teach “via a second memory controller that is connected in a data path between the first memory controller and an interface;”
However, Kalyanasundharam, in an analogous art, teaches via a second memory controller that is connected in a data path between the first memory controller and an interface (A port controller on an integrated circuit includes a physical layer circuit coupled to an external Peripheral Component Interconnect Express (PCIe) communication link, a Cache Coherent Interconnect for Accelerators (CCIX) port selectively coupled to the physical layer circuit, and a transaction layer controller selectively coupled to the physical layer circuit and operating according to an alternate protocol. The port controller includes a light-weight memory protocol controller to send requests to and receive responses from a memory through the CCIX port and over the PCIe communication link [Kalyansundharam PP 0012] The port controller (second memory controller) is connected in the data path between the system memory controller fabric (first memory controller side) and the CCIX port (interface));
Therefore, it would have been obvious for one of ordinary skill in the at before the effective filing date of the claimed invention to have modified the memory system disclosed by Hoekstra in view of Criss to further incorporate Kalyanasundharam’s teachings of a coherent interconnect/interface, in order to improve memory access (The expanded memory capability may offer expanded memory capacity [Kalyanasundharam’s PP 0017]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
As per claim 2, Hoekstra significantly teaches wherein the interface is communicatively coupled to a secondary memory (Memory Controller 104 is coupled to communicate with flash memory 106 , secondary memory 108 , RAM 110 and ROM 112 via one or more buses. [Hoekstra PP 0017]) storing the recovery code (Parity bits associated with correcting error(s) in segments of flash memory 106 of another specified size can be stored in secondary memory 108. [Hoekstra PP 0018]).
As per claim 3, Hoekstra significantly teaches further comprising: generating, by the first memory controller, the recovery code (ECC control 116 can provide both error encoding and error decoding functionality. As data is received from memory (e.g., flash memory 106 , RAM 110 or ROM 112 ) or processor 102 , ECC control 116 can generate parity bits, also referred to as error correction bits [Hoekstra PP 0018]); and
sending the recovery code to the secondary memory via the interface (Process 508 determines whether the type of ECC selected in process 506 has changed. If a new type of ECC is going to be used, process 510 writes the corresponding information in the error correction bits and elsewhere in a corresponding entry in secondary memory 108. [Hoekstra PP 0033]).
As per claim 4, Hoekstra in view of Criss do not explicitly teach “wherein the sending the recovery code via the interface is in accordance with a cache-coherent protocol.”
However, Kalyanasundharam, in an analogous art, teaches wherein the sending the recovery code via the interface is in accordance with a cache-coherent protocol (a Cache Coherent Interconnect for Accelerators (CCIX) port … The port controller also includes a remote coherent slave controller to send cache coherency requests over the PCIe communication link using a full set of CCIX protocol memory transaction types. [Kalyanasundharam PP 0012]).
Therefore, it would have been obvious for one of ordinary skill in the at before the effective filing date of the claimed invention to have modified the memory system disclosed by Hoekstra in view of Criss to further incorporate Kalyanasundharam’s teachings of a coherent interconnect/interface, in order to improve memory access (The expanded memory capability may offer expanded memory capacity [Kalyanasundharam’s PP 0017]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
As per claim 5, Hoekstra significantly teaches and storing the recovery code in the secondary memory (Process 508 determines whether the type of ECC selected in process 506 has changed. If a new type of ECC is going to be used, process 510 writes the corresponding information in the error correction bits and elsewhere in a corresponding entry in secondary memory 108. [Hoekstra PP 0033]).
Hoekstra does not explicitly teach “further comprising: storing data associated with an application in the primary memory;”
However, Criss, in an analogous art, teaches further comprising: storing data associated with an application in the primary memory (At block 808, memory device 102 stores the data bits, the memory controller ECC check bits, and the on-die ECC check bits in memory 112. [Criss PP 0049]);
Therefore, it would have been obvious for one of ordinary skill in the at before the effective filing date of the claimed invention to have modified the memory system disclosed by Hoekstra to incorporate Criss’s teachings of improved error correction, in order to improve reliability and correction performance (improved error detection and correction capabilities may be provided. [Criss PP 0017], increase the reliability of HBM3 or similar memory devices and reduce the cost and latency of error corrections. [Criss PP 0018]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
As per claim 6, Hoekstra significantly teaches wherein the secondary memory is external to the primary memory (Information for the codes used for another set of subsection sizes of the memory array can be stored in a secondary memory outside the memory array …The secondary memory can be implemented using a volatile memory device that is external to the NVM where the data is stored. [Hoekstra PP 0016]).
As per claim 7, Hoekstra in view of Criss do not explicitly teach “wherein: the first memory controller is communicatively coupled, via a data path, to a second memory controller; and the second memory controller converts the recovery code into a format for sending from the interface.”
However, Kalyanasundharam, in an analogous art, teaches wherein: the second memory controller converts the recovery code into a format for sending from the interface (transforming access requests that may include coherency-related requests to a form using only the light-weight set of requests [Kalyanasundharam PP 0032]).
Therefore, it would have been obvious for one of ordinary skill in the at before the effective filing date of the claimed invention to have modified the memory system disclosed by Hoekstra in view of Criss to further incorporate Kalyanasundharam’s teachings of a coherent interconnect/interface, in order to improve memory access (The expanded memory capability may offer expanded memory capacity [Kalyanasundharam’s PP 0017]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
As per claim 8, Hoekstra does not explicitly teach “wherein the primary memory comprises volatile memory.”
However, Criss, in an analogous art, teaches wherein the primary memory comprises volatile memory (memory 112 may include volatile types of memory including, but not limited to, RAM, D-RAM, DDR SDRAM, SRAM, T-RAM or Z-RAM. [Criss PP 0020]).
Therefore, it would have been obvious for one of ordinary skill in the at before the effective filing date of the claimed invention to have modified the memory system disclosed by Hoekstra to incorporate Criss’s teachings of improved error correction, in order to improve reliability and correction performance (improved error detection and correction capabilities may be provided. [Criss PP 0017], increase the reliability of HBM3 or similar memory devices and reduce the cost and latency of error corrections. [Criss PP 0018]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
As per claim 9, Hoekstra does not explicitly teach “wherein: the primary memory comprises parity information; and the first memory controller detects the error based on the parity information.”
However, Criss, in an analogous art, teaches wherein: the primary memory comprises parity information (Parity bits used in an ECC scheme impose conditions on the data and the external ECC check bits written to memory 112. [Criss PP 0024]);
and the first memory controller detects the error based on the parity information (At block 1002, memory controller 104 receives data bits and the memory controller ECC check bits from memory device 102 … At block 1004, the memory controller, using memory controller ECC component 114, checks the received data bits against the received memory controller ECC check bits and performs corrections as needed. [Criss PP 0055]).
Therefore, it would have been obvious for one of ordinary skill in the at before the effective filing date of the claimed invention to have modified the memory system disclosed by Hoekstra to incorporate Criss’s teachings of improved error correction, in order to improve reliability and correction performance (improved error detection and correction capabilities may be provided. [Criss PP 0017], increase the reliability of HBM3 or similar memory devices and reduce the cost and latency of error corrections. [Criss PP 0018]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
As per claim 10, Hoekstra significantly teaches wherein the recovery code comprises at least one of a single-bit error correction, double-bit error detection (SECDED) code (During a read access of flash memory 106 , single bit error correction and double bit error detection (SEC-DED) can be performed on each of the memory segments. [Hoekstra PP 0026]),
or a triple-bit error correction, quadruple-bit error detection (TECQED) code (error correction bits used in more complex ECC to correct multiple errors can be stored in secondary memory 108. [Hoekstra PP 0018]).
As per claim 11, Hoekstra significantly teaches wherein the primary memory comprises a memory module (Data processing system 100 includes a processor 102 , a memory controller 104 with error correction code (ECC) control 116 , non-volatile memory 106 such as flash memory, secondary memory 108 , random access memory (RAM) 110 , read-only memory (ROM) 112 , and peripheral modules 114 . [Hoekstra PP 0017]).
As per claim 12, Hoekstra does not explicitly teach “wherein: the primary memory comprises an error correction code (ECC) memory comprising a location for processing detection and/or correction codes; and the method further comprises: generating, by the first memory controller, an error detection code and writing the error detection code to the location for processing detection and/or correction codes.”
However, Criss, in an analogous art, teaches wherein: the primary memory comprises an error correction code (ECC) memory comprising a location for processing detection and/or correction codes (At block 808, memory device 102 stores the data bits, the memory controller ECC check bits, and the on-die ECC check bits in memory 112. [Criss PP 0049]);
and the method further comprises: generating, by the first memory controller, an error detection code (At block 704, memory controller 104, using memory controller ECC component 114, determines a plurality of memory controller ECC check bits and one or more parity bit(s) for the received data bits. [Criss PP 0048])
and writing the error detection code to the location for processing detection and/or correction codes (At block 808, memory device 102 stores the data bits, the memory controller ECC check bits, and the on-die ECC check bits in memory 112. [Criss PP 0049]).
Therefore, it would have been obvious for one of ordinary skill in the at before the effective filing date of the claimed invention to have modified the memory system disclosed by Hoekstra to incorporate Criss’s teachings of improved error correction, in order to improve reliability and correction performance (improved error detection and correction capabilities may be provided. [Criss PP 0017], increase the reliability of HBM3 or similar memory devices and reduce the cost and latency of error corrections. [Criss PP 0018]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
As per claim 13, Hoekstra does not explicitly teach “wherein: the primary memory comprises one or more volatile-memory-based chips comprising a parity space; and the method further comprises: generating, by the first memory controller, an error detection code and writing the error detection code to the parity space.”
However, Criss, in an analogous art, teaches wherein: the primary memory comprises one or more volatile-memory-based chips comprising a parity space (In some examples, memory 112 may include volatile types of memory including, but not limited to, RAM, D-RAM, DDR SDRAM, SRAM, T-RAM or Z-RAM. [Criss PP 0020], Parity bits used in an ECC scheme impose conditions on the data and the external ECC check bits written to memory 112. [Criss PP 0024]);
and the method further comprises: generating, by the first memory controller, an error detection code (At block 704, memory controller 104, using memory controller ECC component 114, determines a plurality of memory controller ECC check bits and one or more parity bit(s) for the received data bits. [Criss PP 0048])
and writing the error detection code to the parity space (At block 808, memory device 102 stores the data bits, the memory controller ECC check bits, and the on-die ECC check bits in memory 112. [Criss PP 0049]).
Therefore, it would have been obvious for one of ordinary skill in the at before the effective filing date of the claimed invention to have modified the memory system disclosed by Hoekstra to incorporate Criss’s teachings of improved error correction, in order to improve reliability and correction performance (improved error detection and correction capabilities may be provided. [Criss PP 0017], increase the reliability of HBM3 or similar memory devices and reduce the cost and latency of error corrections. [Criss PP 0018]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
As per claim 14, Hoekstra does not explicitly teach “wherein the first memory controller reads at least a data associated with an application and an error detection code from the primary memory.”
However, Criss, in an analogous art, teaches wherein the first memory controller reads at least a data associated with an application and an error detection code from the primary memory (At block 902, when reading data from the memory device is requested, memory device 102 gets the data bits, the memory controller ECC check bits, and the on-die ECC check bits from memory 112. [Criss PP 0050], At block 910, memory device sends the data bits and the memory controller ECC check bits to memory controller 104. [Criss PP 0054], At block 1002, memory controller 104 receives data bits and the memory controller ECC check bits from memory device 102. [Criss PP 0055]).
Therefore, it would have been obvious for one of ordinary skill in the at before the effective filing date of the claimed invention to have modified the memory system disclosed by Hoekstra to incorporate Criss’s teachings of improved error correction, in order to improve reliability and correction performance (improved error detection and correction capabilities may be provided. [Criss PP 0017], increase the reliability of HBM3 or similar memory devices and reduce the cost and latency of error corrections. [Criss PP 0018]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
As per claim 15, Hoekstra in view of Criss do not explicitly teach “wherein the receiving the information from the interface is associated with a higher latency than receiving the information from the primary memory.”
However, Kalyanasundharam, in an analogous art, teaches wherein the receiving the information from the interface is associated with a higher latency than receiving the information from the primary memory (Supporting so many commands requires a much larger, more expensive processor than supporting only non-caching commands. Such processors also tend to have a higher latency in responding to commands. [KALYANASUNDHARAM PP 0075]).
Therefore, it would have been obvious for one of ordinary skill in the at before the effective filing date of the claimed invention to have modified the memory system disclosed by Hoekstra in view of Criss to further incorporate Kalyanasundharam’s teachings of a coherent interconnect/interface, in order to improve memory access (The expanded memory capability may offer expanded memory capacity [Kalyanasundharam’s PP 0017]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
As per claim 16, Hoekstra significantly teaches A device comprising: a primary memory (Data processing system 100 includes … non-volatile memory 106 such as flash memory [Hoekstra PP 0017]);
a first memory controller to generate a recovery code and communicatively coupled to the primary memory (Data processing system 100 includes a processor 102 , a memory controller 104 with error correction code (ECC) control 116 [Hoekstra PP 0017], ECC control 116 can provide both error encoding and error decoding functionality. As data is received from memory or processor 102 , ECC control 116 can generate parity bits, also referred to as error correction bits [Hoekstra PP 0018])
Hoekstra does not explicitly teach “the recovery code for modifying an error on the primary memory; and a second memory controller to convert the recovery code to a format for sending from an interconnection protocol, the second memory controller beinq connected in a data path between the first memory controller and an interface associated with the interconnection protocol.”
However, Criss, in an analogous art, teaches the recovery code for modifying an error on the primary memory (memory controller ECC component 114 checks for inconsistencies between the data and the memory controller ECC check bits and, if required, performs a correction … If the error is correctable by the memory controller ECC component then the original code word can be found and the data is recovered. [Criss PP 0025]);
Therefore, it would have been obvious for one of ordinary skill in the at before the effective filing date of the claimed invention to have modified the memory system disclosed by Hoekstra to incorporate Criss’s teachings of improved error correction, in order to improve reliability and correction performance (improved error detection and correction capabilities may be provided. [Criss PP 0017], increase the reliability of HBM3 or similar memory devices and reduce the cost and latency of error corrections. [Criss PP 0018]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
Hoekstra in view of Criss do not explicitly teach “and a second memory controller to convert the recovery code to a format for sending from an interconnection protocol, the second memory controller beinq connected in a data path between the first memory controller and an interface associated with the interconnection protocol).”
However, Kalyanasundharam, in an analogous art, teaches and a second memory controller to convert the recovery code to a format for sending from an interconnection protocol (transforming access requests that may include coherency-related requests to a form using only the light-weight set of requests [Kalyansundharam PP 0032]), the second memory controller beinq connected in a data path between the first memory controller and an interface associated with the interconnection protocol (A port controller on an integrated circuit includes a physical layer circuit coupled to an external Peripheral Component Interconnect Express (PCIe) communication link, a Cache Coherent Interconnect for Accelerators (CCIX) port selectively coupled to the physical layer circuit, and a transaction layer controller selectively coupled to the physical layer circuit and operating according to an alternate protocol. The port controller includes a light-weight memory protocol controller to send requests to and receive responses from a memory through the CCIX port and over the PCIe communication link [Kalyansundharam PP 0012] The port controller (second memory controller) is connected in the data path between the system memory controller fabric (first memory controller side) and the CCIX port (interface).).
Therefore, it would have been obvious for one of ordinary skill in the at before the effective filing date of the claimed invention to have modified the memory system disclosed by Hoekstra in view of Criss to further incorporate Kalyanasundharam’s teachings of a coherent interconnect/interface, in order to improve memory access (The expanded memory capability may offer expanded memory capacity [Kalyanasundharam’s PP 0017]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
As per claim 17, Hoekstra does not explicitly teach “wherein the first memory controller: receives information comprising the recovery code from the second memory controller; and modifies an error on the primary memory based on the information.”
However, Criss, in an analogous art, teaches and modifies an error on the primary memory based on the information (memory controller ECC component 114 checks for inconsistencies between the data and the memory controller ECC check bits and, if required, performs a correction … If the error is correctable by the memory controller ECC component then the original code word can be found and the data is recovered. [Criss PP 0025]).
Therefore, it would have been obvious for one of ordinary skill in the at before the effective filing date of the claimed invention to have modified the memory system disclosed by Hoekstra to incorporate Criss’s teachings of improved error correction, in order to improve reliability and correction performance (improved error detection and correction capabilities may be provided. [Criss PP 0017], increase the reliability of HBM3 or similar memory devices and reduce the cost and latency of error corrections. [Criss PP 0018]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
Hoekstra in view of Criss do not explicitly teach “wherein the first memory controller: receives information comprising the recovery code from the second memory controller;”
However, Kalyanasundharam, in an analogous art, teaches wherein the first memory controller: receives information comprising the recovery code from the second memory controller (at the remote coherent slave controller, memory access requests are received over the on-chip interconnect fabric [KALYANASUNDHARAM PP 0013]);
Therefore, it would have been obvious for one of ordinary skill in the at before the effective filing date of the claimed invention to have modified the memory system disclosed by Hoekstra in view of Criss to further incorporate Kalyanasundharam’s teachings of a coherent interconnect/interface, in order to improve memory access (The expanded memory capability may offer expanded memory capacity [Kalyanasundharam’s PP 0017]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
As per claim 18, Hoekstra does not explicitly teach “wherein the primary memory comprises volatile memory.”
However, Criss, in an analogous art, teaches wherein the primary memory comprises volatile memory (In some examples, memory 112 may include volatile types of memory including, but not limited to, RAM, D-RAM, DDR SDRAM, SRAM, T-RAM or Z-RAM. [Criss PP 0020]).
Therefore, it would have been obvious for one of ordinary skill in the at before the effective filing date of the claimed invention to have modified the memory system disclosed by Hoekstra to incorporate Criss’s teachings of improved error correction, in order to improve reliability and correction performance (improved error detection and correction capabilities may be provided. [Criss PP 0017], increase the reliability of HBM3 or similar memory devices and reduce the cost and latency of error corrections. [Criss PP 0018]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
As per claim 19, Hoekstra does not explicitly teach “wherein the primary memory comprises one or more volatile-memory-based chips comprising at least one of a parity space or a location for processing detection and/or correction codes.”
However, Criss, in an analogous art, teaches wherein the primary memory comprises one or more volatile-memory-based chips (In some examples, memory 112 may include volatile types of memory including, but not limited to, RAM, D-RAM, DDR SDRAM, SRAM, T-RAM or Z-RAM. [Criss PP 0020]) comprising at least one of a parity space or a location for processing detection and/or correction codes (Parity bits used in an ECC scheme impose conditions on the data and the external ECC check bits written to memory 112. [Criss PP 0024]).
Therefore, it would have been obvious for one of ordinary skill in the at before the effective filing date of the claimed invention to have modified the memory system disclosed by Hoekstra to incorporate Criss’s teachings of improved error correction, in order to improve reliability and correction performance (improved error detection and correction capabilities may be provided. [Criss PP 0017], increase the reliability of HBM3 or similar memory devices and reduce the cost and latency of error corrections. [Criss PP 0018]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
As per claim 20, Hoekstra significantly teaches a device comprising: an interface to receive a request, from a first memory controller associated with a primary memory (In process 602, a message containing a memory read access address is received by memory controller 104. [Hoekstra PP 0034])
and a secondary memory that is external to the primary memory and that comprises the recovery code (Information for the codes used for another set of subsection sizes of the memory array can be stored in a secondary memory outside the memory array …The secondary memory can be implemented using a volatile memory device that is external to the NVM where the data is stored. [Hoekstra PP 0016]),
the secondary memory being communicatively coupled to the interface to send the recovery code from the device to the first memory controller (Memory Controller 104 is coupled to communicate with flash memory 106 , secondary memory 108 , RAM 110 and ROM 112 via one or more buses. [Hoekstra PP 0017]).
Hoekstra does not explicitly teach “for information comprising a recovery code for modifyinq an error on the primary memory;”
However, Criss, in an analogous art, teaches for information comprising a recovery code for modifyinq an error on the primary memory (memory controller ECC component 114 checks for inconsistencies between the data and the memory controller ECC check bits and, if required, performs a correction … If the error is correctable by the memory controller ECC component then the original code word can be found and the data is recovered. [Criss PP 0025]);
Therefore, it would have been obvious for one of ordinary skill in the at before the effective filing date of the claimed invention to have modified the memory system disclosed by Hoekstra to incorporate Criss’s teachings of improved error correction, in order to improve reliability and correction performance (improved error detection and correction capabilities may be provided. [Criss PP 0017], increase the reliability of HBM3 or similar memory devices and reduce the cost and latency of error corrections. [Criss PP 0018]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
Conclusion
Applicants’ amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicants are reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for replying to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no case, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAREEM FUAD ALHWAMDEH whose telephone number is (571)272-5501. The examiner can normally be reached Mon-Fri 7:30-5:00.
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/KAREEM FUAD ALHWAMDEH/Examiner, Art Unit 2112
/ESAW T ABRAHAM/Primary Examiner, Art Unit 2112
