DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fairhurst 20090037660 herein Fairhurst in view of Min 20210217469 herein Min.
Per claim 1, Fairhurst discloses: generating an input signal in response to an event for a memory; (fig. 2&3, ¶0037; A cache controller 206 accepts segments on line 208 to be written into cache lines 204. The cache controller 206 assigns a cache lock-time with a time duration to the segment. The cache controller 206 stores the segment in memory 202 if a cache line 204 is available, and protects the segment stored in the cache line from replacement until the expiration of the lock-time) providing the input signal to a time-varying circuit including a plurality of time- varying devices that correspond to a plurality of storage spaces of the memory and store values that naturally decrease with time; (fig. 3, ¶0042; If the cache controller 206 either reads or writes to a cache line with a previously assigned lock-time, a new lock-time can be assigned to the residing segment. Then, the cache controller protects the cache line from replacement until the expiration of the new lock-time; the examiner notes that the time varying circuit/device is merely a type of RAM, SRAM, DRAM or SSD. Further, the stored values naturally decreasing is the lock-time assigned to the segment which counts down to expiration) generating an output signal by reading a value stored in at least one time-varying device among the plurality of time-varying devices; (fig. 3, ¶0038; The cache controller 206 locates an available cache line in response by determining that the cache line is empty, or by determining that the cache line is available for a replacement segment. A cache line 204 is available for a replacement segment if the residing segment has an expired lock-time, or if the residing segment was assigned a "zero" duration (no) lock-time; the examiner interprets the limitation as checking the recency status of the cache line to determine replacement) and determining a storage space for replacement from among the plurality of storage spaces of the memory, based on the output signal (fig. 3; ¶0047; Step 302 accepts a segment of data. Step 304 assigns a cache lock-time with a time duration to the segment. In one aspect, Step 305 locates an available cache line in response to either determining that the cache line is empty, or determining that the cache line is available for a replacement segment. If a cache line is available, Step 306 stores the segment. Step 308 protects the segment stored in the cache line from replacement until the expiration of the lock-time. Upon the expiration of the lock-time, Step 310 automatically makes the cache line available for a replacement segment) and wherein the providing of the input signal to the time-varying circuit comprises providing the input signal to the time-varying circuit such that a value stored in at least one time-varying device among the plurality of time-varying devices is increased (fig. 2 ¶0051; Upon the performance of a process such as reading or writing the cache line, Step 312 assigns a new lock-time to the segment. Step 314 protects the cache line from replacement until the expiration of the new lock-time; the examiner interprets the increase as a reset/assigning of a new lock-time).
Faithurst discloses increasing or assigning a new lock time but does not specifically disclose: a value stored in at least one time-varying device among the plurality of time-varying devices is increased to a value having a magnitude based on a magnitude and timing of a previous input signal.
However, Min discloses: a value stored in at least one time-varying device among the plurality of time-varying devices is increased to a value having a magnitude based on a magnitude and timing of a previous input signal (Abstract; selecting a program voltage pattern corresponding to the input data from among a plurality of program voltage patterns for storing the input data in a memristor array circuit, and storing the input data in the memristor array circuit depending on the program voltage pattern thus selected. Each of the plurality of program voltage patterns includes a plurality of voltage pulses in which a pulse magnitude gradually increases over time).
It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to combine the teachings of Fairhust amd Min’s voltage pattern for programming the memristor to increase the reliability of the memory (¶0171).
Per claim 2, Fairhurst discloses: wherein the generating of the input signal comprises generating a different input signal according to the type of the event for the memory (fig. 2 ¶0040; Shown in the list 212 are a "long" lock-time and a "short" lock-time. However, it should be understood that the system is not limited to any particular number of lock-time durations. In one variation, the cache controller has a configuration interface on line 214 to accept commands configuring the time duration for each of the lock-times on the list 212. In another aspect, the cache controller 206 accepts a communication on line identifying a segment of data as transient data. The cache controller selects a lock-time from the list 212 in response to the segment being identified as transient data.).
Per claim 3, Fairhurst discloses: generating a first input signal when the event for the memory is an event in which a storage space for replacement in the memory does not need to be determined; and generating a second input signal when the event for the memory is an event in which a storage space for replacement in the memory needs to be determined (fig. 2 ¶0051; Upon the performance of a process such as reading or writing the cache line, Step 312 assigns a new lock-time to the segment. Step 314 protects the cache line from replacement until the expiration of the new lock-time; the examiner notes that the claim is interpreted as signaling a read hit or a replacement).
Per claim 4, Fairhurst discloses: wherein the providing of the input signal to the time-varying circuit comprises providing the input signal to the time-varying circuit such that the value stored in at least one time-varying device among the plurality of time- varying devices is changed (fig. 2 ¶0051; Upon the performance of a process such as reading or writing the cache line, Step 312 assigns a new lock-time to the segment. Step 314 protects the cache line from replacement until the expiration of the new lock-time; the examiner notes that the claim is interpreted as updating the time/recency counter/clock).
Per claim 5, Fairhurst discloses: wherein the providing of the input signal to the time-varying circuit comprises providing the input signal to the time-varying circuit such that the value stored in at least one time-varying device among the plurality of time- varying devices is read ((fig. 3, ¶0038; The cache controller 206 locates an available cache line in response by determining that the cache line is empty, or by determining that the cache line is available for a replacement segment. A cache line 204 is available for a replacement segment if the residing segment has an expired lock-time, or if the residing segment was assigned a "zero" duration (no) lock-time; the examiner notes that the claim is interpreted as accessing the time/recency counter/clock).
Per claim 6, Fairhurst discloses: wherein the providing of the input signal to the time-varying circuit comprises providing the input signal to a time-varying device corresponding to a storage space related to the event among the plurality of storage spaces of the memory, from among the plurality of time-varying devices (fig. 3,¶0041; the cache controller 206 may accept a communication that identifies the input port (not shown) supplying the segment. The cache controller identifies the segment as transient data by cross-referencing input ports to transient data sources. The cross-referenced table is shown as port list 216. In another aspect, the cache controller assigns the lock-time in response to reading priority fields included in communications associated with the segment. This priority field may be in overhead accompanying the data segment, or be part of a separate communication; ¶0042; If the cache controller 206 either reads or writes to a cache line with a previously assigned lock-time, a new lock-time can be assigned to the residing segment. Then, the cache controller protects the cache line from replacement until the expiration of the new lock-time;).
Per claim 7, Fairhurst discloses: wherein the generating of the output signal comprises generating the output signal by reading values stored in two or more time- varying devices corresponding to two or more storage spaces related to the event among the plurality of storage spaces of the memory, from among the plurality of time-varying devices ((fig. 3, ¶0038; The cache controller 206 locates an available cache line in response by determining that the cache line is empty, or by determining that the cache line is available for a replacement segment. A cache line 204 is available for a replacement segment if the residing segment has an expired lock-time, or if the residing segment was assigned a "zero" duration (no) lock-time; the examiner notes that the claim is interpreted as accessing the time/recency counter/clock).
Per claim 8, Fairhurst discloses: wherein the determining of the storage space for replacement comprises: selecting one time-varying device from among the two or more time-varying devices by analyzing, based on the output signal, the values stored in the two or more time-varying devices; and determining a storage space corresponding to the selected time-varying device, from among the two or more storage spaces, as the storage space for replacement ((fig. 3, ¶0038; The cache controller 206 locates an available cache line in response by determining that the cache line is empty, or by determining that the cache line is available for a replacement segment. A cache line 204 is available for a replacement segment if the residing segment has an expired lock-time, or if the residing segment was assigned a "zero" duration (no) lock-time; the examiner notes that the claim is interpreted as selecting a cache line in the memory device for replacement. The value is merely a clock/counter).
Per claim 9, Fairhurst discloses: wherein the selecting of the one time-varying device from among the two or more time-varying devices comprises selecting one time- varying device storing a value less than a predetermined value, from among the two or more time-varying devices, based on the output signal ((fig. 3, ¶0038; The cache controller 206 locates an available cache line in response by determining that the cache line is empty, or by determining that the cache line is available for a replacement segment. A cache line 204 is available for a replacement segment if the residing segment has an expired lock-time, or if the residing segment was assigned a "zero" duration (no) lock-time; the examiner notes that the value less than a predetermined value is interpreted as a non zero timer/clock).
Per claim 10, Fairhurst discloses: wherein the selecting of the one time-varying device from among the two or more time-varying device comprises selecting one time- varying device storing a smallest value, from among the two or more time-varying devices, based on the output signal ((fig. 3, ¶0038; The cache controller 206 locates an available cache line in response by determining that the cache line is empty, or by determining that the cache line is available for a replacement segment. A cache line 204 is available for a replacement segment if the residing segment has an expired lock-time, or if the residing segment was assigned a "zero" duration (no) lock-time; the examiner notes that the smallest value is interpreted as the lowest timer/count value).
Claims 11-14 are the electronic circuit claims corresponding to the method claims 1-10 and are rejected under the same reasons set forth in connection with the rejection of claims 1-10. The rejections are silent to the memory comprises at least one of a register, a cache memory, and a main memory and the plurality of time- varying devices comprises at least one of a memristor, dynamic random-access memory (DRAM), and static random-access memory (SRAM). However, fig. 2 and ¶0036- 37 Fairhurst discloses the memory as disclosed.
Claims 15-20 are the electronic circuit claims corresponding to the method claims 1-10 and are rejected under the same reasons set forth in connection with the rejection of claims 1-10. The rejections are silent to a set-associative cache; selecting of the row and the column. However, ¶0020 of Fairhurst discloses a set associative cache ¶0020 (A Pseudo-LRU (PLRU) algorithm is used for caches with large associativity (generally < 4 ways)).
Response to Arguments
Applicant’s arguments, with respect to the rejection(s) of claim(s) 1, 11 and 15 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Min. Min discloses: selecting a program voltage pattern corresponding to the input data from among a plurality of program voltage patterns for storing the input data in a memristor array circuit, and storing the input data in the memristor array circuit depending on the program voltage pattern thus selected. Each of the plurality of program voltage patterns includes a plurality of voltage pulses in which a pulse magnitude gradually increases over time.
Remark
Examiner respectfully requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist Examiner in prosecuting the application.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BABOUCARR FAAL whose telephone number is (571)270-5073. The examiner can normally be reached M-F 8:30-5:30 EST.
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BABOUCARR . FAAL
Primary Examiner
Art Unit 2138
/BABOUCARR FAAL/Primary Examiner, Art Unit 2138
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