DETAILED ACTION
Claims 1-20 are presented for examination.
This office action is in response to amendment of application on 28-NOV-2025.
Claims 7, 8, 10, 15, 17-20 are cancelled.
Claims 1, 3, 11, 12 are amended.
Claims 1-6, 9, 11-14, 16 remain pending.
Applicant’s amendments to the drawings have overcome each and every objection previously set forth in the Final Office Action mailed 29-JULY-2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 28-NOV-2025 has been entered.
Response to Arguments
Applicant’s arguments, see pages 6, filed 28-NOV-2025, with respect to the amendments to the objections to the drawings have been fully considered and are persuasive. The objections to the drawings previously set forth have been withdrawn due to amendments.
Applicant’s arguments, see pages 6-9, filed 28-NOV-2025, with respect to the rejections under 35 U.S.C. 103, have been fully considered and are persuasive due to amendments. The rejections under 35 U.S.C. 103 previously set forth have been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of a different interpretation of previously applied prior art references.
1. In response to Applicant’s arguments, see page 7, that Igahara and Li fail to disclose switching from the QLC mode to the TLC mode in response to a command to perform a TLC programming operation and remaining in the QLC mode in response to a command to perform a TLC read operation such that the TLC read operation is performed while operating in the QLC mode, Examiner respectfully disagrees. As shown in the rejection of the previous office action, Igahara teaches the switching from the QLC mode to the TLC mode in response to a command to perform a TLC programming operation (see Igahara Col. 9 lines 6-16 and 52-53, which teaches to dynamically switch between two modes to write host data into cells with different densities, which applies to a combination of TLC and QLC modes.). Further, with respect to [0050] of Li, Li teaches that a less dense memory read operation is performed although the cells were programmed to a first, more-dense configuration. With the interpretation that the “mode” corresponds to the way the cells are written, the less-dense read is performed while in the more-dense mode. The combinations of the teachings renders obvious an embodiment where a the system is able to switch between a QLC mode and a TLC mode to perform their respective programming, but where a TLC read can be performed while operating in the QLC mode.
2. In response to Applicant’s arguments, see page 7-8, that TLC and SLC read operations are not analogous due to challenges associated with mixed mode operation which prevent a TLC mode and a QLC mode from operating together, Examiner respectfully disagrees. As shown in both [0047] of Li, and Col. 9 lines 52-53 of Igahara, storage systems which operate with both TLC and QLC together are fully taught, and as described in [0050] of Li and Col. 9 lines 40-53 of Igahara, the teachings are applicable broadly to any combination where two different densities are used, including with various combinations like SLC/QLC, SLC/TLC, and TLC/QLC. The teachings from Igahara and Li together show that, before the effective filing date of the claimed invention, these techniques that apply to systems that designate a less-dense operation and a more-dense operation, may apply analogously with SLC as the less-dense mode and QLC as the more-dense mode, as they would to a system with TLC as the less-dense mode and QLC as the more-dense mode.
3. In response to Applicant’s arguments, see page 8, that Li does not teach a first more-dense mode as QLC and a less-dense mode is TLC, Examiner respectfully disagrees. Applicant argues that the fact that a first array programmed to a more-dense mode and a second array programmed to a less dense mode precludes the teachings from disclosing remaining in the QLC mode in response to a command to perform a TLC read operation such that the TLC read operation is performed while operating in the QLC mode. However, Examiner notes that, as shown above and in the previous rejections, the less-dense memory read operation performed while the higher first density was used to program, in combination with the teachings that these ideas can apply when the lower density is TLC and the higher density is QLC, is within the broadest reasonable interpretation of the claimed remaining in the QLC mode in response to a command to perform a TLC read operation. Given that the programming density does not change from the higher QLC mode, it is understood to be in QLC mode while performing the TLC read operation.
4. In response to Applicant’s arguments, see page 8, that Li does not define what “performed as normal” means, and therefore does not teach that a TLC read operation is performed while in the QLC mode, because a TLC read operation can still be performed by transitioning to a TLC mode, Examiner respectfully disagrees. The “less-dense memory read operation is performed as normal” language of Li is interpreted to mean that a less-dense memory read operation is performed, and the “as normal” aspect does not preclude that interpretation in context. Again, considering that the only requirement for the switching to occur between the TLC mode and QLC mode is when the programming occurs, which is consistent with both claim 1 and an embodiment put forth in Applicant’s instant specification in [00106]. A QLC mode can be interpreted to be simply the state in which the cells are programmed, and therefore, the teachings of Li which disclose that the less-dense read is performed in spite of the programming can be understood as remaining in the QLC mode, as there is no implication or suggestion that the programming would transition to a TLC in order to perform the read. Therefore, a less-dense read operation being performed on a second set of memory cells, which are in the QLC mode but readable in the less-dense reading operation, is taught, and is applicable to the embodiment where the more-dense mode is QLC, and the less-dense mode is TLC.
5. Examiner acknowledges the Applicant’s attempts to clarify the limitation, but as shown in detail in the rejection below, the broadest reasonable interpretation of the claim still does not preclude the interpretation of the combination of Igahara and Li discussed above to teach their respective claim elements, but does require the addition of Abrahams to teach the amended limitation of the multi-parameter load previously found in cancelled dependent claims.
6. Regarding Applicant’s arguments, see page 9, that the dependent claims are allowable for the same reasons as the independent claims, as shown above and in the rejections, the dependent claims are not allowable, and therefore claims that depend on them remain not allowable.
Claim Objections
Claims 1 and 11 are objected to because of the following informalities:
In claim 1 line 14, “the TCL programming” should read “the TLC programming”.
In claim 11 line 13, “the TCL programming” should read “the TLC programming”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 9, 11, 12-14, 16 are rejected under 35 U.S.C. 103 as being unpatentable over
Igahara et al., U.S. Patent No. 10,824,353 (hereinafter 'Igahara') in view of
Li et al., U.S. Pub. No. 20240256136 (hereinafter 'Li') further in view of
Abrahams et al., U.S Pub. No. 20040078454 (hereinafter 'Abrahams').
Regarding Claim 1: A memory device, comprising: (Fig. 1 Igahara teaches an SSD 3 which contains NAND flash memory 5)
Igahara teaches a plurality of memory cells; and (Column 5, lines 54-55 Igahara teaches an array of memory cells “The NAND flash memory 5 includes a memory cell array including memory cells arranged in an array”)
Igahara teaches control circuitry configured to operate in both a quad-level cell (QLC) mode and a triple-level cell (TLC) mode, wherein the control circuitry is configured to, to operate in the QLC mode, perform at least one of a QLC programming operation and a QLC read operation on one or more of the plurality of memory cells using first parameters corresponding to operation in the QLC mode, to operate in the TLC mode, perform a TLC programming operation on one or more of the plurality of memory cells using second parameters corresponding to operation in the TLC mode, and (Column 6, lines 54-55 Igahara further teaches writing to memory in a TLC mode and a QLC mode “The NAND flash memory 5 may execute a write operation in… a TLC mode in which three bits are written per memory cell, or a QLC mode in which four bits are written per memory cell.“ Further, given that the modes are defined by how many bits are written per memory cell, Igahara teaches that the writing in the TLC and QLC modes uses their respective parameters, the amount of bits being interpreted as one of the parameters.)
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Igahara teaches selectively switch between the QLC mode and the TLC mode (Fig. 13, Fig. 14, and Column 9, lines 10-14 Igahara teaches switching between two write modes with different numbers of bits per memory cell, those write modes including TLC and QLC “The mode switch module 121 is configured to dynamically switch the write mode between a first mode where data having N bits is written per one memory cell and a second mode where data having M bits is written per one memory cell”)
Igahara teaches wherein the control circuitry is configured to (i) switch from the QLC mode to the TLC mode in response to a command to perform a TLC programming operation… and perform the TCL programming operation using the second parameters (Figs. 13-14, and Column 9, lines 51-55, Igahara teaches that while in a QLC mode, the mode switch module may switch to the TLC mode and write as TLC. As discussed above, the TLC programming is performed using second parameters.)
While Igahara teaches that the writing mode can be switched between TLC and QLC modes, Igahara does not appear to explicitly disclose (ii) remain in the QLC mode in response to a command to perform a TLC read operation such that the TLC read operation is performed while operating in the QLC mode without the second parameters such that the TLC read operation is performed using the first parameters while operating in the QLC mode or performing a multi-parameter load to load the second parameters.
However, Li teaches remain in the QLC mode in response to a command to perform a TLC read operation such that the TLC read operation is performed while operating in the QLC mode without the second parameters such that the TLC read operation is performed using the first parameters while operating in the QLC mode. ([0027], [0050], Li teaches that a first more-dense mode can be used for performing operations on cells in both a first more-dense and a second less-dense array, and that read operations can still be performed for those cells that are less-densely programmed without changing from the more-dense mode. Moreover, in [0047], Fig. 9B, and [0088], Li further teaches a specific embodiment where the first more-dense mode is QLC and the second less-dense mode is TLC. As discussed above, since the parameters are understood to be the amount of bits used for writing to the cell, and a read operation does not involve a writing, the second parameters for writing in the TLC mode are not used. Further, the first parameters are taught above.)
Igahara and Li are analogous art because they are from the same field of endeavor, memory devices operating in QLC and TLC modes.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the memory device with control circuitry configured to operate in both a QLC mode by using first parameters and TLC mode by using second parameters and selectively switch between the QLC and TLC modes, and to switch from the QLC mode to the TLC mode to program in TLC, as disclosed by Igahara, to also remain in the QLC mode in response to a command to perform a TLC read such that the TLC read is performed while operating in the QLC mode, as disclosed by Li.
One of ordinary skill in the art would have been motivated to make this modification in order to support both modes of programming logical states without additional hardware as discussed in Li [0028] “This concurrent programming can be performed as often as logical states can be mapped to corresponding threshold voltage (or program verify) levels, can be employed for both coarse and fine programming operations, and can be performed without additional programming hardware (e.g., charge pumps and the like) or additional control logic that is otherwise required in iPlane-enabled memory devices.”
While Igahara/Li teach that when performing a TLC or QLC write, corresponding parameters are used, Igahara and Li do not appear to explicitly disclose (i) switch from the QLC mode to the TLC mode in response to a command to perform a TLC programming operation by performing a multi-parameter load to load the second parameters and perform the TCL programming operation using the second parameters
However, Abrahams teaches performing a multi-parameter load([0009] Abrahams teaches loading a variety of operational parameters to operate a memory device “The values for the one or more operational parameters may specify operating conditions for the component. A monitor may be coupled to the component and may be configured to access the values on the non-volatile memory to determine if the component is operating outside of the operating conditions… The operational parameters may indicate voltage, frequency, input current, input power, or other operating conditions for the component.”)
Igahara, Li, and Abrahams are analogous art because they are from the same field of endeavor, configurations of memory controllers.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Igahara/Li and Abrahams, to achieve the result of a memory device described previously, which can switch between a QLC mode to a TLC mode to perform their respective programming operations with their respective parameters, to also perform multi-parameter loads to load the parameters taught by Igahara/Li.
One of ordinary skill in the art would have been motivated to make this modification in order to store all of the various parameters that a device would need for correct operation not specific to just QLC and TLC mode as discussed in Abrahams [0022] “The operational parameters may specify certain conditions for correct operation of the component.”
Regarding Claim 2: The combination of Igahara, Li, and Abrahams teaches all limitations of claim 1, from which claim 2 depends.
Igahara/Li/Abrahams further teaches powers on in the QLC mode (Fig. 14 and Column 6, lines 44-52, Igahara teaches operating a write-mode-switching memory device with a QLC configuration “Alternatively, the NAND flash memory 5 may be a QLC flash memory configured to store four bits per memory cell (16LC flash memory). In that case, generally, four page data is written in memory cells connected to a single word line. Thus, four bits may be written per memory cell. Any area (for example, any one or more blocks) in the QLC flash memory may be used… as a TLC area configured to store three bits per memory cell.”)
Regarding claim 3: The combination of Igahara, Li, and Abrahams teaches all limitations of claim 1, from which claim 3 depends.
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Igahara/Li/Abrahams further teaches non-volatile memory that stores (Fig. 1A and [0041] Li teaches a ROM on a local memory 119 of a controller “The local memory 119 can also include read-only memory (ROM) for storing micro-code.”
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Igahara/Li/Abrahams further teaches (i) the first parameters corresponding to the operation in the QLC mode and (ii) the second parameters corresponding to operation in the TLC mode ([0027] Li teaches threshold voltage levels as QLC programming parameters “The QLC or PLC mode includes specific programming operations and parameters (such as threshold voltage levels and corresponding program verify levels).” [0089], Fig. 9, and Table 4 Li further teaches mapping corresponding TLC programming voltages “As discussed, corresponding program/read verify voltages between these logical states may also be used to map the logical states between TLC memory and QLC memory.”)
Igahara and Li are analogous art because they are from the same field of endeavor, programming memory devices in QLC and TLC modes.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the memory device of claim 1 as disclosed by Igahara with a non-volatile memory that stores (i) first parameters corresponding to operation in the QLC mode, and (ii) second parameters corresponding to operation in the TLC mode as disclosed by Li.
One of ordinary skill in the art would have been motivated to make this modification in order to keep the parameters available to the sub-system controller even if no power was supplied to the device as discussed in Li [0020] “A memory sub-system can include high density non-volatile memory devices where retention of data is desired when no power is supplied to the memory device.”
Regarding claim 4: The combination of Igahara, Li, and Abrahams teaches all limitations of claim 3, from which claim 4 depends.
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Igahara/Li/Abrahams further teaches loading parameters from the non-volatile memory into the operating memory of the device ([0037] Abrahams teaches a monitor that accesses non-volatile memory to obtain operational parameters and reads it into local memory “For example, a monitor may access the non-volatile memory of the component to obtain the operational parameter values. The monitor may read the operational parameters into a local memory from which it operates.”)
Igahara, Li, and Abrahams are analogous art because they are from the same field of endeavor, configurations of memory controllers.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the memory device of claim 3, wherein to operate in the QLC mode, the control circuity is configured to load the first parameters as disclosed by Igahara and Li from the non-volatile memory into operating memory of the device as disclosed by Abrahams.
One of ordinary skill in the art would have been motivated to make this modification in order to cache the parameter values to speed up device performance when operating in the QLC mode as discussed in Abrahams [0033] “The monitor 200 may cache the operational parameter values at power-up to reduce read traffic.”
Regarding claim 5: The combination of Igahara, Li, and Abrahams teaches all limitations of claim 3, from which claim 5 depends.
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Igahara/Li/Abrahams further teaches loading parameters from the non-volatile memory into the operating memory of the device ([0037] Abrahams teaches a monitor that accesses non-volatile memory to obtain operational parameters and reads it into local memory “For example, a monitor may access the non-volatile memory of the component to obtain the operational parameter values. The monitor may read the operational parameters into a local memory from which it operates.”)
Igahara, Li, and Abrahams are analogous art because they are from the same field of endeavor, configurations of memory controllers.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the memory device of claim 3, wherein to operate in the TLC mode, the control circuity is configured to load the second parameters as disclosed by Igahara and Li from the non-volatile memory into operating memory of the device as disclosed by Abrahams.
One of ordinary skill in the art would have been motivated to make this modification in order to cache the parameter values to speed up device performance when operating in the TLC mode as discussed in Abrahams [0033] “The monitor 200 may cache the operational parameter values at power-up to reduce read traffic.”
Regarding claim 6: The combination of Igahara, Li, and Abrahams teaches all limitations of claim 1, from which claim 3 depends.
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Igahara/Li/Abrahams further teaches the control circuitry is configured to retrieve the first parameters or the second parameters from the non-volatile memory ([0034] Abrahams teaches accessing different operational parameters in non-volatile memory in response to a component change “Monitor 200 may be configured to access the operational parameter values stored in non-volatile memory 150. For example, a component may be upgraded to a newer component, and 200 may access different operational parameter values for the newer component from the non-volatile memory 150 on the newer component.”)
Igahara, Li, and Abrahams are analogous art because they are from the same field of endeavor, configurations of memory controllers.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined teach the memory device of claim 3, wherein to switch between the QLC mode and the TLC mode as disclosed by Igahara and Li where the control circuitry is configured to retrieve the first parameters or the second parameters from the non-volatile memory as disclosed by Abrahams.
One of ordinary skill in the art would have been motivated to make this modification in order to only cache the parameters as needed when operating in multiple modes to improve the current mode’s operation as discussed in Abrahams [0033] “The monitor 200 may cache the operational parameter values at power-up to reduce read traffic.”
Regarding Claim 9: The combination of Igahara, Li, and Abrahams teaches all limitations of claim 1, from which claim 9 depends.
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Igahara/Li/Abrahams further teaches teaches to switch from the TLC mode to the QLC mode in response to a command to perform at least one of a QLC read operation and a QLC programming operation (Fig. 36 Igahara teaches receiving a write command S51 while in a TLC write mode, then switching to a QLC mode at S54 to write to NAND flash memory at S57)
Regarding Claim 11: Igahara teaches A method of operating a memory device including a plurality of memory cells, the method comprising: (Fig. 1 and Column 5, lines 54-55 Igahara teaches an SSD with a NAND flash memory 5 that contains an array of memory cells “The NAND flash memory 5 includes a memory cell array including memory cells arranged in an array”)
Igahara teaches operating in both a quad-level cell (QLC) mode and a triple-level cell (TLC) mode, wherein operating in both the QLC mode and the TLC mode includes performing at least one of a QLC programming operation and a QLC read operation on one or more of the plurality of memory cells using first parameters corresponding to operation in the QLC mode, performing a TLC programming operation on one or more of the plurality of memory cells using second parameters corresponding to operation in the TLC mode, (Column 6, lines 54-55 Igahara further teaches writing to memory in a TLC mode and a QLC mode “The NAND flash memory 5 may execute a write operation in… a TLC mode in which three bits are written per memory cell, or a QLC mode in which four bits are written per memory cell.“ Further, given that the modes are defined by how many bits are written per memory cell, Igahara teaches that the writing in the TLC and QLC modes uses their respective parameters, the amount of bits being interpreted as one of the parameters.)
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Igahara teaches selectively switching between the QLC mode and the TLC mode, (Fig. 13, Fig. 14, and Column 9, lines 10-14 Igahara teaches switching between two write modes with different numbers of bits per memory cell, those write modes including TLC and QLC “The mode switch module 121 is configured to dynamically switch the write mode between a first mode where data having N bits is written per one memory cell and a second mode where data having M bits is written per one memory cell”)
Igahara teaches switching from the QLC mode to the TLC mode in response to a command to perform a TLC programming operation… and perform the TCL programming operation using the second parameters, and (Figs. 13-14, and Column 9, lines 51-55, Igahara teaches that while in a QLC mode, the mode switch module may switch to the TLC mode and write as TLC. As discussed above, the TLC programming is performed using second parameters.)
While Igahara teaches that the writing mode can be switched between TLC and QLC modes, Igahara does not appear to explicitly disclose remaining in the QLC mode in response to a command to perform a TLC read operation without performing the multi-parameter load to load the second parameters such that the TLC read operation is performed using the first parameters while operating in the QLC mode.
However, Li teaches remaining in the QLC mode in response to a command to perform a TLC read operation without the second parameters such that the TLC read operation is performed using the first parameters while operating in the QLC mode ([0027], [0050], Li teaches that a first more-dense mode can be used for performing operations on cells in both a first more-dense and a second less-dense array, and that read operations can still be performed for those cells that are less-densely programmed without changing the mode. Moreover, in [0047], Fig. 9B, and [0088], Li further teaches a specific embodiment where the first more-dense mode is QLC and the second less-dense mode is TLC. As discussed above, since the parameters are understood to be the amount of bits used for writing to the cell, and a read operation does not involve a writing, the second parameters for writing in the TLC mode are not used. Further, the first parameters are taught above.)
Igahara and Li are analogous art because they are from the same field of endeavor, memory devices operating in QLC and TLC modes.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the memory device with control circuitry configured to operate in both a QLC mode and TLC mode and selectively switch between the QLC and TLC modes, and to switch from the QLC mode to the TLC mode to program in TLC, as disclosed by Igahara, to also remain in the QLC mode in response to a command to perform a TLC read such that the TLC read is performed while operating in the QLC mode, as disclosed by Li.
One of ordinary skill in the art would have been motivated to make this modification in order to support both modes of programming logical states without additional hardware as discussed in Li [0028] “This concurrent programming can be performed as often as logical states can be mapped to corresponding threshold voltage (or program verify) levels, can be employed for both coarse and fine programming operations, and can be performed without additional programming hardware (e.g., charge pumps and the like) or additional control logic that is otherwise required in iPlane-enabled memory devices.”
While Igahara/Li teach that when performing a TLC or QLC write, corresponding parameters are used, Igahara and Li do not appear to explicitly disclose switching from the QLC mode to the TLC mode in response to a command to perform a TLC programming operation by performing a multi-parameter load to load the second parameters.
However, Abrahams teaches to perform a multi-parameter load ([0009] Abrahams teaches loading a variety of operational parameters to operate a memory device “The values for the one or more operational parameters may specify operating conditions for the component. A monitor may be coupled to the component and may be configured to access the values on the non-volatile memory to determine if the component is operating outside of the operating conditions… The operational parameters may indicate voltage, frequency, input current, input power, or other operating conditions for the component.”)
Igahara, Li, and Abrahams are analogous art because they are from the same field of endeavor, configurations of memory controllers.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Igahara/Li and Abrahams, to achieve the result of a method described previously, where the device switches between a QLC mode to a TLC mode to perform their respective programming operations with their respective parameters, to also perform multi-parameter loads to load the parameters taught by Igahara/Li.
One of ordinary skill in the art would have been motivated to make this modification in order to store all of the various parameters that a device would need for correct operation not specific to just QLC and TLC mode as discussed in Abrahams [0022] “The operational parameters may specify certain conditions for correct operation of the component.”
Regarding claim 12: The combination of Igahara, Li, and Abrahams teaches all limitations of claim 11, from which claim 12 depends.
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Igahara/Li/Abrahams further teaches storing, in non-volatile memory, (Fig. 1A and [0041] Li teaches a ROM on a local memory 119 of a controller “The local memory 119 can also include read-only memory (ROM) for storing micro-code.”
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Igahara/Li/Abrahams further teaches (i) the first parameters corresponding to the operation in the QLC mode and (ii) the second parameters corresponding to the operation in the TLC mode ([0027] Li teaches threshold voltage levels as QLC programming parameters “The QLC or PLC mode includes specific programming operations and parameters (such as threshold voltage levels and corresponding program verify levels).” [0089], Fig. 9, and Table 4 Li further teaches mapping corresponding TLC programming voltages “As discussed, corresponding program/read verify voltages between these logical states may also be used to map the logical states between TLC memory and QLC memory.”)
One of ordinary skill in the art would have been motivated to make this modification in order to keep the parameters available to the sub-system controller even if no power was supplied to the device as discussed in Li [0020] “A memory sub-system can include high density non-volatile memory devices where retention of data is desired when no power is supplied to the memory device.”
Regarding claim 13: The combination of Igahara, Li, and Abrahams teaches all limitations of claim 13, from which claim 14 depends.
Igahara/Li/Abrahams further teaches from the non-volatile memory into operating memory of the device ([0037] Abrahams teaches a monitor that accesses non-volatile memory to obtain operational parameters and reads it into local memory “For example, a monitor may access the non-volatile memory of the component to obtain the operational parameter values. The monitor may read the operational parameters into a local memory from which it operates.”)
One of ordinary skill in the art would have been motivated to make this modification in order to cache the parameter values to speed up device performance when operating in the various mode as discussed in Abrahams [0033] “The monitor 200 may cache the operational parameter values at power-up to reduce read traffic.” Such parameters would be treated as different kinds of the same operational parameters, and it would be obvious to store and load them the same way.
Regarding claim 14: The combination of Igahara, Li, and Abrahams teaches all limitations of claim 12, from which claim 14 depends.
Igahara/Li/Abrahams further teaches includes retrieving the first parameters or the second parameters from the non-volatile memory. ([0034] Abrahams teaches accessing different operational parameters in the non-volatile memory in response to a component change. “Monitor 200 may be configured to access the operational parameter values stored in non-volatile memory 150. For example, a component may be upgraded to a newer component, and 200 may access different operational parameter values for the newer component from the non-volatile memory 150 on the newer component.”)
One of ordinary skill in the art would have been motivated to make this modification in order to only cache the parameters as needed when operating in multiple modes to improve the current mode’s operation as discussed in Abrahams [0033] “The monitor 200 may cache the operational parameter values at power-up to reduce read traffic.”
Regarding Claim 16: The combination of Igahara, Li, and Abrahams teaches all limitations of claim 11, from which claim 16 depends.
Igahara/Li/Abrahams further teaches to switch from the TLC mode to the QLC mode in response to a command to perform at least one of a QLC read operation and a QLC programming operation (Fig. 36 Igahara teaches receiving a write command S51 while in a TLC write mode, then switching to a QLC mode at S54 to write to NAND flash memory at S57)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAITLYN HUNG PHAM whose telephone number is (571)272-6333. The examiner can normally be reached Mon-Thurs 8:00-6:00 EST.
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/K.H.P./Examiner, Art Unit 2133
/ROCIO DEL MAR PEREZ-VELEZ/Supervisory Patent Examiner, Art Unit 2133