Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
1. This office action is responsive to communication(s) filed on 2/29/2026.
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant’s submission filed on 2/29/ 2026 has been entered.
2. Claims 1-20 are presented for examination.
3. Applicant's arguments with respect to the newly added limitations have been considered but are moot in view of the rejections as set forth below. in the same reason of the previous Office action
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. § 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
5. Claims 1-3 and 5-8, are rejected under 35 U.S.C. § 103(a) as being unpatentable over Prather US Pub. No. 20210074348 (previous cited) in view of Yang US Patent No. 10241687 (previous cited).
As per claims 1-2, and 5-7, Figs. 2, 3A, 4A and 5 or 6 of Prather disclose a method, comprising: receiving, at logic (112a) coupled to a memory device (200, par. ) that includes multiple memory dies (100a-100c, abstract) divided into multiple memory channels (pass through, par. 26, banks 0-n, also see a claim 4 of Yang for channels), a signal indicative of a command to die included in the first memory channel (Fig. 2).
Prather fails to disclose a command to enter a lower- power refresh mode. However, a claim 8 of Yang discloses the low power refresh mode. It would have been obvious to a person of ordinary skill in the art at the time invention was made to modify Prather’s refresh mode which utilizes the lower power mode as taught by Yang in order to use the less power than a power mode (claim 8).
It is noted that a third memory and a fourth memory array limitations in claim 2 or 7 would be rejected by Figs. 2 and 4 of Prather even they are not shown in Fig. 2 or Fig. 4. See a paragraph 26.
It is noted that determine a duration of a respective time delay for the respective memory die … based on at least one programmable component limitations in claim 10 would be rejected by a programable register of a paragraph 33 or claim 10 of Prather.
As per claims 3 and 8, an abstract and a claim 11 of Prather disclose wherein: respective memory dies of the multiple memory dies comprise respective memory array (150s) of the memory device (abstract), and the method further comprises: determining at least one duration of the first time delay (beginning low of 415a) or the second time delay (beginning low of 417a) via a fuse-based identification (programmable register, par. 33 or claim 10) of the respective memory dies; or a ZQ identification of the respective memory dies.
6. Claims 4 and 9 are rejected under 35 U.S.C. § 103(a) as being unpatentable over Prather US Pub. No. 20210074348 in view of Yang US Patent No. 10241687 and further in view of Ayyapureddi US Pub. No. 20220374168 (previous cited).
Prather and Yang fail to disclose wherein the logic and the memory device are included in a device that operates in compliance with at least one Compute Express Link (CXL) standard. However, a paragraph 14 of Ayyapureddi discloses this limitation. It would have been obvious to a person of ordinary skill in the art at the time invention was made to add the protocol such as the Compute Express Link (CXL) standard to Prather as taught by Ayyapureddi in order to improve communications between a memory device and a memory controller.
Allowable Subject matter
7. Claims 10-20 allowed.
8. The following is a statement of reasons for the indication of allowable subject matter: determine a duration of a respective time delay for an associated array in relation to the lower-power refresh mode in claims 10 and 13; and a combination of other limitations thereof as recited in claims
Response to Arguments
9. Applicants’ arguments have been fully considered but they are not persuasive.
For the above reasons, it is believed that the rejections should be sustained. Feature of an invention not found in the claims can be given no patentable weight in distinguishing the claimed invention over the prior art.
10. When responding to the office action, Applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner to locate the appropriate paragraphs.
11. Any inquiry concerning this communication or earlier communications from the examiner should be directed to HOAI V HO whose telephone number is (571)272-1777. The examiner can normally be reached 7:00 AM -- 5:30 PM from Monday through Thursday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is (571)-273-8300.
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/HOAI V HO/Primary Examiner, Art Unit 2827
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