Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 2 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “nitrogen structure” in claim 2 is a relative term which renders the claim indefinite. The term “nitrogen structure” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The term "nitrogen structure" is indefinite because it is unclear what
For Purposes of examination, the claim is interpreted by the Examiner as follows:
Claim 2: “… wherein a multilayer structure is disposed on a surface of the substrate arranged in the second region, and the surface of the substrate arranged in the second region is a nitrogen surface.”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1, 7, 10, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng (US 20230106052 A1).
Regarding claim 1, Cheng discloses a semiconductor structure, comprising: a substrate (Fig. 2b, element 10; ¶: [0076]) comprising a first region (Fig. 2b, element 10a; ¶: [0076]) and a second region (Fig. 2b, element 10b, 10c; ¶: [0076]), the second region surrounding the first region; a first N-type heavily-doped semiconductor layer (Fig. 2b, element 123; ¶: [0085]), a channel layer (Fig. 2b, element 121; ¶: [0085]), and a second N-type heavily-doped semiconductor layer (Fig. 2b, element 122; ¶: [0085]) arranged on the first region sequentially; a source electrode (Fig. 1, element 13b; ¶: [0079]) connected to the second N-type heavily-doped semiconductor layer; a drain electrode (Fig. 1, element 13c; ¶: [0079]) connected to the first N-type heavily-doped semiconductor layer; and a gate electrode (Fig. 1, element 13a; ¶: [0079]) wrapping around sidewall of the channel layer.
It is noted that the term “surrounding” is taken as a first region (row) 1a and second region (row) 1b extending parallel to each other, where the first region is between second regions 1b.
However, Cheng does not specifically disclose a patterned structure sequenced before the first heavily-doped semiconductor layer, the channel layer, and the second heavily-doped semiconductor layer in the first region.
Cheng does disclose a patterned structure (Fig. 2b, element 11; ¶: [0036, 0077]) sequenced before the first heavily-doped semiconductor layer, the channel layer, and the second heavily-doped semiconductor disposed within the second region.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a pattern structure to the first region to further support the source/drain/gate sections of the semiconductor structure (¶: [0010-0014]).
Regarding claim 7, Cheng teaches the semiconductor structure of claim 1. Cheng further teaches a dielectric layer (Fig. 9, element 14; ¶: [0130]) wrapping around the sidewall of the channel layer, wherein the gate electrode (Fig. 9, element 13a, 14; ¶: [0130]) wraps around sidewall of the dielectric layer away from the channel layer (Fig. 9, element 12; ¶: [0111]).
Regarding claim 10, Cheng teaches the semiconductor structure of claim 1. Cheng further teaches the channel layer being a nanowire structure or a nanosheet structure (Fig. 1, element 12; ¶: [0078]).
Regarding claim 11, Cheng teaches the semiconductor structure of claim 1. Cheng is silent on wherein a shape of a cross-section of the patterned structure comprises any one of triangle, circle, ellipse and polygon, and the cross-section is parallel to the substrate.
However, the claimed features are related to a change in shape of disclosed features. "The applicant has not presented persuasive evidence that the claimed dimensions are for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed dimensions). Also, the applicant has not shown that the claimed dimensions produce a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art."
Therefore, before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to choose a known and commonly used shape because where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.MPEP 2144.04 (IV)(A)
Claims 2-5, 8-9, 12-17, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Then et al. (US 9397188 B2) hereinafter referred to as "Then".
Regarding claim 2, Cheng teaches a nitrogen structure (Fig. 2b, element 121, 122, 123; ¶: [0085]) being disposed on a surface of the substrate arranged in the second region.
Cheng does not teach the surface of the substrate arranged in the second region being a nitrogen surface.
Then teaches the surface of the substrate (Fig. 1A, element 205; column 3 line 58-64) arranged in the second region being a nitrogen surface (Fig. 1A, element 205; column 3 line 58-64).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the surface be a nitrogen surface in order to enhanced channel mobility, sheet charge, passivation of interfacial states, or energy barriers for channel charge carrier confinement. (column 3 line 44-47).
Regarding claim 3, Cheng teaches the semiconductor structure of claim 1, but does not teach a third N-type heavily-doped semiconductor layer arranged on the second region, surrounding and connecting to sidewall of the first N-type heavily-doped semiconductor layer, wherein the drain electrode is connected to the first N-type heavily-doped semiconductor layer through the third N-type heavily-doped semiconductor layer.
Then teaches a third N-type heavily-doped semiconductor layer (Fig. 1C, element 212A; column 7 line 59-63) arranged on the second region, surrounding and connecting to sidewall of the first N-type heavily-doped semiconductor layer, wherein the drain electrode is connected to the first N-type heavily-doped semiconductor layer through the third N-type heavily-doped semiconductor layer (Fig. 1C, element 212C; column 7 line 59-63).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a semiconductor layer made of a potentially different material allowing for an intermediary of the bandgap of the channel layer (column 8 line 14-20).
Regarding claim 4, Cheng in view of Then teaches the semiconductor structure of claim 3. Cheng does not teach a material of the third N-type heavily-doped semiconductor layer being a group III nitride material, and a surface of the third N-type heavily-doped semiconductor layer away from the substrate being a nitrogen surface.
Then teaches a material of the third N-type heavily-doped semiconductor layer being a group III nitride material (Fig. 1C, element 212a; column 8 line 4-6), and a surface of the third N-type heavily-doped semiconductor layer away from the substrate being a nitrogen surface (Fig. 1C, element 212a; column 3 line 41-43).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the surface be a nitrogen surface in order to enhanced channel mobility, sheet charge, passivation of interfacial states, or energy barriers for channel charge carrier confinement. (column 3 line 44-47).
Regarding claim 5, Cheng teaches the semiconductor structure of claim 1, as well as a material of the patterned structure, the first N-type heavily-doped semiconductor layer, the channel layer, and the second N-type heavily-doped semiconductor layer being a group III nitride material (Fig. 2b, element 121, 122, 123; ¶: [0084]).
Cheng does not teach surfaces of the patterned structure, the first N-type heavily-doped semiconductor layer, the channel layer, and the second N-type heavily-doped semiconductor layer close to the substrate being nitrogen surfaces.
Then teaches surfaces of the patterned structure, the first N-type heavily-doped semiconductor layer, the channel layer, and the second N-type heavily-doped semiconductor layer close to the substrate are nitrogen surfaces (Fig. 1A, element 212b; column 3 line 41-43).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the surface be a nitrogen surface in order to enhanced channel mobility, sheet charge, passivation of interfacial states, or energy barriers for channel charge carrier confinement. (column 3 line 44-47).
Regarding claim 8, Cheng teaches the semiconductor structure of claim 7. Cheng does not teach a material of the dielectric layer comprising any one of high-dielectric-constant material of HfO2, Al2O3 and Si3N4.
Then teaches a material of the dielectric layer comprising any one of high-dielectric-constant material of HfO2, Al2O3 and Si3N4. (Fig. 1b, element 240; column 7 line 39).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the dielectric material be a high K dielectric as it is known in the art as suitable for FET gate dielectrics (column 7 line 34-36).
Regarding claim 9, Cheng teaches the semiconductor structure of claim 1. Cheng does not teach the channel layer being an N-type lightly-doped layer, and a doping concentration of the channel layer being less than 1E18.
Then teaches the channel layer being an N-type lightly-doped layer (Fig. 1a, element 245; column 4 line 41-46), and a doping concentration of the channel layer being less than 1E18 (Fig. 1a, element 245; column 4 line 41-46).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have very little to no doping in the channel layer in order to have relatively high carrier mobility (column 4 line 41-43).
Regarding claim 12, Cheng teaches a manufacturing method of a semiconductor structure, comprising: providing a substrate (Fig. 2b, element 10; ¶: [0027]), wherein the substrate comprises a first region (Fig. 2b, element 10a; ¶: [0027]) and a second region (Fig. 2b, element 10b, 10c; ¶: [0027]), and the second region surrounds the first region; preparing a patterned structure (Fig. 2b, element 11; ¶: [0027]) on the first region; preparing a channel layer (Fig. 2b, element 121; ¶: [0028]) and a second N-type heavily-doped semiconductor layer (Fig. 1, element 13c; ¶: [0028]) on the first N-type heavily-doped semiconductor layer sequentially; preparing a gate electrode (Fig. 1, element 13a; ¶: [0030]) wrapping around sidewall of the channel layer; preparing a drain electrode (Fig. 1, element 13c; ¶: [0030]) on the third N-type heavily-doped semiconductor layer; and preparing a source electrode (Fig. 1, element 13b; ¶: [0030]) on the second N-type heavily-doped semiconductor layer. Cheng does not teach preparing a patterned structure on the first region; preparing a third N-type heavily-doped semiconductor layer and a first N-type heavily-doped semiconductor layer on the substrate and the patterned structure simultaneously, wherein the third N-type heavily-doped semiconductor layer is arranged on the second region, and the first N-type heavily-doped semiconductor layer is arranged on the patterned structure.
Then teaches preparing a third N-type heavily-doped semiconductor layer and a first N-type heavily-doped semiconductor layer on the substrate and the patterned structure simultaneously (Fig. 3, element 212a, 212c; column 10 line 1-3), wherein the third N-type heavily-doped semiconductor layer is arranged on the second region, and the first N-type heavily-doped semiconductor layer is arranged on the patterned structure (Fig. 3, element 212a, 212c; column 10 line 1-3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form them simultaneously as the thickness of one layer is dependent on the desired dimensions of the other (column 10 line 13-16).
Regarding claim 13, Cheng in view of Then teaches the manufacturing method of the semiconductor structure of claim 12. Cheng does not teach after the preparing a patterned structure on the first region, further comprising: nitriding a surface of the second region of the substrate.
Then teaches after the preparing a patterned structure on the first region, further comprising: nitriding a surface of the second region of the substrate (Fig. 1A, element 205; column 3 line 58-64).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the surface be a nitrogen surface in order to enhanced channel mobility, sheet charge, passivation of interfacial states, or energy barriers for channel charge carrier confinement. (column 3 line 44-47).
Regarding claim 14, Cheng in view of Then teaches the manufacturing method of the semiconductor structure of claim 12. Cheng further teaches preparing a channel layer and a second N-type heavily-doped semiconductor layer on the first N-type heavily-doped semiconductor layer sequentially comprising: preparing the channel layer and the second N-type heavily-doped semiconductor layer simultaneously and sequentially; and removing a channel layer and a second N-type heavily-doped semiconductor layer on the third N-type heavily-doped semiconductor layer (Fig. 4, element 123; ¶: [0028-0029]).
Regarding claim 15, Cheng in view of Then teaches the manufacturing method of the semiconductor structure of claim 12. Cheng further teaches preparing a channel layer and a second N-type heavily-doped semiconductor layer on the first N-type heavily-doped semiconductor layer sequentially comprising: preparing the channel layer and the second N-type heavily-doped semiconductor layer simultaneously and sequentially (Fig. 4, element 122, 245; ¶: [0028-0029]); removing a third N-type heavily-doped semiconductor layer the channel layer and a second N-type heavily-doped semiconductor layer arranged on the second region and preparing the drain electrode on sidewall of the first N-type heavily-doped semiconductor layer (Fig. 4, element 13a, 13b, 13c; ¶: [0030]).
Regarding claim 16, Cheng in view of Then teaches the manufacturing method of the semiconductor structure of claim 12. Cheng does not teach a material of the third N-type heavily-doped semiconductor layer, the patterned structure, the first N-type heavily-doped layer, the channel layer, and the second N-type heavily-doped semiconductor layer being a group III nitride material, and a surface of the third N-type heavily-doped semiconductor layer away from the substrate being a nitrogen surface, and surfaces of the patterned structure, the first N-type heavily-doped layer, the channel layer and the second N-type heavily-doped semiconductor layer close to the substrate being nitrogen surfaces.
Then teaches a material of the third N-type heavily-doped semiconductor layer (Fig. 1C, element 212a; column 8 line 4-6), the patterned structure (Fig. 4A, element 407; column 10 line 17-19), the first N-type heavily-doped layer (Fig. 1C, element 212c; column 10 line 1-3), the channel layer Fig. 1C, element 245; column 8 line 20-24, and the second N-type heavily-doped semiconductor layer (Fig. 1C, element 212c; column 10 line 1-3) being a group III nitride material and a surface of the third N-type heavily-doped semiconductor layer away from the substrate being a nitrogen surface (Fig. 1C, element 212a; column 3 line 41-43), and surfaces of the patterned structure, the first N-type heavily-doped layer, the channel layer and the second N-type heavily-doped semiconductor layer close to the substrate being nitrogen surfaces (Fig. 1A, element 212b; column 3 line 41-43).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the surface be a nitrogen surface in order to enhanced channel mobility, sheet charge, passivation of interfacial states, or energy barriers for channel charge carrier confinement (column 3 line 44-47)
Regarding claim 17, Cheng in view of Then teaches the manufacturing method of the semiconductor structure of claim 12. Cheng further teaches preparing the gate electrode on the sidewall of the dielectric layer away from the channel layer, wherein the gate electrode wraps around the sidewall of the dielectric layer away from the channel layer (Fig. 4, element 13a; ¶: [33]). Cheng does not teach preparing a gate electrode on sidewall of the channel layer further comprising: preparing a dielectric layer on the third N-type heavily-doped semiconductor layer and the sidewall of the channel layer, wherein the dielectric layer wraps around the sidewall of the channel layer.
Then teaches preparing a gate electrode on sidewall of the channel layer further comprising: preparing a dielectric layer on the third N-type heavily-doped semiconductor layer and the sidewall of the channel layer, wherein the dielectric layer wraps around the sidewall of the channel layer (Fig. 4D, element 250; column 10 line 46-48).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a dielectric layer to fill any gaps caused form the semiconductor layer (column 10 line 51-52).
Regarding claim 20, Cheng in view of Then teaches the manufacturing method of the semiconductor structure of claim 12. Cheng does not teach preparing a channel layer and a second N-type heavily-doped semiconductor layer on the first N-type heavily-doped layer sequentially comprising: performing an N-type ions doping process to the channel layer, wherein a doping concentration of the channel layer is less than 1E18.
Then teaches preparing a channel layer and a second N-type heavily-doped semiconductor layer on the first N-type heavily-doped layer sequentially comprising: performing an N-type ions doping process to the channel layer, wherein a doping concentration of the channel layer is less than 1E18 (Fig. 1a, element 245; column 4 line 41-46).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have very little to no doping in the channel layer in order to have relatively high carrier mobility (column 4 line 41-43).
Allowable Subject Matter
Claims 6, 18, and 19 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 6, Chen in view of Then teach certain elements of the claimed invention such as a first, second, and third N-type heavily doped semiconductor layer, a channel layer, a pattern layer, as well as a source, drain, and gate electrode.
However, the prior art of record to the examiner’s knowledge when taken alone or in combination does not teach the element of the invention claimed by the applicant regarding: “at least one N-type lightly-doped insertion layer arranged in the first N-type heavily-doped semiconductor layer and/or the third N-type heavily-doped semiconductor layer”.
Regarding claim 18, Chen in view of Then teach certain elements of the claimed invention such as a substrate, on which is disposed is a first, second, and third N-type heavily doped semiconductor layer, a channel layer, a pattern layer, as well as a source, drain, and gate electrode
However, the prior art of record to the examiner’s knowledge when taken alone or in combination does not teach the element of the invention claimed by the applicant regarding:” preparing the third N-type heavily-doped semiconductor layer and the first N-type heavily-doped semiconductor layer on the substrate and the patterned structure simultaneously comprising: forming at least one N-type lightly-doped insertion layer in the third N-type heavily-doped semiconductor layer and/or the first N-type heavily-doped semiconductor layer”.
Regarding claim 19, Chen in view of Then teach certain elements of the claimed invention such as a first, second, and third N-type heavily doped semiconductor layer, a channel layer, a pattern structure, as well as a source, drain, and gate electrode.
However, the prior art of record to the examiner’s knowledge when taken alone or in combination does not teach the element of the invention claimed by the applicant regarding:” a shape of a cross-section of the patterned structure comprising any one of triangle, circle, ellipse, and polygon, and the cross-section is parallel to the substrate”.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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/I.H./Examiner, Art Unit 2899 /LAWRENCE C TYNES JR./Examiner, Art Unit 2899
Prosecution Insights