DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note by the Examiner
For clarity, references to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and examiner explanations for 102 &/or 103 rejections are provided in parenthesis.
Election/Restrictions
Applicant’s election without traverse of Invention I, drawn to claims 1-5, in the reply filed on 06/11/2026 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choi et al. (Pub. No.: US 20130048994 A1), hereinafter as Choi.
With regards to claim 1, Choi teaches an array substrate, comprising: a substrate (see Choi Fig. 2, substrate 110; Choi [0033]), a gate layer (see Choi Fig. 2, gate electrode 124; Choi [0033]), a gate insulating layer (see Choi Fig. 2, gate insulating film 140; Choi [0035]), a semiconductor layer (see Choi Fig. 2, semiconductor layer 154; Choi [0035]), a source and drain layer (see Choi Fig. 2, source electrode 173 and a drain electrode 175; Choi [0037]), and a protective layer (see Choi Fig. 2, protective film 180; Choi [0041]) stacked in sequence (see Choi Fig. 2); wherein the source and drain layer comprises: a metal laminated layer (see Choi Fig. 2, first source electrode 165s, first drain electrode 165d, second source electrode 174s, and second drain electrode 174d; Choi [0037]) disposed on the semiconductor layer (see Choi Fig. 2); and an antioxidant protective layer (see Choi Fig. 2, third source electrode 177s and third drain electrode 177d; Choi [0037]; also see Choi [0040]: “The third source electrode 177s and the third drain electrode 177d may prevent the second source electrode 174s and the second drain electrode 174d from being oxidized in a below-described process of forming a first protective film 181 or a second protective film 183.” thus showing that third source electrode 177s and third drain electrode 177d are antioxidant.) disposed between the metal laminated layer and the protective layer (see Choi Fig. 2).
With regards to claim 2, Choi teaches the array substrate of claim 1, wherein the metal laminated layer (see Choi Fig. 2, first source electrode 165s, first drain electrode 165d, second source electrode 174s, and second drain electrode 174d) comprises: a first metal layer (see Choi Fig. 2, first source electrode 165s and first drain electrode 165d) disposed on the semiconductor layer (see Choi Fig. 2, semiconductor layer 154); and a second metal layer (see Choi Fig. 2, second source electrode 174s and second drain electrode 174d) disposed on the first metal layer (see Choi Fig. 2).
With regards to claim 3, Choi teaches the array substrate of claim 2, wherein a material of the first metal layer (see Choi Fig. 2, first source electrode 165s and first drain electrode 165d) comprises molybdenum element and/or titanium element (see Choi [0038]: “For example, the first source electrode 165s and the first drain electrode 165d may include gallium zinc oxide (GaZnO), titanium (Ti), titanium alloy (such as TiN), molybdenum (Mo), copper, copper alloy (such as CuMn), or Cu-alloy nitride (such as CuMnN).”; where one would choose either molybdenum or titanium.); and a material of the second metal layer (see Choi Fig. 2, second source electrode 174s and second drain electrode 174d) is copper (see Choi [0039]: “The second source electrode 174s and the second drain electrode 174d may include copper or copper alloy.”).
With regards to claim 4, Choi teaches the array substrate of claim 1, wherein a material of the antioxidant protective layer (see Choi Fig. 2, third source electrode 177s and third drain electrode 177d) comprises nitrogen element (see Choi [0040]: “The third source electrode 177s and the third drain electrode 177d may be formed of Cu-alloy nitride, … , or CuMn nitride (CuMnN).”).
With regards to claim 5, Choi teaches the array substrate of claim 1, wherein a material of the protective layer (see Choi Fig. 2, protective film 180) is silicon oxide compound (see Choi [0043]: “The protective film 180 may include the first protective film 181 and the second protective film 183. The first protective film 181 may be formed of silicon oxide (SiOx), and the second protective film 183 may be formed of silicon nitride (SiNx).”).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EKATERINA T BIRCH whose telephone number is (571)272-8676. The examiner can normally be reached Mon-Fri, 8am-4pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke can be reached at 5712721657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/E.T.B./Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
Prosecution Insights