Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office action is in response to Applicant' s communication filed 1/5/2026 in response to the Office action dated 10/15/2025. Claim 21 has been cancelled. New claim 22 has been added. Claims 1-7, 9-20, and 22 are pending in this application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 12-14, and 20 are rejected under 35 U.S.C 103 as being unpatentable over Ryu (US 20130114354 A1) in view of Igahara et al. (US 20190095116 A1), hereinafter Igahara, and further in view of Balasubramaniam et al. (US 10991387 B1), hereinafter Balasubramaniam.
Regarding claim 1, Ryu teaches an apparatus, comprising: a memory device (Paragraph 28, Fig. 1, nonvolatile memory 100);
and a controller coupled with the memory device (Paragraph 28, Fig. 1, controller 200);
and configured to cause the apparatus to: write first data to a first data block of a memory system based at least in part on a first logical type of the first data (Paragraphs 42, 58; Fig. 4, hot type data [first logical type] is stored in first memory area 111 [first data block] consisting of memory blocks);
write second data to the first data block based at least in part on a second logical type of the second data (Paragraph 58; Fig. 4, random type data [second logical type] is temporarily stored in first memory area 111 [first data block]),
the first logical type and the second logical type associated with storage to a same type of memory cell (Paragraph 43, first memory area 111 consists of single-bit data memory cells),
and a second data block of the memory system (Paragraphs 42, 58; Fig. 4, second memory area 112 [second data block] consisting of memory blocks).
Ryu does not explicitly teach increment, in response to writing the first data, a first counter associated with tracking a first quantity of data written to the first data block that is of the first logical type; increment, in response to writing the second data, a second counter associated with tracking a second quantity of data written to the first data block that is of the second logical type; and perform, after writing the first data and the second data to the first data block and based at least in part on the first quantity of data written to the first data block that is of the first logical type exceeding a threshold quantity, a media management operation to transfer at least the first data to a second data block of the memory system.
However, Igahara teaches to increment, in response to writing the first data, a first counter associated with tracking a first quantity of data written to the first data block that is of the first logical type (Paragraph 69; Fig. 7, in response to a write command, tracking an amount [counter] of high access frequency data [first type] written within [first data] block ID 1); and
increment, in response to writing the second data, a second counter associated with tracking a second quantity of data written to the first data block that is of the second logical type (Paragraph 69; Fig. 7, in response to a write command, tracking an amount [counter] of low access frequency data [second type] written within [first data] block ID 1).
Ryu and Igahara are analogous art because they are in the same field of endeavor, that being data type storage management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the storage device of Ryu to further include the first and second counters according to the teachings of Igahara. The motivation for doing so would have been to improve garbage collection performance (Igahara, Paragraph 208).
Ryu in view of Igahara does not explicitly teach to perform, after writing the first data and the second data to the first data block and based at least in part on the first quantity of data written to the first data block that is of the first logical type exceeding a threshold quantity, a media management operation to transfer at least the first data to a second data block of the memory system.
However, Balasubramaniam teaches to perform, after writing the first data and the second data to the first data block and based at least in part on the first quantity of data written to the first data block that is of the first logical type exceeding a threshold quantity, a media management operation to transfer at least the first data to a second data block of the memory system (Col. 4, lines 3-20; Fig. 5B, blocks 64-70, in response to a write command and the amount of cold data [first type] reaching a predetermined threshold [quantity], migrating the data to a different location).
The Examiner notes that Ryu teaches the first and second data blocks while Balasubramaniam teaches the media management operation.
Ryu, Igahara, and Balasubramaniam are analogous art because they are in the same field of endeavor, that being data type storage management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the storage device of Ryu in view of Igahara to further include the media management operation according to the teachings of Balasubramaniam. The motivation for doing so would have been to preserve the life of the memory device (Balasubramaniam, Col. 3, lines 32-35).
Regarding claim 12, Ryu in view of Igahara, further in view of Balasubramaniam teaches the apparatus of claim 1, wherein: the first logical type comprises data associated with a first likelihood of being overwritten within a duration after being written (Ryu, Paragraph 54, hot data),
data associated with a second likelihood of being overwriting within the duration (Ryu, Paragraph 54, cold data),
write booster data, user data, data associated with a first zone of the memory system, redundant array of independent not-and (NAND) parity data, firmware data, or data associated with a first zone of the memory system (Ryu, Paragraph 57, random data stored in first memory area 111),
and the second logical type comprises the data associated with the first likelihood of being overwritten within the duration (Ryu, Paragraph 54, hot data),
the data associated with the second likelihood of being overwriting within the duration (Ryu, Paragraph 54, cold data),
write booster data, user data, data associated with a second zone of the memory system, redundant array of independent not-and (NAND) parity data, firmware data, or data associated with a second zone of the memory system (Ryu, Paragraph 57, sequential data stored in second memory area 111), the second logical type being different than the first logical type.
Regarding claim 13, Ryu in view of Igahara, further in view of Balasubramaniam teaches the apparatus of claim 1, wherein the type of memory cell comprises a single level memory cell associated with a first access latency, a single level memory cell associated with a second access latency that is less than the first access latency, or a multiple-level memory cell (Ryu, Paragraph 29, first memory area 111 comprises single-bit memory cells [SLC] and second memory area 112 comprises multi-bit memory cells [MLC], the single-bit memory cells [SLC] having a lower access latency than the multi-bit memory cells [MLC]).
Regarding claim 14, this is a computer-readable medium version of the claimed apparatus discussed above (claim 1, respectively), in which Ryu in view of Igahara, further in view of Balasubramaniam also teaches a non-transitory computer-readable medium storing code comprising instructions which are executable by a processor (Ryu, Paragraph 115; Fig. 15, computing system 4000, RAM 4200, CPU 4100).
The remaining claim limitations have been addressed and/or covered in the cited areas as set forth above. Thus, accordingly, this claim is also obvious over Ryu in view of Igahara, further in view of Balasubramaniam.
Regarding claim 20, this is a method version of the claimed apparatus discussed above (claim 1, respectively), wherein all claim limitations also have been addressed and/or covered in the cited areas as set forth above. Thus, accordingly, this claim is also obvious over Ryu in view of Igahara, further in view of Balasubramaniam.
Claims 2-7 and 15-19 are rejected under 35 U.S.C 103 as being unpatentable over Ryu in view of Igahara, further in view of Balasubramaniam as applied to claims 1 and 14 above, and further in view of Saxena et al. (US 20200401334 A1), hereinafter Saxena.
Regarding claim 2, Ryu in view of Igahara, further in view of Balasubramaniam teaches the apparatus of claim 1, but does not explicitly teach wherein, to perform the media management operation, the controller is configured to cause the apparatus to: transfer the second data to a third data block of the memory system, wherein the second data block is associated with exclusive storage of data of the first logical type and the third data block is associated with exclusive storage of data of the second logical type.
However, Saxena teaches wherein, to perform the media management operation, the controller is configured to cause the apparatus to: transfer the second data to a third data block of the memory system (Paragraphs 61-63; Fig. 3, SLC sequential data [second data type] is transferred from the write cache to the SLC S block [third data block] in non-volatile memory 104 via controller 102),
wherein the second data block is associated with exclusive storage of data of the first logical type (Paragraph 61; Fig. 3, SLC R block [second data block] region exclusively stores SLC random data [first logical type])
and the third data block is associated with exclusive storage of data of the second logical type (Paragraph 61; Fig. 3, SLC S block [third data block] region exclusively stores SLC sequential data [second logical type]).
Ryu, Igahara, Balasubramaniam, and Saxena are analogous art because they are in the same field of endeavor, that being data type storage management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the apparatus of Ryu in view of Igahara, further in view of Balasubramaniam to further include more memory regions for exclusive storage of different data types according to the teachings of Saxena. The motivation for doing so would have been to increase write performance and compacting of data (Saxena, Paragraph 28).
Regarding claim 3, Ryu in view of Igahara, further in view of Balasubramaniam teaches the apparatus of claim 1, but does not explicitly teach wherein the controller is further configured to cause the apparatus to: write third data to a third data block based at least in part on a third logical type of the third data being associated with storage to a second type of memory cell different than the type of memory cell associated with the first logical type and the second logical type.
However, Saxena teaches wherein the controller is further configured to cause the apparatus to: write third data to a third data block based at least in part on a third logical type of the third data being associated with storage to a second type of memory cell different than the type of memory cell associated with the first logical type and the second logical type (Paragraph 60, Fig. 3, video data [third data type] is transferred to the MLC S1 block region [distinct from SLC cells for first and second data types] in non-volatile memory 104 via controller 102).
Ryu, Igahara, Balasubramaniam, and Saxena are analogous art because they are in the same field of endeavor, that being data type storage management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the apparatus of Ryu in view of Igahara, further in view of Balasubramaniam to further include the third data type and data block according to the teachings of Saxena. The motivation for doing so would have been to increase write performance and compacting of data (Saxena, Paragraph 28).
Regarding claim 4, Ryu in view of Igahara teaches the apparatus of claim 1 and the first data block (Ryu, Paragraphs 42, 58; Fig. 4, first memory area 111 [first data block] consisting of memory blocks).
Ryu in view of Igahara does not explicitly teach wherein the controller is further configured to cause the apparatus to: determine, based at least in part on writing the first data to the first data block to which the second data is also written, whether a threshold quantity of data having the first logical type has been written to one or more data blocks associated with the type of memory cell and comprising the first data block, wherein the media management operation is performed based at least in part on the threshold quantity of data having been written.
However, Balasubramaniam teaches wherein the controller is further configured to cause the apparatus to: determine, based at least in part on writing the first data to the first data block to which the second data is also written (Col. 3, lines 21-27, 36-55; Fig. 4, blocks 50-52, writing hot and cold data to the same location (NEA disk surface)),
whether a threshold quantity of data having the first logical type has been written to one or more data blocks and comprising the first data block (Col. 4, lines 7-12; Fig. 5A, block 64, determining whether the amount of cold data [first type] stored exceeds a predetermined threshold),
wherein the media management operation is performed based at least in part on the threshold quantity of data having been written (Col. 4, lines 7-20; Fig. 5A, blocks 64-70, migrating data based on the amount of cold data exceeding a predetermined threshold).
Ryu, Igahara, and Balasubramaniam are analogous art because they are in the same field of endeavor, that being data type storage management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the storage device of Ryu in view of Igahara to further include the media management operation according to the teachings of Balasubramaniam. The motivation for doing so would have been to preserve the life of the memory device (Balasubramaniam, Col. 3, lines 32-35).
Ryu in view of Igahara, further in view of Balasubramaniam does not explicitly teach blocks associated with the type of memory cell.
However, Saxena teaches blocks associated with the type of memory cell (Paragraph 52; Fig. 3, SLC R blocks comprise of blocks with SLC memory cells).
Ryu, Igahara, Balasubramaniam, and Saxena are analogous art because they are in the same field of endeavor, that being data type storage management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the apparatus of Ryu in view of Igahara, further in view of Balasubramaniam to further include the blocks associated with the type of memory cell according to the teachings of Saxena. The motivation for doing so would have been to increase write performance and compacting of data (Saxena, Paragraph 28).
Regarding claim 5, Ryu in view of Igahara, further in view of Balasubramaniam teaches the apparatus according to claim 4, but does not explicitly teach wherein the controller is further configured to cause the apparatus to: determine, based at least in part on writing the second data to the first data block, whether a second threshold quantity of data having the second logical type has been written to the one or more data blocks, wherein the second data is transferred to a third data block of the memory system as part of the media management operation based at least in part on the second threshold quantity of data having been written.
However, Saxena teaches wherein the controller is further configured to cause the apparatus to: determine, based at least in part on writing the second data to the first data block, whether a second threshold quantity of data having the second logical type has been written to the one or more data blocks (Paragraph 86; Fig. 8B, step 866, controller 102 determines whether the number of open blocks in each data stream [data type] is sufficiently full based on another percentage threshold [“other percentages can be used”]),
wherein the second data is transferred to a third data block of the memory system as part of the media management operation based at least in part on the second threshold quantity of data having been written (Paragraph 90, Figs. 11A and 11B, open blocks for the sequential data stream [used for writing the second logical type, SLC sequential data to the third data block, SLC S] are determined based on which blocks are sufficiently full).
Ryu, Igahara, Balasubramaniam, and Saxena are analogous art because they are in the same field of endeavor, that being data type storage management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the apparatus of Ryu in view of Igahara, further in view of Balasubramaniam to further include determining whether a second capacity threshold has been met in a certain data type when writing data according to the teachings of Saxena. The motivation for doing so would have been to reduce the scanning time necessary to reconstitute open block tables (Saxena, Paragraph 85).
Regarding claim 6, Ryu in view of Igahara, further in view of Balasubramaniam teaches the apparatus of claim 1, but does not explicitly teach wherein the controller is further configured to cause the apparatus to: determine, based at least in part on writing the first data and the second data, whether a quantity of filled data blocks associated with storage of the first logical type and the second logical type satisfies a threshold quantity, wherein a filled data block excludes empty pages of memory cells, and wherein the media management operation is performed based at least in part on the quantity of filled data blocks satisfying the threshold quantity.
However, Saxena teaches wherein the controller is further configured to cause the apparatus to: determine, based at least in part on writing the first data and the second data, whether a quantity of filled data blocks associated with storage of the first logical type and the second logical type satisfies a threshold quantity (Paragraph 86; Fig. 8B, step 866, in writing next data, controller 102 determines whether the number of open blocks in each stream [data type] is sufficiently full based on a percentage threshold),
wherein a filled data block excludes empty pages of memory cells, and wherein the media management operation is performed based at least in part on the quantity of filled data blocks satisfying the threshold quantity (Paragraph 86, Fig. 8B, steps 868 and 870, if the threshold is met, then the open block table is updated to be used in the next write).
Ryu, Igahara, Balasubramaniam, and Saxena are analogous art because they are in the same field of endeavor, that being data type storage management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the apparatus of Ryu in view of Igahara, further in view of Balasubramaniam to further include the threshold quantity operations according to the teachings of Saxena. The motivation for doing so would have been to reduce the scanning time for open blocks (Saxena, Paragraph 85).
Regarding claim 7, Ryu in view of Igahara, further in view of Balasubramaniam teaches the apparatus of claim 6, but does not explicitly teach wherein the threshold quantity is based at least in part on a percentage of a total quantity of data blocks of the memory system that are filled.
However, Saxena teaches wherein the threshold quantity is based at least in part on a percentage of a total quantity of data blocks of the memory system that are filled (Paragraph 86, threshold is based on the total number of open blocks that are sufficiently full).
Ryu, Igahara, Balasubramaniam, and Saxena are analogous art because they are in the same field of endeavor, that being data type storage management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the apparatus of Ryu in view of Igahara, further in view of Balasubramaniam to further include the threshold quantity according to Saxena. The motivation for doing so would have been to be able to reduce the scanning time for open blocks (Saxena, Paragraph 85).
Regarding claim 15, this is a computer-readable medium version of the claimed apparatus discussed above (claim 2, respectively), wherein all claim limitations also have been addressed and/or covered in the cited areas as set forth above. Thus, accordingly, this claim is also obvious over Ryu in view of Igahara, further in view of Balasubramaniam and Saxena.
Regarding claim 16, this is a computer-readable medium version of the claimed apparatus discussed above (claim 3, respectively), wherein all claim limitations also have been addressed and/or covered in the cited areas as set forth above. Thus, accordingly, this claim is also obvious over Ryu in view of Igahara, further in view of Balasubramaniam and Saxena.
Regarding claim 17, this is a computer-readable medium version of the claimed apparatus discussed above (claim 4, respectively), wherein all claim limitations also have been addressed and/or covered in the cited areas as set forth above. Thus, accordingly, this claim is also obvious over Ryu in view of Igahara, further in view of Balasubramaniam and Saxena.
Regarding claim 18, this is a computer-readable medium version of the claimed apparatus discussed above (claim 5, respectively), wherein all claim limitations also have been addressed and/or covered in the cited areas as set forth above. Thus, accordingly, this claim is also obvious over Ryu in view of Igahara, further in view of Balasubramaniam and Saxena.
Regarding claim 19, this is a computer-readable medium version of the claimed apparatus discussed above (claim 6, respectively), in which Ryu in view of Igahara, further in view of Balasubramaniam and Saxena also teaches a non-transitory computer-readable medium storing code comprising instructions which are executable by a processor (Ryu, Paragraph 115; Fig. 15, computing system 4000, RAM 4200, CPU 4100).
The remaining claim limitations have been addressed and/or covered in the cited areas as set forth above. Thus, accordingly, this claim is also obvious over Ryu in view of Igahara, further in view of Balasubramaniam and Saxena.
Claim 9 is rejected under 35 U.S.C 103 as being unpatentable over Ryu in view of Igahara, further in view of Balasubramaniam as applied to claim 1 above, and further in view of Kanteti (US 20220197508 A1).
Regarding claim 9, Ryu in view of Igahara, further in view of Balasubramaniam teaches the apparatus of claim 1 and the first data block (Ryu, Paragraphs 42, 58; Fig. 4, first memory area 111 [first data block] consisting of memory blocks).
Ryu in view of Igahara, further in view of Balasubramaniam does not explicitly teach wherein the controller is further configured to cause the apparatus to: write first metadata to the first data block, the first metadata indicating that the first data has the first logical type; and write second metadata to the first data block, the second metadata indicating that the second data has the second logical type.
However, Kanteti teaches wherein the controller is further configured to cause the apparatus to: write first metadata to the first data block, the first metadata indicating that the first data has the first logical type; and write second metadata to the first data block, the second metadata indicating that the second data has the second logical type (Paragraph 17, assigning stream ID’s [a form of metadata] to allocation data to indicate a particular data type).
Ryu, Igahara, Balasubramaniam, and Kanteti are analogous art because they are in the same field of endeavor, that being writing data to a storage device based on data type. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the apparatus of Ryu in view of Igahara, further in view of Balasubramaniam to further include metadata indicating the type of data according to the teachings of Kanteti. The motivation for doing so would have been to significantly reduce mapping overhead. (Kanteti, Paragraph 21).
Claim 10 is rejected under 35 U.S.C 103 as being unpatentable over Ryu in view of Igahara, further in view of Balasubramaniam as applied to claim 1 above, and further in view of Saxena and Chang (US 20110161563 A1).
Regarding claim 10, Ryu in view of Igahara, further in view of Balasubramaniam teaches the apparatus of claim 1, but does not explicitly teach wherein the controller is further configured to cause the apparatus to: write third data to a third data block of the memory system based at least in part on a third logical type of the third data; write fourth data to the third data block based at least in part on a fourth logical type of the fourth data, the third logical type and the fourth logical type associated with storage to a second type of memory cell; determine to perform a second media management operation to transfer valid data from the third data block; and perform the second media management operation to transfer, to a fourth data block of the memory system, a portion of the third data comprising a first quantity of valid data and a portion of the fourth data comprising a second quantity of valid data based at least in part on the first quantity of valid data and the second quantity of valid data failing to satisfy a threshold.
However, Saxena teaches wherein the controller is further configured to cause the apparatus to: write third data to a third data block of the memory system based at least in part on a third logical type of the third data (Paragraph 60, Fig. 3, video data [third data type] is transferred to the MLC S1 block [third data block] region);
write fourth data to the third data block based at least in part on a fourth logical type of the fourth data, the third logical type and the fourth logical type associated with storage to a second type of memory cell (Paragraph 60, Fig. 3, video data [third data type] and user data [fourth data type] are transferred to the MLC S1 block [third data block] in non-volatile memory 104 via controller 102).
Ryu, Igahara, Balasubramaniam, and Saxena are analogous art because they are in the same field of endeavor, that being the writing of data to different regions of a memory device according to data type. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the apparatus of Ryu in view of Igahara, further in view of Balasubramaniam to further include the fourth data type and data block according to the teachings of Saxena. The motivation for doing so would have been to increase write performance and compacting of data (Saxena, Paragraph 28).
Ryu in view of Igahara, further in view of Balasubramaniam and Saxena does not explicitly teach to determine to perform a second media management operation to transfer valid data from the third data block; and perform the second media management operation to transfer, to a fourth data block of the memory system, a portion of the third data comprising a first quantity of valid data and a portion of the fourth data comprising a second quantity of valid data based at least in part on the first quantity of valid data and the second quantity of valid data failing to satisfy a threshold.
However, Chang teaches to determine to perform a second media management operation to transfer valid data from the third data block (Paragraph 48; Fig. 5, step 560, valid data from the logical block [third data block] is combined and copied to the free physical block set);
and perform the second media management operation to transfer, to a fourth data block of the memory system, a portion of the third data comprising a first quantity of valid data and a portion of the fourth data comprising a second quantity of valid data (Paragraph 48; Fig. 5, step 560, valid data from two physical block sets [first and second quantities] corresponding to the logical block [third data block] is combined and copied to a free physical block set [fourth data block])
based at least in part on the first quantity of valid data and the second quantity of valid data failing to satisfy a threshold (Paragraphs 40, 47; Fig. 2, step 250, garbage collection predetermined criterion may be based on the valid data quantities of first and second physical block sets).
Ryu, Igahara, Balasubramaniam, Saxena, and Chang are analogous art because they are in the same field of endeavor, that being data block storage management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the apparatus of Ryu in view of Igahara, further in view of Balasubramaniam and Saxena to further include transferring valid data to a fourth storage block according to the teachings of Chang. The motivation for doing so would have been to improve the space efficiency of the storage system. (Chang, Paragraph 48).
Claim 11 is rejected under 35 U.S.C 103 as being unpatentable over Ryu in view of Igahara, further in view of Balasubramaniam as applied to claim 1 above, and further in view of Thomas et al. (US 20170285948 A1), hereinafter Thomas.
Regarding claim 11, Ryu in view of Igahara, further in view of Balasubramaniam teaches the apparatus of claim 1, but does not explicitly teach wherein the controller is further configured to cause the apparatus to: determine to perform a second media management operation to transfer a portion of the first data comprising valid data from the second data block; and perform the second media management operation to transfer the portion of the first data from the second data block to the first data block based at least in part on a quantity of the valid data failing to satisfy a threshold.
However, Thomas teaches wherein the controller is further configured to cause the apparatus to: determine to perform a second media management operation to transfer a portion of the first data comprising valid data from the second data block; and perform the second media management operation to transfer the portion of the first data from the second data block to the first data block (Paragraph 61; Fig. 8, steps 804 and 806, controller 102 relocates the valid data from a selected source block to an open relocation block)
based at least in part on a quantity of the valid data failing to satisfy a threshold (Paragraph 67, Fig. 9, source block is selected based on the percentage of valid data compared to a variable threshold 910).
Ryu, Igahara, Balasubramaniam, and Thomas are analogous art because they are in the same field of endeavor, that being data type storage management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the apparatus of Ryu to further include transferring valid data to the first data block according to the teachings of Thomas. The motivation for doing so would have been to free up additional space for more data. (Thomas, Paragraph 45).
Claim 22 is rejected under 35 U.S.C 103 as being unpatentable over Ryu in view of Igahara, further in view of Balasubramaniam as applied to claim 1 above, and further in view of Dronamraju et al. (US 20180260154 A1), hereinafter Dronamraju.
Regarding claim 22, Ryu in view of Igahara, further in view of Balasubramaniam teaches the apparatus of claim 1, but does not explicitly teach wherein the first logical type is associated with write booster data, user data, redundant array of independent not-and (NAND) parity data, firmware data, or data associated with operation of the memory system, and the second logical type is associated with the write booster data, the user data, the redundant array of independent NAND parity data, the firmware data, or the data associated with operation of the memory system, the second logical type being different than the first logical type.
However, Dronamraju teaches wherein the first logical type is associated with write booster data, user data (Paragraph 58; Fig. 4, storing user data within a third allocation area 424), redundant array of independent not-and (NAND) parity data, firmware data, or data associated with operation of the memory system, and
the second logical type is associated with the write booster data, the user data, the redundant array of independent NAND parity data, the firmware data, or the data associated with operation of the memory system, the second logical type being different than the first logical type (Paragraph 58; Fig. 4, storing metadata such as volume size information [data associated with operation of the memory system] within a fourth allocation area).
Ryu, Igahara, Balasubramaniam, and Dronamraju are analogous art because they are in the same field of endeavor, that being data type storage management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the apparatus of Ryu in view of Igahara, further in view of Balasubramaniam to further include the user data and metadata types according to Dronamraju. The motivation for doing so would have been to be able to reduce fragmentation and write amplification by separating storage of user data and metadata (Dronamraju, Paragraph 14).
Response to Arguments
Applicant’s arguments (see pages 9-11 of the remarks) filed 1/5/25, with respect to the rejections of claims 1, 14, and 20 under 35 U.S.C 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Ryu, Igahara, and Balasubramaniam.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jason Pinga whose telephone number is (571) 272-2620. The examiner can normally be reached on M-F 8:30am-6pm ET.
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supervisor, Arpan Savla, can be reached on (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/J.M.P./Examiner, Art Unit 2137
/TRACY A WARREN/Primary Examiner, Art Unit 2137