DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/24/25 has been entered.
1. REJECTIONS BASED ON PRIOR ART
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC ' 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-6, 11-13, and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ramesh (US 10789094 B1) in view of Oyaizu (US 20040255076).
With regards to claim 1, Ramesh teaches comprising:
receiving, by a persistent storage device comprising non-volatile memory and a buffer storing data, a first memory-addressed instruction; and (Col. 2 Lines 23-27: As used herein, a volatile memory resource may be referred to in the alternative as a “non-persistent memory device” while a non-volatile memory resource may be referred to in the alternative as a “persistent memory device.”;
Col. 5 Lines 38- 58: The hierarchical memory apparatus 104 can, as illustrated in FIG. 1, include a memory resource 102, which can include a read buffer 103, a write buffer 105, and/or an input/output (I/O) device access component 107. In some embodiments, the memory resource 102 can be a random-access memory resource, such as a block RAM, which can allow for data to be stored within the hierarchical memory apparatus 104 in embodiments in which the hierarchical memory apparatus 104 is a FPGA. … The memory resource 102 is internal to the hierarchical memory apparatus 104 and is generally smaller than memory that is external to the hierarchical memory apparatus 104, such as persistent and/or non-persistent memory resources that can be external to the hierarchical memory apparatus 104.;
Col. 9 line 67 - Col. 10 Line 2: However, in some embodiments, the persistent memory device can be included in (e.g., internal to) the hierarchical memory apparatus 104.;
Hierarchical memory apparatus is interpreted to be a persistent storage device, the non-volatile memory is interpreted to be the persistent memory device, and the buffer is interpreted to be the memory resource.)
copying a portion of the data in the buffer of the persistent storage device to the non-volatile memory, based on receiving the first memory-addressed instruction, (Col. 6 Lines 6-13: The write buffer 105 can include a portion of the memory resource 102 that is reserved for storing data that is awaiting transmission to a location external to the hierarchical memory apparatus 104. For instance, the write buffer 105 can store data that is to be transmitted to memory (e.g., persistent memory) that is external to the hierarchical memory apparatus 104 in association with a program (e.g., write) operation being performed on the external memory.;
Col. 6 Line 57 - Col. 7 Line 2: In addition, the memory access MUX 109 can redirect requests (e.g., read requests, write requests) received by the hierarchical memory apparatus 104. In some embodiments, the requests can be received by the hierarchical memory apparatus 104 from a hypervisor (e.g., the hypervisor 412 illustrated in FIG. 4, herein), a bare metal server, or host computing device communicatively coupled to the hierarchical memory apparatus 104. Such requests can be redirected by the memory access MUX 109 from the read buffer 103, the write buffer 105, and/or the I/O access component 107 to an address register (e.g., the address register 106-2, which can be a BAR2 region of the hierarchical memory controller 113, as described below).;
Transmitted data from the buffer to the memory (e.g. persistent memory) is interpreted to be "copying a portion of the data in the buffer of the persistent storage device to the non-volatile memory". The requests the read buffer, write buffer, and I/O access component are sent are interpreted as potential first memory-addressed instructions.)
wherein the portion of the data in the buffer to be copied is based on a start address in a start address register of the persistent storage device and an end address in an end address register of the persistent storage device. ((Col. 6 Lines 1-5 and 13-18, FIG. 1) Because the write/read buffer is associated with the data in the address register, its size would need to be large enough to contain said data. (Col. 12 Ln. 60-66) The address registers can store memory addresses used by the hierarchal memory apparatus, which is interpreted to include the memory resource that stores the read and write buffers. Therefore, it can be interpreted that the "start address in a start address register of the persistent storage device" is equal to the beginning address in one of the address registers 106-1 to 106-N in the hierarchical memory apparatus and the "end address in an end address register of the persistent storage device" is equal to the last address in one of the address registers 106-1 to 106-N in the hierarchical memory apparatus. (Column 9 Lines 42-45) The size of the register can be as big as the persistent memory device. Because the buffers can buffer data from registers and the registers can be based on the addresses and the size of the persistent memory device, the buffers are interpreted as the claimed portion of the data in the buffer to be copied based on the start address and the end address of the persistent storage device.)
However, the Ramesh reference does not explicitly teach wherein the start address and the end address identify locations in the buffer.
The Oyaizu reference teaches it is conventional to have wherein the start address and the end address identify locations in the buffer. (paragraph 19, where the second control block may sequentially read data for transferring to the flash memory from the buffer, in an order from start address to end address of the buffer, when data stored in the buffer is written to the flash memory)
It would have been obvious to a person of ordinary skill in the art before the claimed invention was effectively filed to modify the Ramesh reference to have wherein the start address and the end address identify locations in the buffer, as taught by the Oyaizu reference.
The suggestion/motivation for doing so would have been to have sequentially read data transferred to the flash memory from the buffer, in an order from start
address to end address of the buffer, when data stored in the buffer is written to the flash memory. (Oyaizu, paragraph 19)
Therefore it would have been obvious to combine the Ramesh and Oyaizu references for the benefits shown above to obtain the invention as specified in the claim.
With regards to claim 3, the combination of Ramesh in view of Oyaizu teaches the method of claim 1 as shown above; and Ramesh further teaches wherein:
the portion of the buffer has a first size, and the first size is based on a value in a first register of the persistent storage device. (Col. 6 Lines 13-18: In some embodiments, the write buffer 105 can be around 4 Kilobytes (KB) in size, although embodiments are not limited to this particular size. The write buffer 105 can buffer data that is registered in one of the address registers 106-1 to 106-N.;
Because the write/read buffer can buffer the data that is registered in the address register, its size would need to be large enough to contain said data.)
With regards to claim 4, the combination of Ramesh in view of Oyaizu teaches the method of claim 1 as shown above; and Ramesh further teaches comprising:
determining that a first portion of the buffer stores host data; and (Col. 6 Lines 6-13: The write buffer 105 can include a portion of the memory resource 102 that is reserved for storing data that is awaiting transmission to a location external to the hierarchical memory apparatus 104. For instance, the write buffer 105 can store data that is to be transmitted to memory (e.g., persistent memory) that is external to the hierarchical memory apparatus 104 in association with a program (e.g., write) operation being performed on the external memory.;
The first portion is interpreted to be the write buffer and data that is stored awaiting transmission is interpreted to come from a host.)
determining that a second portion of the buffer stores data generated by the persistent storage device. (Col. 5 Line 59 - Col. 6 Line 1: The read buffer 103 can include a portion of the memory resource 102 that is reserved for storing data that has been received by the hierarchical memory apparatus 104 but has not been processed by the hierarchical memory apparatus 104. For instance, the read buffer 103 can store data that has been received by the hierarchical memory apparatus 104 in association with (e.g., during and/or as a part of) a sense (e.g., read) operation being performed on memory (e.g., persistent memory) that is external to the hierarchical memory apparatus 104.;
The second portion is interpreted to be the read buffer and data being stored by the hierarchical memory apparatus with a sense operation being performed on memory is interpreted to be data generated by the persistent storage device.)
With regards to claim 5, the combination of Ramesh in view of Oyaizu teaches the method of claim 1 as shown above; and Ramesh further teaches comprising:
determining that a first portion of the buffer stores host data; and (Col. 6 Lines 6-13: The write buffer 105 can include a portion of the memory resource 102 that is reserved for storing data that is awaiting transmission to a location external to the hierarchical memory apparatus 104. For instance, the write buffer 105 can store data that is to be transmitted to memory (e.g., persistent memory) that is external to the hierarchical memory apparatus 104 in association with a program (e.g., write) operation being performed on the external memory.;
The first portion is interpreted to be the write buffer and data that is stored awaiting transmission is interpreted to come from a host.)
determining that a second portion of the buffer stores data generated by the persistent storage device, (Col. 5 Line 59 - Col. 6 Line 1: The read buffer 103 can include a portion of the memory resource 102 that is reserved for storing data that has been received by the hierarchical memory apparatus 104 but has not been processed by the hierarchical memory apparatus 104. For instance, the read buffer 103 can store data that has been received by the hierarchical memory apparatus 104 in association with (e.g., during and/or as a part of) a sense (e.g., read) operation being performed on memory (e.g., persistent memory) that is external to the hierarchical memory apparatus 104.;
The second portion is interpreted to be the read buffer and data being stored by the hierarchical memory apparatus with a sense operation being performed on memory is interpreted to be data generated by the persistent storage device.)
wherein: the copying of a portion of the data in the buffer of the persistent storage device to the non-volatile memory comprises copying a part of the first portion of the buffer. (Col. 6 Lines 6-13: The write buffer 105 can include a portion of the memory resource 102 that is reserved for storing data that is awaiting transmission to a location external to the hierarchical memory apparatus 104. For instance, the write buffer 105 can store data that is to be transmitted to memory (e.g., persistent memory) that is external to the hierarchical memory apparatus 104 in association with a program (e.g., write) operation being performed on the external memory.;
Transmitted data from the buffer to the memory (e.g. persistent memory) is interpreted to be copying a portion of the data in the buffer of the persistent storage device to the non-volatile memory. The first portion is interpreted to be the write buffer.)
With regards to claim 6, the combination of Ramesh in view of Oyaizu teaches the method of claim 1 as shown above; and Ramesh further teaches comprising:
determining that a first portion of the buffer stores host data; (Col. 6 Lines 6-13: The write buffer 105 can include a portion of the memory resource 102 that is reserved for storing data that is awaiting transmission to a location external to the hierarchical memory apparatus 104. For instance, the write buffer 105 can store data that is to be transmitted to memory (e.g., persistent memory) that is external to the hierarchical memory apparatus 104 in association with a program (e.g., write) operation being performed on the external memory.;
The first portion is interpreted to be the write buffer and data that is stored awaiting transmission is interpreted to come from a host.)
reading, by the persistent storage device, first data from the non-volatile memory; (Col. 5 Line 59 - Col. 6 Line 1: The read buffer 103 can include a portion of the memory resource 102 that is reserved for storing data that has been received by the hierarchical memory apparatus 104 but has not been processed by the hierarchical memory apparatus 104. For instance, the read buffer 103 can store data that has been received by the hierarchical memory apparatus 104 in association with (e.g., during and/or as a part of) a sense (e.g., read) operation being performed on memory (e.g., persistent memory) that is external to the hierarchical memory apparatus 104.;
The hierarchical memory apparatus (interpreted as the persistent storage device) performs a read operation on the memory, e.g. persistent memory (interpreted to be non-volatile memory). The received data is interpreted to be first data.)
processing the first data, by the persistent storage device, to form first processed data; (Col. 5 Line 59 - Col. 6 Line 1: The read buffer 103 can include a portion of the memory resource 102 that is reserved for storing data that has been received by the hierarchical memory apparatus 104 but has not been processed by the hierarchical memory apparatus 104. For instance, the read buffer 103 can store data that has been received by the hierarchical memory apparatus 104 in association with (e.g., during and/or as a part of) a sense (e.g., read) operation being performed on memory (e.g., persistent memory) that is external to the hierarchical memory apparatus 104.;
The stored data is interpreted to be processed by the hierarchical memory apparatus in association with the memory.)
storing, by the persistent storage device, the first processed data in a second portion of the buffer; and (Col. 5 Line 59 - Col. 6 Line 1: The read buffer 103 can include a portion of the memory resource 102 that is reserved for storing data that has been received by the hierarchical memory apparatus 104 but has not been processed by the hierarchical memory apparatus 104. For instance, the read buffer 103 can store data that has been received by the hierarchical memory apparatus 104 in association with (e.g., during and/or as a part of) a sense (e.g., read) operation being performed on memory (e.g., persistent memory) that is external to the hierarchical memory apparatus 104.;
The second portion is interpreted to be the read buffer.)
determining that the second portion of the buffer stores data generated by the persistent storage device, (Col. 5 Line 59 - Col. 6 Line 1: The read buffer 103 can include a portion of the memory resource 102 that is reserved for storing data that has been received by the hierarchical memory apparatus 104 but has not been processed by the hierarchical memory apparatus 104. For instance, the read buffer 103 can store data that has been received by the hierarchical memory apparatus 104 in association with (e.g., during and/or as a part of) a sense (e.g., read) operation being performed on memory (e.g., persistent memory) that is external to the hierarchical memory apparatus 104.;
The second portion is interpreted to be the read buffer and data being stored by the hierarchical memory apparatus with a sense operation being performed on memory is interpreted to be data generated by the persistent storage device.)
wherein: the copying of a portion of the data in the buffer of the persistent storage device to the non-volatile memory comprises copying a part of the first portion of the buffer. ((Col. 6 Lines 6-13) The write buffer 105 can include a portion of the memory resource 102 that is reserved for storing data that is awaiting transmission to a location external to the hierarchical memory apparatus 104. For instance, the write buffer 105 can store data that is to be transmitted to memory (e.g., persistent memory) that is external to the hierarchical memory apparatus 104 in association with a program (e.g., write) operation being performed on the external memory.;
Transmitting data from the buffer to the memory (e.g. persistent memory) is interpreted to be copying a portion of the data in the buffer of the persistent storage device to the non-volatile memory. The first portion is interpreted to be the write buffer.)
Claim 11 is essentially the same as claim 1 except that the claim is directed to a system instead of the method in claim 1. The differences between claim 11 and claim 1 are “a persistent storage device comprising: a non-volatile memory; a buffer; and a processing circuit” configured to perform the steps noted above. This is shown in fig. 3 and corresponding text of Ramesh and fig. 1 and corresponding text of Oyaizu; and further discussed by the citations noted above. Claim 11 is therefore rejected under the same rationale as applied to claim 1 above.
Claim 12 is essentially the same as claim 5 except that the claim is directed to a system instead of the method in claim 1. Claim 12 is therefore rejected under the same rationale as applied to claim 5 above.
Claim 13 is essentially the same as claim 6 except that the claim is directed to a system instead of the method in claim 1. Claim 13 is therefore rejected under the same rationale as applied to claim 6 above.
Claim 18 is essentially the same as claim 1 except that the claim is directed to a system instead of the method in claim 1. The differences between claim 11 and claim 1 are “a persistent storage device comprising: a non-volatile memory; a buffer; a processing circuit; and memory, the memory storing instructions that, when executed by the processing circuit, cause the processing circuit to perform a method” to perform the steps noted above. This is shown in fig. 3 and corresponding text of Ramesh and fig. 1 and corresponding text of Oyaizu; and further discussed by the citations noted above. Claim 18 is therefore rejected under the same rationale as applied to claim 1 above.
Claim 19 is essentially the same as claim 5 except that the claim is directed to a persistent storage device instead of the method in claim 1. Claim 19 is therefore rejected under the same rationale as applied to claim 5 above.
Claim 20 is essentially the same as claim 6 except that the claim is directed to a persistent storage device instead of the method in claim 1. Claim 20 is therefore rejected under the same rationale as applied to claim 6 above.
Claim(s) 7-10, 14-16, and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ramesh (US 10789094 B1) in view of view of Oyaizu (US 20040255076) as shown in the rejections above, and further view of Tan (US 20230107227 A1).
With regards to claim 7, the combination of Ramesh in view of Oyaizu teaches the method of claim 1 as shown above; and Ramesh further teaches comprising:
receiving, by the persistent storage device, a second memory-addressed instruction; and sending, by the persistent storage device, … , based on the receiving, by the persistent storage device, of the second memory-addressed instruction. (Col. 7 Lines 29-34: As a non-limiting example, if the hierarchical memory apparatus 104 receives a read request from the I/O device, the memory access MUX 109 can facilitate retrieval of data from a persistent memory device via the hypervisor by selecting the appropriate messages to send from the hierarchical memory apparatus 104.)
The combination of Ramesh and Oyaizu does not teach:
… an indication of a quantity of data stored in the buffer …
However, Tan does teach:
… an indication of a quantity of data stored in the buffer … (¶0052 If the buffer 225 has sufficient space to store the write data, the memory system controller 215 may cause the interface 220 to transmit an indication of availability to the host system 205 (e.g., a “ready to transfer” indication), e.g., according to a protocol (e.g., a UFS protocol or an eMMC protocol).;
¶0072 The data flow… Accordingly, data may be added to the first buffer 315 in chunks of a size equal to the multi-plane page size, while data may be added to the second buffer 320 in chunks of sizes less than the multi-plane page size. If the data stored in the second buffer 320 reaches the threshold size, the memory system may perform a copy operation 325 to copy data of the threshold size (e.g., including multiple chunks of data corresponding to metadata, small data files, or both that together equal the multi-plane page size) from the second buffer 320 to the first buffer 315.;
The buffer is made up of chunks of a size equal to or less than the threshold size. The sufficient space left to store write data is interpreted to be a quantity of data stored in the buffer and the indication of availability to the host system is seen as an indication.)
It would have been obvious to one having ordinary skill in the computer art before the effective filing date of the claimed invention to modify the method disclosed by the combination of Ramesh and Oyaizu to indicate a quantity of data stored in the buffer using the teaching of Tam. The modification would be obvious because one of ordinary skill in the art would be motivated to determine the amount of data in a buffer and compare this number to a threshold, to start the copying of data from the buffer to the non-volatile memory.
With regards to claim 8, the combination of Ramesh in view of Oyaizu teaches the method of claim 1 as shown above; and Ramesh further teaches comprising:
determining that a first portion of the buffer stores host data; (Col. 6 Lines 6-13: The write buffer 105 can include a portion of the memory resource 102 that is reserved for storing data that is awaiting transmission to a location external to the hierarchical memory apparatus 104. For instance, the write buffer 105 can store data that is to be transmitted to memory (e.g., persistent memory) that is external to the hierarchical memory apparatus 104 in association with a program (e.g., write) operation being performed on the external memory.;
The first portion is interpreted to be the write buffer and data that is stored awaiting transmission is interpreted to come from a host.)
determining … ; and (Col. 6 Lines 13-18: In some embodiments, the write buffer 105 can be around 4 Kilobytes (KB) in size, although embodiments are not limited to this particular size. The write buffer 105 can buffer data that is registered in one of the address registers 106-1 to 106-N.)
copying a part of the first portion of the buffer to the non-volatile memory, based on determining … . (Col. 6 Lines 6-13: The write buffer 105 can include a portion of the memory resource 102 that is reserved for storing data that is awaiting transmission to a location external to the hierarchical memory apparatus 104. For instance, the write buffer 105 can store data that is to be transmitted to memory (e.g., persistent memory) that is external to the hierarchical memory apparatus 104 in association with a program (e.g., write) operation being performed on the external memory.;
Transmitted data from the buffer to the memory (e.g. persistent memory) is interpreted to be copying a portion of the data in the buffer of the persistent storage device to the non-volatile memory. The first portion is interpreted to be the write buffer.)
The combination of Ramesh and Oyaizu does not teach:
… that a size of the first portion exceeds a threshold …
However, Tan does teach:
… that a size of the first portion exceeds a threshold … (¶0074 In some examples, ... The first buffer 405 may be configured to trigger a buffer flush operation upon satisfying a flush condition. The flush condition may, in some examples, be the first buffer 405 storing a total amount of data equal to or greater than a flush threshold (e.g., the size of the first buffer 405). The first buffer 405, upon triggering the buffer flush operation, may be configured to write data to one or more memory devices.;
The size of the first portion is interpreted to the total amount of data stored in the first buffer. The threshold is interpreted to be the flush threshold. The flush operation that may be configured to write data to one or memory is interpreted to be a type of copying data. One of more memory devices are interpreted to contain non-volatile memory.)
It would have been obvious to one having ordinary skill in the computer art before the effective filing date of the claimed invention to modify the method disclosed by the combination of Ramesh and Oyaizu to have the copying of data from the first portion of the buffer to the non-volatile memory be based on the size of the first portion exceeding a threshold using the teaching of Tan. The modification would be obvious because one of ordinary skill in the art would be motivated to improve read performance and avoid die misalignment. (Tan - Abstract: Methods, systems, and devices for two-stage buffer operations supporting write commands are described. If data is written to a memory device starting at a multi-plane page offset other than zero, the read performance for the data may decrease significantly due to die misalignment.;
¶0012 If the data stored in the first buffer satisfies a flush threshold, the memory system may write the data from the first buffer to the memory device. By setting the threshold size equal to the multi-plane page size of the memory device, the memory system may ensure that data written to the memory device from the first buffer starts at a multi-plane page offset of zero, avoiding die misalignment and supporting improved read performance (e.g., compared to die misaligned data).)
With regards to claim 9, the combination of Ramesh in view of Oyaizu teaches the method of claim 1 as shown above; and Ramesh further teaches comprising:
determining that a first portion of the buffer stores host data; (Col. 6 Lines 6-13: The write buffer 105 can include a portion of the memory resource 102 that is reserved for storing data that is awaiting transmission to a location external to the hierarchical memory apparatus 104. For instance, the write buffer 105 can store data that is to be transmitted to memory (e.g., persistent memory) that is external to the hierarchical memory apparatus 104 in association with a program (e.g., write) operation being performed on the external memory.;
The first portion is interpreted to be the write buffer and data that is stored awaiting transmission is interpreted to come from a host.)
determining …; and (Col. 6 Lines 13-18: In some embodiments, the write buffer 105 can be around 4 Kilobytes (KB) in size, although embodiments are not limited to this particular size. The write buffer 105 can buffer data that is registered in one of the address registers 106-1 to 106-N.)
copying a part of the first portion of the buffer to the non-volatile memory, based on determining …, (Col. 6 Lines 6-13: The write buffer 105 can include a portion of the memory resource 102 that is reserved for storing data that is awaiting transmission to a location external to the hierarchical memory apparatus 104. For instance, the write buffer 105 can store data that is to be transmitted to memory (e.g., persistent memory) that is external to the hierarchical memory apparatus 104 in association with a program (e.g., write) operation being performed on the external memory.;
Transmitted data from the buffer to the memory (e.g. persistent memory) is interpreted to be copying a portion of the data in the buffer of the persistent storage device to the non-volatile memory. The first portion is interpreted to be the write buffer.)
wherein a size of the part of the first portion is greater than or equal to the first amount. (The size of the part of the first portion is interpreted as the size of the first portion, therefore the first amount is equal to the size of the first portion.)
The combination of Ramesh and Oyaizu does not teach:
… that a size of the first portion exceeds a threshold by a first amount … a size of the first portion exceeds the threshold by the first amount …
However, Tan does teach:
… that a size of the first portion exceeds a threshold by a first amount … a size of the first portion exceeds the threshold by the first amount … (¶0074 In some examples, ... The first buffer 405 may be configured to trigger a buffer flush operation upon satisfying a flush condition. The flush condition may, in some examples, be the first buffer 405 storing a total amount of data equal to or greater than a flush threshold (e.g., the size of the first buffer 405). The first buffer 405, upon triggering the buffer flush operation, may be configured to write data to one or more memory devices.;
The size of the first portion is interpreted to the total amount of data stored in the first buffer. The threshold is interpreted to be the flush threshold. The first amount is interpreted to be the size of the first buffer. The flush operation that may be configured to write data to one or memory is interpreted to be a type of copying data. One of more memory devices are interpreted to contain non-volatile memory.)
It would have been obvious to one having ordinary skill in the computer art before the effective filing date of the claimed invention to modify the method disclosed by the combination of Ramesh and Oyaizu to have the copying of data from the first portion of the buffer to the non-volatile memory be based on the size of the first portion exceeding a threshold by a first amount using the teaching of Tan. The modification would be obvious because one of ordinary skill in the art would be motivated to improve read performance and avoid die misalignment. (Tan - Abstract: Methods, systems, and devices for two-stage buffer operations supporting write commands are described. If data is written to a memory device starting at a multi-plane page offset other than zero, the read performance for the data may decrease significantly due to die misalignment.;
¶0012 If the data stored in the first buffer satisfies a flush threshold, the memory system may write the data from the first buffer to the memory device. By setting the threshold size equal to the multi-plane page size of the memory device, the memory system may ensure that data written to the memory device from the first buffer starts at a multi-plane page offset of zero, avoiding die misalignment and supporting improved read performance (e.g., compared to die misaligned data).)
With regards to claim 10, the combination of Ramesh in view of Oyaizu teaches the method of claim 1 as shown above; and Ramesh further teaches comprising:
receiving, by the persistent storage device, a second memory-addressed instruction; and sending, by the persistent storage device, … , based on the receiving, by the persistent storage device, of the second memory-addressed instruction. (Col. 7 Lines 29-34: As a non-limiting example, if the hierarchical memory apparatus 104 receives a read request from the I/O device, the memory access MUX 109 can facilitate retrieval of data from a persistent memory device via the hypervisor by selecting the appropriate messages to send from the hierarchical memory apparatus 104.)
The combination of Ramesh and Oyaizu does not teach:
… an indication of a quantity of host data stored in the buffer …
However, Tan does teach:
… an indication of a quantity of host data stored in the buffer … (¶0052 If the buffer 225 has sufficient space to store the write data, the memory system controller 215 may cause the interface 220 to transmit an indication of availability to the host system 205 (e.g., a “ready to transfer” indication), e.g., according to a protocol (e.g., a UFS protocol or an eMMC protocol). As the interface 220 subsequently receives from the host system 205 the data associated with the write command, the interface 220 may transfer the data to the buffer 225 for temporary storage using the data path 250.;
¶0074 In some examples … The first buffer 405 may be configured to write chunks of data of the threshold size 425 to each multi-plane page of the memory device(s) to avoid die misalignment, where the multi-plane page size may be equal to the threshold size 425.;
The sufficient space to store write data is interpreted to be a quantity of host data stored in the buffer and the indication of availability to the host system is seen as an indication.)
It would have been obvious to one having ordinary skill in the computer art before the effective filing date of the claimed invention to modify the method disclosed by the combination of Ramesh and Oyaizu to indicate a quantity of host data stored in the buffer using the teaching of Tam. The modification would be obvious because one of ordinary skill in the art would be motivated to determine the amount of host data in a buffer and compare this number to a threshold, to start the copying of data from the buffer to the non-volatile memory.
Claim 14 is essentially the same as claim 7 except that the claim is directed to a system instead of the method in claim 1. Claim 14 is therefore rejected under the same rationale as applied to claim 7 above.
Claim 15 is essentially the same as claim 8 except that the claim is directed to a system instead of the method in claim 1. Claim 15 is therefore rejected under the same rationale as applied to claim 8 above.
Claim 16 is essentially the same as claim 9 except that the claim is directed to a system instead of the method in claim 1. Claim 16 is therefore rejected under the same rationale as applied to claim 9 above.
Claim 21 is essentially the same as claim 7 except that the claim is directed to a persistent storage device instead of the method in claim 1. Claim 21 is therefore rejected under the same rationale as applied to claim 7 above.
2. ARGUMENTS CONCERNING PRIOR ART REJECTIONS
Rejections - USC 102/103
Applicant's arguments (see pages 9-10 of the remarks) and amendments with respect to claims 1, 3-10, 11-16 and 18-21 have been considered, and are persuasive.
Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Oyaizu reference to teach the newly amended claim language as shown in the rejections above.
3. RELEVANT ART CITED BY THE EXAMINER
The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant's art and those arts considered reasonably pertinent to applicant's disclosure. See MPEP 707.05(c).
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. These references include:
Kannan (US 20180024830), which teaches a method for non-disruptive upgrade of a storage system is provided. The method includes disabling, by an interlock, access by one or more processors of the storage system to the first memory, responsive to a request. The method includes persisting configuration information in the first memory to the solid-state memory, with the access to the first memory disabled by the interlock, wherein the persisting, the first memory and the solid-state memory are supported by an energy reserve. The method includes enabling, by the interlock, access by the one or more processors to the first memory, responsive to completing the persisting, and writing, by the one or more processors of the storage system, to the first memory, to perform the upgrade with further configuration information, with the access enabled by the interlock and wherein at least the persisting is accomplished without power cycling.
4. CLOSING COMMENTS
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRASITH THAMMAVONG whose telephone number is (571) 270-1040. The examiner can normally be reached Monday - Friday 12-8 PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla can be reached on (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PRASITH THAMMAVONG/
Primary Examiner, Art Unit 2137