DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note by the Examiner
For clarity, references to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and examiner explanations for 102 &/or 103 rejections are provided in parenthesis.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: 595 in Fig. 1. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to because line A-A' is not clearly shown in Figs. 1, 5, 13, 22, and 26, and lines A-A' and B-B' are not clearly shown in Fig. 3. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 17 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 13 (on which claim 17 depends upon) states a new limitation “wherein a bottom surface of the first spacer is in contact with an upper surface of the active pattern” and claim 17 states the limitation "a fourth spacer that is disposed below the first spacer," however, none of the drawings show these two limitations together. Because of this, claim 17 contains new matter.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 13-14 and 16-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13 recites the limitation "a first direction" in the 28th line of the claim. This is indefinite as there is already a first direction claimed earlier. For examination purposes, it will be assumed that both “first direction” are the same first direction. Due to their dependency on claim 13, claims 14-17 are also rejected.
Claim 14 recites the limitation "the conductive pattern" in the 6th line of the claim. There is insufficient antecedent basis for this limitation in the claim. For examination purposes, it will be assumed that Applicant meant to write "the conductive pattern structure".
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (Pub. No.: US 20220085026 A1), hereinafter as Kim’22.
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Image A: closeup of Kim’22 Fig. 2, showcasing portions.
With regards to claim 1, Kim’22 teaches a semiconductor device, comprising: an active pattern (see Kim’22 Fig. 2, an active pattern 105; Kim’22 [0019]) disposed on a substrate (see Kim’22 Fig. 2, substrate 100; Kim’22 [0016]); a gate structure (see Kim’22 Fig. 2, gate structure 160; Kim’22 [0017]) disposed on an upper portion of the active pattern (see Kim’22 Fig. 2); a bit line structure (see Kim’22 Fig. 2, bit line structure 325; Kim’22 [0017]) disposed on the active pattern (see Kim’22 Fig. 2), wherein the bit line structure includes a first conductive pattern (see Kim’22 Fig. 2, conductive structure 265; Kim’22 [0025]), a second conductive pattern (see Kim’22 Fig. 2, fourth conductive pattern 305; Kim’22 [0027]) and an insulation structure (see Kim’22 Fig. 2, first capping pattern 315; Kim’22 [0027]) stacked on each other in a vertical direction substantially perpendicular to an upper surface of the substrate (see Kim’22 Fig. 2); a lower spacer structure (see Kim’22 Fig. 2, air spacer 397, third upper spacer 405, and fourth lower spacer 365; Kim’22 [0031] & [0028]) disposed on a lower portion of a sidewall of the bit line structure (see Kim’22 Fig. 2); an upper spacer structure (see Kim’22 Fig. 2, first upper spacer 385 and fourth upper spacer 445; Kim’22 [0031]) disposed on the lower spacer structure (see Kim’22 Fig. 2), wherein the upper spacer structure is disposed on an upper portion of the sidewall of the bit line structure (see Kim’22 Fig. 2); a contact plug structure (see Kim’22 Fig. 2 and Kim’22 [0039]: “The contact plug structure may include a lower contact plug 425, an ohmic contact pattern 455, a barrier layer 460 and an upper contact plug 475 sequentially stacked the vertical direction.”) disposed on the active pattern (see Kim’22 Fig. 2), wherein the contact plug structure is spaced apart from the bit line structure (see Kim’22 Fig. 2); and a capacitor (see Kim’22 Fig. 2, capacitor 550; Kim’22 [0017]) disposed on the contact plug structure (see Kim’22 Fig. 2), wherein the lower spacer structure includes: a first spacer (see Kim’22 Fig. 2, air spacer 397; Kim’22 [0031]) partially covering a sidewall of the first conductive pattern (see Kim’22 Fig. 2), and including air (see Kim’22 [0035]: “The air spacer 397 may include, for example, air.”); and a second spacer (see Kim’22 Fig. 2, third upper spacer 405; Kim’22 [0031]) disposed on the first spacer (see Kim’22 Fig. 2), wherein the first conductive pattern includes: a lower portion (see Image A) contacting an upper surface of the active pattern (see Image A); a middle portion (see Image A) disposed on the lower portion (see Image A); and an upper portion (see Image A) disposed on the middle portion (see Image A), and wherein the first spacer covers a sidewall of the lower portion of the first conductive pattern (see Image A), and the second spacer covers a sidewall of the middle portion of the first conductive pattern (see Image A).
Claims 13 and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Rhee et al. (Pub. No.: US 20220149048 A1), hereinafter as Rhee.
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Image B: closeup of Rhee Fig. 2, showcasing portions and their widths.
With regards to claim 13, Rhee teaches a semiconductor device, comprising: an active pattern (see Rhee Fig. 2, active pattern 105; Rhee [0016]) disposed on a substrate (see Rhee Fig. 2, substrate 100; Rhee [0013]); an isolation pattern (see Rhee Fig. 2, isolation pattern 110; Rhee [0016]) disposed on the substrate (see Rhee Fig. 2), wherein the isolation pattern covers a sidewall of the active pattern (see Rhee Fig. 2); a gate structure (see Rhee Fig. 2, gate structure 160; Rhee [0014]) disposed on an upper portion of the active pattern and an upper portion of the isolation pattern (see Rhee Fig. 2), wherein the gate structure extends in a first direction (see Rhee Fig. 2, D1) substantially parallel to an upper surface of the substrate (see Rhee Fig. 2); an insulation pattern structure (see Rhee Fig. 2, insulation pattern structure 195; Rhee [0014]) disposed on the active pattern, the isolation pattern and the gate structure (see Rhee Fig. 2); a bit line structure (see Rhee Fig. 2, bit line structure 305; Rhee [0014]) extending on the active pattern (see Rhee Fig. 2) in a second direction (see Rhee Fig. 2, D2), wherein the second direction is substantially parallel to the upper surface of the substrate and crosses the first direction (see Rhee Fig. 2), and wherein the bit line structure includes a first conductive pattern structure (see Rhee Fig. 2, first conductive pattern 255; Rhee [0023]), a second conductive pattern (see Rhee Fig. 2, second conductive pattern 275; Rhee [0023]), and an insulation structure (see Rhee Fig. 2, first and second capping patterns 285 and 295; Rhee [0023]) sequentially stacked in a vertical direction substantially perpendicular to the upper surface of the substrate (see Rhee Fig. 2); a lower spacer structure (see Rhee Fig. 2, second lower spacer 235, first lower spacer 225, first upper spacer 315, and air spacer 325; Rhee [0026]&[0029]) disposed on a lower portion of a sidewall of the bit line structure (see Rhee Fig. 2), and including a first spacer (see Rhee Fig. 2, second lower spacer 235), a second spacer (see Rhee Fig. 2, first upper spacer 315) and a third spacer (see Rhee Fig. 2, air spacer 325); an upper spacer structure (see Rhee Fig. 2, third upper spacer 345 and fourth upper spacer 385; Rhee [0029]) disposed on the lower spacer structure (see Rhee Fig. 2) and on an upper portion of the sidewall of the bit line structure (see Rhee Fig. 2); a contact plug structure (see Rhee Fig. 2 and Rhee [0036]: “The contact plug structure may include the lower contact plug 365, an ohmic contact pattern 395, a barrier layer 400 and an upper contact plug 415 that are sequentially stacked in the vertical direction.”) disposed on the active pattern (see Rhee Fig. 2), and spaced apart from the bit line structure (see Rhee Fig. 2); and a capacitor (see Rhee Fig. 2, capacitor 490; Rhee [0014]) disposed on the contact plug structure (see Rhee Fig. 2), wherein the first conductive pattern structure includes a lower portion (see Image B), a middle portion (see Image B) and an upper portion (see Image B) sequentially stacked on each other in the vertical direction (see Image B), wherein a first width (see Image B), in the first direction, of the lower portion of the first conductive pattern structure is greater than a second width (see Image B), in the first direction, of the middle portion of the first conductive pattern structure (see Image B), and wherein the first spacer is disposed between the contact plug and the bit line structure (see Rhee Fig. 2) in the first direction substantially parallel to the upper surface of the substrate (see Rhee Fig. 2), and wherein a bottom surface of the first spacer is in contact with an upper surface of the active pattern (see Rhee Fig. 2).
With regards to claim 14, Rhee teaches the semiconductor device of claim 13, wherein the upper spacer structure (see Rhee Fig. 2, third upper spacer 345 and fourth upper spacer 385) is disposed on a sidewall of the upper portion (see Image B) of the first conductive pattern structure (see Rhee Fig. 2, first conductive pattern 255), and wherein a third width (see Image B), in the first direction (see Rhee Fig. 2, D1), of the upper portion (see Image B) of the first conductive pattern structure is substantially the same as the second width (see Image B), in the first direction, of the middle portion (see Image B) of the first conductive pattern structure (see Rhee Fig. 2, first conductive pattern 255).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 3, 7-9, and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Ikeda (Patent. No.: US 11121135 B1), in view of Kim et al. (Pub. No. US 20200402981 A1), hereinafter as Kim’20.
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Image C: closeup of Ikeda Fig. 5L, showcasing coplanarity and upper, middle, and lower portions.
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Image D: closeup of Ikeda Fig. 5L, showcasing first and second widths.
With regards to claim 1, Ikeda teaches a semiconductor device, comprising: an active pattern (see Ikeda Fig. 5L, active region 52; Ikeda col. 4, ln. 66) disposed on a substrate (see Ikeda Fig. 5A, substrate 50; Ikeda col. 4, ln. 65); a bit line structure (see Ikeda Fig. 5B, bit line stack 168/168′; Ikeda col. 5, ln. 18) disposed on the active pattern (see Ikeda Fig. 5L), wherein the bit line structure includes a first conductive pattern (see Ikeda Fig. 5B, bit line contact structure 154; Ikeda col. 5, ln. 9), a second conductive pattern (see Ikeda Fig. 5B, metal layer 156; Ikeda col. 5, ln. 12) and an insulation structure (see Ikeda Fig. 5B, dielectric layer 158; Ikeda col. 5, ln. 13) stacked on each other in a vertical direction substantially perpendicular to an upper surface of the substrate (see Ikeda Fig. 5B); a lower spacer structure (see Ikeda Fig. 5L, insulating stack layer 370 and nitride layer 179; Ikeda col. 6, ln. 30 and Ikeda col. 5, ln. 40) disposed on a lower portion of a sidewall of the bit line structure (see Ikeda Fig. 5L); an upper spacer structure (see Ikeda Fig. 5L, dielectric layer 174, dielectric layer 176, and dielectric layer 162; Ikeda col. 5, ln. 51, Ikeda col. 5, ln. 55, and Ikeda col. 5, ln. 13) disposed on the lower spacer structure (see Ikeda Fig. 5L), wherein the upper spacer structure is disposed on an upper portion of the sidewall of the bit line structure (see Ikeda Fig. 5L); a contact plug structure (see Ikeda Fig. 5L, capacitor contact structure 180; Ikeda col. 5, ln. 64) disposed on the active pattern (see Ikeda Fig. 5L), wherein the contact plug structure is spaced apart from the bit line structure (see Ikeda Fig. 5L), wherein the lower spacer structure includes: a first spacer (see Ikeda Fig. 5L, dielectric spacer 170; Ikeda col. 5, ln. 33) partially covering a sidewall of the first conductive pattern (see Ikeda Fig. 5L), and including air (see Ikeda col. 4, ln. 52-58: “The dielectric spacer 170 may be the oxide or air gap.” Also note Ikeda col. 4, ln. 59-64: “To fabricate the structure in FIG. 4, a fabrication process flow is further provided. FIG. 5A to FIG. 5L are drawings, schematically illustrating a process flow of a method to fabricate the memory cell as viewed by cross-section structure cutting at the line I-I in FIG. 2, according to an embodiment of the invention.”); and a second spacer (see Ikeda Fig. 5L, nitride liner layer 172; Ikeda col. 5, ln. 35) disposed on the first spacer (see Ikeda Fig. 5L), wherein the first conductive pattern includes: a lower portion (see Image C) contacting an upper surface of the active pattern (see Image C); a middle portion (see Image C) disposed on the lower portion (see Image C); and an upper portion (see Image C) disposed on the middle portion (see Image C), and wherein the first spacer covers a sidewall of the lower portion of the first conductive pattern (see Image C), and the second spacer covers a sidewall of the middle portion of the first conductive pattern (see Image C).
Ikeda does not teach a gate structure disposed on an upper portion of the active pattern and a capacitor disposed on the contact plug structure.
Kim’20 teaches a gate structure (see Kim’20 Fig. 3, first gate structure 160; Kim’20 [0014]) disposed on an upper portion of an active pattern (see Kim’20 Fig. 3, second active pattern 105; Kim’20 [0017]); and a capacitor (see Kim’20 Fig. 3, capacitor 540; Kim’20 [0014]) disposed on a contact plug structure (see Kim’20 Fig. 3 and Kim’20 [0047]: “The first contact plug structure on the first region I of the substrate 100 may include a lower contact plug 405, a first metal silicide pattern 435 and a first upper contact plug 455 sequentially stacked in the vertical direction.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to add a gate structure and a capacitor as taught by Kim’20 to the device of Ikeda in order to control transistors and store charges, respectively.
With regards to claim 3, Ikeda and Kim’20 teach the semiconductor device of claim 1, wherein the second spacer (see Ikeda Fig. 5L, nitride liner layer 172) covers a sidewall of the upper portion (see Image C) of the first conductive pattern (see Ikeda Fig. 5B, bit line contact structure 154).
With regards to claim 7, Ikeda and Kim’20 teach the semiconductor device of claim 1, wherein a first width (see Image D) of the lower portion (see Image C) of the first conductive pattern (see Ikeda Fig. 5B, bit line contact structure 154) is greater than a second width (see Image D) of each of the middle portion (see Image C) and the upper portion (see Image C) of the first conductive pattern (see Image C, Image D, and Ikeda Fig. 5L).
With regards to claim 8, Ikeda and Kim’20 teach the semiconductor device of claim 1, further comprising: an isolation pattern (STI structure 54; Ikeda col. 5, ln. 6) disposed on the substrate (see Ikeda Fig. 5A, substrate 50) and covering a sidewall of the active pattern (see Ikeda Fig. 5L, active region 52); and an insulation pattern structure (see Ikeda Fig. 5L, insulating bottom 152a; Ikeda col. 4, ln. 21) disposed on the active pattern and the isolation pattern (see Ikeda Fig. 5L), wherein the gate structure (see Kim’20 Fig. 3, first gate structure 160) extends in a first direction (see Kim’20 Fig. 3, first direction) substantially parallel to the upper surface of the substrate (see Kim’20 Fig. 3) and is disposed on the upper portion of the active pattern and an upper portion of the isolation pattern (see Kim’20 Fig. 3), and wherein the bit line structure (see Ikeda Fig. 5B, bit line stack 168/168′) extends in a second direction (a direction coming out of the page like Kim’20 Fig. 3’s second direction) and is disposed on the active pattern and the insulation pattern structure (see Ikeda Fig. 5L), wherein the second direction is substantially parallel to the upper surface of the substrate and crosses the first direction (see Kim’20 Fig. 3).
With regards to claim 9, Ikeda and Kim’20 teach the semiconductor device of claim 8, wherein the bit line structure (see Ikeda Fig. 5B, bit line stack 168/168′) further includes: a third conductive pattern (see Ikeda Fig. 5L, TiN layer 152c; Ikeda col. 4, ln. 22) disposed on the insulation pattern structure (see Ikeda Fig. 5L, insulating bottom 152a), wherein the third conductive pattern is disposed on the upper portion (see Image C) of the first conductive pattern (see Ikeda Fig. 5B, bit line contact structure 154).
With regards to claim 11, Ikeda and Kim’20 teach the semiconductor device of claim 8, wherein an upper surface of the middle portion (see Image C) of the first conductive pattern (see Ikeda Fig. 5B, bit line contact structure 154) is substantially coplanar with an upper surface of the insulation pattern structure (see Image C).
With regards to claim 12, Ikeda and Kim’20 teach the semiconductor device of claim 1, wherein the lower spacer structure (see Ikeda Fig. 5L, insulating stack layer 370 and nitride layer 179) further includes a third spacer (see Ikeda Fig. 5L nitride layer 179; Ikeda col. 5, ln. 40) whose bottom and a sidewall are covered by the second spacer (see Ikeda Fig. 5L, nitride liner layer 172), and wherein the upper spacer structure (see Ikeda Fig. 5L, dielectric layer 174, dielectric layer 176, and dielectric layer 162) includes a fourth spacer (see Ikeda Fig. 5L, dielectric layer 162; Ikeda col. 5, ln. 13), a fifth spacer (see Ikeda Fig. 5L, dielectric layer 174; Ikeda col. 5, ln. 51) and a sixth spacer (see Ikeda Fig. 5L, dielectric layer 176; Ikeda col. 5, ln. 55) sequentially stacked on each other on the upper sidewall (see Ikeda Fig. 5L) of the bit line structure (see Ikeda Fig. 5B, bit line stack 168/168′) in a horizontal direction substantially parallel to the upper surface of the substrate (see Ikeda Fig. 5L).
Claim 4 is rejected under 35 U.S.C. 103 as being obvious over Kim’22 in view of Park (Pub. No. US 20190122980 A1).
With regards to claim 4, Kim’22 teaches the semiconductor device of claim 1, further comprising a third spacer (see Kim’22 Fig. 2, fourth lower spacer 365; Kim’22 [0028]) disposed below the first spacer (see Kim’22 Fig. 2) and contacting the sidewall of the lower portion (see Image A) of the first conductive pattern (see Kim’22 Fig. 2, conductive structure 265).
Kim’22 does not teach that the third spacer includes a polymer that decomposes at a temperature equal to or less than about 300°C.
Park teaches a spacer (Park Fig. 2a, char spacer PBC) that includes a polymer that decomposes at a temperature equal to or less than about 300°C (the graft polymers GP are in the polymer brush layer PBL (see Park [0078]), which is etched to form the polymer brush patterns PB (see Park [0079]), which forms the char spacer PBC when thermally processed (see Park Abstract). See Park [0085]: " To form the char spacer PBC, a plurality of graft polymers GP forming the polymer brush pattern PB may be thermally processed in the absence of oxygen. At this time, thermal processing temperature may be the same or similar to the pyrolysis temperature of the graft polymers GP. For example, deposition for forming the second insulating spacer film 146L may be performed at about 250° C. to about 1,000° C. in the absence of oxygen so that the char spacer PBC is formed from the polymer brush pattern PB.". The temperature 250° C is less than 300° C, so the spacer can be made of a polymer that decomposes below 300° C.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the third spacer of Kim’22 with the material taught by Park in order to decrease the permittivity of the spacer structure (see Park [0100]: “According to the embodiment described with reference to FIGS. 4 through 18, a structure may be obtained in which an insulating spacer 140 including a char spacer PBC having very low permittivity (e.g., a permittivity of about 3 or less, e.g., less than about 3, 2.5, 2, or 1.5) is between a conductive line structure 130 and a conductive plug 460 and extends in a length direction of a bit line BL, and so the load capacitance between a plurality of conductive patterns in a cell miniaturized due to high integration density may be minimized.”).
Claims 5 and 6 are rejected under 35 U.S.C. 103 as being obvious over Ikeda and Kim’20 in view of Wu et al. (Pub. No.: US 20240213152 A1), hereinafter as Wu.
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Image E, close up of Wu Fig. 5 showcasing upper, middle, and lower portions.
With regards to claim 5, Ikeda and Kim’20 teach the semiconductor device of claim 1.
Ikeda and Kim’20 do not teach that each of the lower portion, the middle portion and the upper portion of the first conductive pattern has a shape of a cylinder, a square pillar or a square pillar with rounded vertices.
Wu teaches a bit line structure (see Wu Fig.1, bit line contact structures 2, connection layer 31, first barrier layer 32, conductive layer 33, and top isolation layer 34) including a first conductive pattern (see Wu Fig.1, bit line contact structures 2), a second conductive pattern (see Wu Fig.1, connection layer 31) and an insulation structure (see Wu Fig.1, top isolation layer 34) stacked on each other in a vertical direction substantially perpendicular to an upper surface of a substrate (see Wu Fig.1, substrate 1), wherein the first conductive pattern includes: a lower portion (see Image E, lower portion); a middle portion (see Image E, middle portion) disposed on the lower portion (see Wu Fig.1 and Image E); and an upper portion (see Image E, upper portion) disposed on the middle portion (see Wu Fig.1 and Image E).
Wu also teaches that the lower portion (see Image E, lower portion), the middle portion (see Image E, middle portion) and the upper portion (see Image E, upper portion) of the first conductive pattern (see Wu Fig.1, bit line contact structures 2) has a shape of a cylinder, a square pillar or a square pillar with rounded vertices (see Wu Fig. 4 and Wu [0059]: “The bit line contact structures 2 are filled in the corresponding bit line contact holes 11. The bit line contact hole 11 may be a round hole, a square hole or a special-shaped hole. The embodiment of the present disclosure does not limit the shape and size of the bit line contact hole 11.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the first conductive pattern of the combined device of Ikeda and Kim’20 with the shape taught by Wu in order to connect the bit line to specific regions of the active area and insulate the first conductive pattern on all sides.
With regards to claim 6, Ikeda and Kim’20 teach the semiconductor device of claim 1.
Ikeda and Kim’20 do not teach that each of the lower portion and the middle portion of the first conductive pattern has a shape of a cylinder, a square pillar or a square pillar with rounded vertices, and the upper portion of the first conductive pattern has a shape of a rectangular pillar or a rectangular pillar with rounded vertices.
Wu teaches a bit line structure (see Wu Fig.1, bit line contact structures 2, connection layer 31, first barrier layer 32, conductive layer 33, and top isolation layer 34) including a first conductive pattern (see Wu Fig.1, bit line contact structures 2), a second conductive pattern (see Wu Fig.1, connection layer 31) and an insulation structure (see Wu Fig.1, top isolation layer 34) stacked on each other in a vertical direction substantially perpendicular to an upper surface of a substrate (see Wu Fig.1, substrate 1), wherein the first conductive pattern includes: a lower portion (see Image E, lower portion); a middle portion (see Image E, middle portion) disposed on the lower portion (see Wu Fig.1 and Image E); and an upper portion (see Image E, upper portion) disposed on the middle portion (see Wu Fig.1 and Image E).
Wu also teaches that the lower portion (see Image E, lower portion) and the middle portion (see Image E, middle portion) of the first conductive pattern (see Wu Fig.1, bit line contact structures 2) has a shape of a cylinder, a square pillar or a square pillar with rounded vertices (see Wu Fig. 4 and Wu [0059]: “The bit line contact structures 2 are filled in the corresponding bit line contact holes 11. The bit line contact hole 11 may be a round hole, a square hole or a special-shaped hole. The embodiment of the present disclosure does not limit the shape and size of the bit line contact hole 11.”), and the upper portion (see Image E, upper portion) of the first conductive pattern (see Wu Fig.1, bit line contact structures 2) has a shape of a rectangular pillar or a rectangular pillar with rounded vertices (see Wu Fig. 4 and Wu [0059]: “The bit line contact structures 2 are filled in the corresponding bit line contact holes 11. The bit line contact hole 11 may be a round hole, a square hole or a special-shaped hole. The embodiment of the present disclosure does not limit the shape and size of the bit line contact hole 11.” A square hole is a rectangular hole, so the upper portion of the first conductive pattern has a rectangular pillar shape).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the first conductive pattern of the combined device of Ikeda and Kim’20 with the shape taught by Wu in order to connect the bit line to specific regions of the active area and insulate the first conductive pattern on all sides.
Claim 10 is rejected under 35 U.S.C. 103 as being obvious over Ikeda and Kim’20, in view of Yoon et al. (Pub. No.: US 20220181457 A1), hereinafter as Yoon.
With regards to claim 10, Ikeda and Kim’20 teach the semiconductor device of claim 9.
Ikeda and Kim’20 do not teach that each of the first and third conductive patterns includes polysilicon doped with n-type impurities.
Yoon teaches a first and third conductive patterns (see Yoon Fig. 17, first conductive pattern 416; and see Yoon Fig. 17, third conductive pattern 420) that includes polysilicon doped with n-type impurities (see Yoon [0158] and [0161]: “The first conductive pattern 416 may include, e.g., polysilicon doped with N-type impurities such as arsenic and/or phosphorus.” “The third conductive pattern 420 may include, e.g., polysilicon doped with an N-type impurities.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the first and third conductive patterns of the combined device of Ikeda and Kim’20 with the material taught by Yoon in order to allow the first and third conductive patterns to merge into one pattern (see Yoon [0161]: “The third conductive pattern 420 may include, e.g., polysilicon doped with an N-type impurities. For example, the first to third conductive patterns 416, 418, and 420 may include polysilicon, which is the same material. Thus, the first to third conductive patterns 416, 418, and 420 may be merged into one pattern, e.g. merged homogenously into one pattern.”).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Rhee, in view of Ahn et al. (Pub. No.: US 20190097007 A1), hereinafter as Ahn.
With regards to claim 16, Rhee teaches the semiconductor device of claim 13.
Rhee does not teach that the first spacer includes air.
Ahn teaches a first spacer (see Ahn Fig. 4A, lower air spacer 140AS; Ahn [0063]) includes air (being called lower air spacer would indicate that this spacer includes air.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the material of the first spacer of Rhee with that taught by Ahn in order to reduce parasitic capacitance between the bit line structure and contact plug structure by utilizing air’s low dielectric constant.
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ikeda and Kim'20, in view of Wu et al. (Pub. No.: US 20240213152 A1), hereinafter as Wu.
With regards to claim 18, Ikeda teaches a semiconductor device, comprising: an active pattern (see Ikeda Fig. 5L, active region 52; Ikeda col. 4, ln. 66) disposed on a substrate (see Ikeda Fig. 5A, substrate 50; Ikeda col. 4, ln. 65); a bit line structure (see Ikeda Fig. 5B, bit line stack 168/168′; Ikeda col. 5, ln. 18) disposed on the active pattern (see Ikeda Fig. 5L), wherein the bit line structure includes a first conductive pattern (see Ikeda Fig. 5B, bit line contact structure 154; Ikeda col. 5, ln. 9), a second conductive pattern (see Ikeda Fig. 5B, metal layer 156; Ikeda col. 5, ln. 12) and an insulation structure (see Ikeda Fig. 5B, dielectric layer 158; Ikeda col. 5, ln. 13) stacked on each other in a vertical direction (see Ikeda Fig. 5B) substantially perpendicular to an upper surface of the substrate (see Ikeda Fig. 5B); a lower spacer structure (see Ikeda Fig. 5L, insulating stack layer 370 and nitride layer 179; Ikeda col. 6, ln. 30 and Ikeda col. 5, ln. 40) disposed on a lower portion of a sidewall of the bit line structure (see Ikeda Fig. 5L); an upper spacer structure (see Ikeda Fig. 5L, dielectric layer 174, dielectric layer 176, and dielectric layer 162; Ikeda col. 5, ln. 51, Ikeda col. 5, ln. 55, and Ikeda col. 5, ln. 13) disposed on the lower spacer structure (see Ikeda Fig. 5L), and disposed on an upper portion of the sidewall of the bit line structure (see Ikeda Fig. 5L); a contact plug structure (see Ikeda Fig. 5L, capacitor contact structure 180; Ikeda col. 5, ln. 64) disposed on the active pattern (see Ikeda Fig. 5L), wherein the contact plug structure is spaced apart from the bit line structure (see Ikeda Fig. 5L), wherein the first conductive pattern includes: a lower portion (see Image C) contacting an upper surface of the active pattern (see Image C); a middle portion (see Image C) disposed on the lower portion (see Image C); and an upper portion (see Image C) disposed on the middle portion (see Image C), and wherein the lower spacer structure covers sidewalls of the lower portion and the middle portion of the first conductive pattern (see Image C), and the upper spacer structure covers a sidewall of the upper portion of the first conductive pattern (see Image C).
Ikeda does not teach a gate structure disposed on an upper portion of the active pattern; and a capacitor disposed on the contact plug structure; and that the upper portion of the first conductive pattern has a shape of a rectangular pillar or a rectangular pillar with rounded vertices.
Kim’20 teaches a gate structure (see Kim’20 Fig. 3, first gate structure 160; Kim’20 [0014]) disposed on an upper portion of an active pattern (see Kim’20 Fig. 3, second active pattern 105; Kim’20 [0017]); and a capacitor (see Kim’20 Fig. 3, capacitor 540; Kim’20 [0014]) disposed on a contact plug structure (see Kim’20 Fig. 3 and Kim’20 [0047]: “The first contact plug structure on the first region I of the substrate 100 may include a lower contact plug 405, a first metal silicide pattern 435 and a first upper contact plug 455 sequentially stacked in the vertical direction.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to add a gate structure and a capacitor as taught by Kim’20 to the device of Ikeda in order to control transistors and store charges, respectively.
Ikeda and Kim’20 do not teach that the upper portion of the first conductive pattern has a shape of a rectangular pillar or a rectangular pillar with rounded vertices.
Wu teaches that an upper portion (see Image E, upper portion) of a first conductive pattern (see Wu Fig.1, bit line contact structures 2) has a shape of a rectangular pillar or a rectangular pillar with rounded vertices (see Wu Fig. 4 and Wu [0059]: “The bit line contact structures 2 are filled in the corresponding bit line contact holes 11. The bit line contact hole 11 may be a round hole, a square hole or a special-shaped hole. The embodiment of the present disclosure does not limit the shape and size of the bit line contact hole 11.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the first conductive pattern of the combined device of Ikeda and Kim’20 with the shape taught by Wu in order to connect the bit line to specific regions of the active area and insulate the first conductive pattern on all sides.
With regards to claim 19, Ikeda, Kim’20, and Wu teach the semiconductor device of claim 18, wherein a first width (see Image D) of the lower portion (see Image C) of the first conductive pattern (see Ikeda Fig. 5B, bit line contact structure 154) is greater than a second width (see Image D) of each of the middle portion (see Image C) and the upper portion (see Image C) of the first conductive pattern (see Image C, Image D, and Ikeda Fig. 5L).
With regards to claim 20, Ikeda, Kim’20, and Wu teach the semiconductor device of claim 18, wherein the lower spacer structure (see Ikeda Fig. 5L, insulating stack layer 370 and nitride layer 179) includes air (see Ikeda col. 4, ln. 52-58: “The dielectric spacer 170 may be the oxide or air gap.” Also note Ikeda col. 4, ln. 59-64: “To fabricate the structure in FIG. 4, a fabrication process flow is further provided. FIG. 5A to FIG. 5L are drawings, schematically illustrating a process flow of a method to fabricate the memory cell as viewed by cross-section structure cutting at the line I-I in FIG. 2, according to an embodiment of the invention.”).
Response to Arguments
Applicant’s arguments, see page 13 for claim of 35 U.S.C. 102(b)(2)(C), filed 8/04/2026, with respect to the rejection(s) of claim(s) 1-20 under 35 U.S.C. 102 and 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of new prior art.
Conclusion
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/E.T.B./Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
