DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note by the Examiner
For clarity, references to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and examiner explanations for 102 &/or 103 rejections are provided in parenthesis.
Information Disclosure Statement
The information disclosure statement filed 11/17/2023 fails to comply with the provisions of 37 CFR 1.97, 1.98 and MPEP § 609 because Office Action dated August 20, 2024 from the Taiwan Patent Office for corresponding Taiwan Patent Application No. 112144592 does not have a concise explanation of relevance. It has been placed in the application file, but the information referred to therein has not been considered as to the merits. Applicant is advised that the date of any re-submission of any item of information contained in this information disclosure statement or the submission of any missing element(s) will be the date of submission for purposes of determining compliance with the requirements based on the time of filing the statement, including all certification requirements for statements under 37 CFR 1.97(e). See MPEP § 609.05(a).
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: 595 in Fig. 1. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to because line A-A' is not clearly shown in Figs. 1, 5, 13, 22, and 26, and lines A-A' and B-B' are not clearly shown in Fig. 3. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the first portion and the second portion of the upper portion of the first conductive pattern structure claimed in claim 15 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities: r
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 13-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With regards to claim 13, currently in the embodiments shown, the claimed bit line structure is not shown to have differing widths within the first conductive pattern and disposed upon the insulation pattern structure. There are two bit lines shown in the cross-sectional views, one showing differing widths within the first conductive pattern and another showing positioning upon the insulation pattern structure, but it is not shown that these bit lines are one and the same. Therefore, it is unclear how a bit line structure can have differing widths within the first conductive pattern and be disposed upon the insulation pattern structure.
With regards to claim 14, claim 14 is rejected because of its dependency on claim 13.
With regards to claim 15, it is unclear how the second portion contacts the top surface of the insulation pattern structure when the upper portion 255c is between the first barrier pattern 265 (which is part of a conductive structure) and the middle portion 255b (as seen in Fig. 2, 29, and 30). Furthermore, the specification and the drawings fail to demonstrate the first and second portions claimed in claim 15. Currently in the embodiments shown, the only top surface the upper portion 255c is in contact with is the middle portion 255b. Claim 15 is rejected also because of its dependency on claim 13.
With regards to claim 16, claim 16 is rejected because of its dependency on claim 13.
With regards to claim 17, claim 17 is rejected because of its dependency on claim 13.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 7, 12, and 18-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee et al. (Pub. No.: US 20230145857 A1), hereinafter as A_Lee.
The applied reference has a common applicant with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
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Image A.1, close up of A_Lee Fig. 24 showcasing upper, middle, and lower portions
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Image A.2, close up of A_Lee Fig. 24 showcasing various widths of portions
With regards to claim 1, A_Lee teaches a semiconductor device, comprising: an active pattern (see A_Lee Fig. 24, active pattern 103) disposed on a substrate (see A_Lee Fig. 24, substrate 100); a gate structure (see A_Lee Fig. 2, gate structure 170) disposed on an upper portion of the active pattern (see A_Lee Fig. 2);
a bit line structure (see A_Lee Fig. 24, bit line structure 395 consisting of: a first capping pattern 385, first etch stop pattern 365, a first mask 275, a fourth conductive pattern 265, a second barrier pattern 255, and a third conductive pattern 245; and a first filling pattern 750. Examiner notes that the first filling pattern 750 has conductive material as seen in A_Lee [0043] “The first filling pattern 750 includes a conductive material,”) disposed on the active pattern (see A_Lee Fig. 24, active pattern 103), wherein the bit line structure includes a first conductive pattern (see A_Lee Fig. 24, a third conductive pattern 245 and a first filling pattern 750), a second conductive pattern (see A_Lee Fig. 24, a fourth conductive pattern 265) and an insulation structure (see A_Lee Fig. 24, first mask 275, first etch stop pattern 365, and first capping pattern 385) stacked on each other in a vertical direction substantially perpendicular to an upper surface of the substrate (see A_Lee Fig. 24);
a lower spacer structure (see A_Lee Fig. 24, second filling pattern 810, second capping pattern 795, first air spacer 800, and first spacer 730) disposed on a lower portion of a sidewall of the bit line structure (see A_Lee Fig. 24); an upper spacer structure (see A_Lee Fig. 24, spacer structure 855; and A_Lee [0083]: “The air gap 835 may be referred as a second air spacer 835, and the second, third and fifth spacers 835, 820 and 840 form a spacer structure 855”) disposed on the lower spacer structure (see A_Lee Fig. 24), wherein the upper spacer structure is disposed on an upper portion of the sidewall of the bit line structure (see A_Lee Fig. 24);
a contact plug structure (see A_Lee Fig. 19, lower contact plugs 475, metal silicide pattern 500, upper contact plug 549, and first pad 700; see A_Lee [0023], where the first pad 700 is made of conductive materials: “The first pad 700 includes, for example, at least one of doped polysilicon, a metal such as tungsten or ruthenium, etc., a metal nitride such as titanium nitride or tantalum nitride, etc., or graphene.” ; and see A_Lee [0076]: “Referring to FIGS. 22 and 23, in an embodiment, the second metal layer 540 and the third barrier layer 530 are patterned to form an upper contact plug 549,”) disposed on the active pattern (see A_Lee Fig. 24), wherein the contact plug structure is spaced apart from the bit line structure (see A_Lee Fig. 24);
and a capacitor (see A_Lee Fig. 24, capacitor 670) disposed on the contact plug structure (see A_Lee Fig. 24), wherein the lower spacer structure includes: a first spacer (see A_Lee Fig. 24, first air spacer 800) partially covering a sidewall of the first conductive pattern (see A_Lee Fig. 24), and including air (see A_Lee [0097]: “Thus, the first air spacer 800 that includes a low-k material such as air”); and a second spacer (see A_Lee Fig. 24, second capping pattern 795) disposed on the first spacer (see A_Lee Fig. 24).
With regards to claim 2, A_Lee teaches the semiconductor device of claim 1, wherein the first conductive pattern (see A_Lee Fig. 24, a third conductive pattern 245 and a first filling pattern 750) includes: a lower portion (see Image A.1, lower portion) contacting an upper surface of the active pattern (see A_Lee Fig. 24, active pattern 103); a middle portion (see Image A.1, middle portion) disposed on the lower portion (see Image A.1); and an upper portion (see Image A.1, upper portion, where the upper portion is third conductive pattern 245) disposed on the middle portion (see Image A.1), and wherein the first spacer (see Image A.1 and A_Lee Fig. 24, first air spacer 800) covers a sidewall of the lower portion of the first conductive pattern (see Image A.1), and the second spacer (see Image A.1 and A_Lee Fig. 24, second capping pattern 795) covers a sidewall of the middle portion of the first conductive pattern (see Image A.1).
With regards to claim 7, A_Lee teaches the semiconductor device of claim 2, wherein a first width (see Image A.2, width W1) of the lower portion (see Image A.1, lower portion) of the first conductive pattern (see A_Lee Fig. 24, a third conductive pattern 245 and a first filling pattern 750) is greater than a second width (see Image A.2, width W2 and width W3) of each of the middle portion and the upper portion (see Image A.1, middle portion and upper portion (where the upper portion is third conductive pattern 245)) of the first conductive pattern (see Image A.2).
With regards to claim 12, A_Lee teaches the semiconductor device of claim 1, wherein the lower spacer structure (see A_Lee Fig. 24, second filling pattern 810, second capping pattern 795, first air spacer 800, and first spacer 730) further includes a third spacer (see A_Lee Fig. 24, second filling pattern 810) whose bottom and a sidewall are covered by the second spacer (see A_Lee Fig. 24, second capping pattern 795; and see A_Lee Fig. 24), and wherein the upper spacer structure (see A_Lee Fig. 24, spacer structure 855; and A_Lee [0083]: “The air gap 835 may be referred as a second air spacer 835, and the second, third and fifth spacers 835, 820 and 840 form a spacer structure 855”) includes a fourth spacer (see A_Lee Fig. 24, a third spacer 820), a fifth spacer (see A_Lee Fig. 24, air gap 835) and a sixth spacer (see A_Lee Fig. 24, fifth spacer 840) sequentially stacked on each other on the upper sidewall of the bit line structure (see A_Lee Fig. 24, a first capping pattern 385, first etch stop pattern 365, a first mask 275, a fourth conductive pattern 265, a second barrier pattern 255, a third conductive pattern 245, and a first filling pattern 750) in a horizontal direction substantially parallel to the upper surface of the substrate (see A_Lee Fig. 2, substrate 100; and see A_Lee Fig. 24).
With regards to claim 18, A_Lee teaches a semiconductor device, comprising: an active pattern (see A_Lee Fig. 24, active pattern 103) disposed on a substrate (see A_Lee Fig. 24, substrate 100); a gate structure (see A_Lee Fig. 2, gate structure 170) disposed on an upper portion of the active pattern (see A_Lee Fig. 2);
a bit line structure (see A_Lee Fig. 24, bit line structure 395 consisting of: a first capping pattern 385, first etch stop pattern 365, a first mask 275, a fourth conductive pattern 265, a second barrier pattern 255, and a third conductive pattern 245; and a first filling pattern 750. Examiner notes that the first filling pattern 750 has conductive material as seen in A_Lee [0043] “The first filling pattern 750 includes a conductive material,”) disposed on the active pattern (see A_Lee Fig. 24), wherein the bit line structure includes a first conductive pattern (see A_Lee Fig. 24, a third conductive pattern 245 and a first filling pattern 750), a second conductive pattern (see A_Lee Fig. 24, a fourth conductive pattern 265) and an insulation structure (see A_Lee Fig. 24, first mask 275, first etch stop pattern 365, and first capping pattern 385) stacked on each other in a vertical direction substantially perpendicular to an upper surface of the substrate (see A_Lee Fig. 24);
a lower spacer structure (see A_Lee Fig. 24, second filling pattern 810, second capping pattern 795, first air spacer 800, and first spacer 730) disposed on a lower portion of a sidewall of the bit line structure (see A_Lee Fig. 24); an upper spacer structure (see A_Lee Fig. 24, spacer structure 855; and A_Lee [0083]: “The air gap 835 may be referred as a second air spacer 835, and the second, third and fifth spacers 835, 820 and 840 form a spacer structure 855”) disposed on the lower spacer structure, and disposed on an upper portion of the sidewall of the bit line structure (see A_Lee Fig. 24);
a contact plug structure (see A_Lee Fig. 19, lower contact plugs 475, metal silicide pattern 500, upper contact plug 549, and first pad 700; see A_Lee [0023], where the first pad 700 is made of conductive materials: “The first pad 700 includes, for example, at least one of doped polysilicon, a metal such as tungsten or ruthenium, etc., a metal nitride such as titanium nitride or tantalum nitride, etc., or graphene.” ; and see A_Lee [0076]: “Referring to FIGS. 22 and 23, in an embodiment, the second metal layer 540 and the third barrier layer 530 are patterned to form an upper contact plug 549,”) disposed on the active pattern (see A_Lee Fig. 24), wherein the contact plug structure is spaced apart from the bit line structure (see A_Lee Fig. 24);
and a capacitor (see A_Lee Fig. 24, capacitor 670) disposed on the contact plug structure (see A_Lee Fig. 24), wherein the first conductive pattern includes: a lower portion (see Image A.1, lower portion) contacting an upper surface of the active pattern (see A_Lee Fig. 24, active pattern 103); a middle portion (see Image A.1, middle portion) disposed on the lower portion (see Image A.1); and an upper portion (see Image A.1, upper portion, where the upper portion is third conductive pattern 245) disposed on the middle portion (see Image A.1), wherein the upper portion of the first conductive pattern has a shape of a rectangular pillar (see Image A.1, A_Lee Fig. 24, and A_Lee Fig. 22. The upper portion is third conductive pattern 245 and third conductive pattern 245 is part of bit line structure 395. Fig. 22 shows bit line structure 395 as long rectangle in plan view, so therefore third conductive pattern 245 is also a rectangle in plan view giving the upper portion a rectangular pillar shape.), and wherein the lower spacer structure covers sidewalls of the lower portion and the middle portion of the first conductive pattern (see Image A.1 and A_Lee Fig. 24), and the upper spacer structure covers a sidewall of the upper portion of the first conductive pattern (see Image A.1 and A_Lee Fig. 24).
With regards to claim 19, A_Lee teaches the semiconductor device of claim 18, wherein a first width (see Image A.2, width W1) of the lower portion (see Image A.1, lower portion) of the first conductive pattern (see A_Lee Fig. 24, a third conductive pattern 245 and a first filling pattern 750) is greater than a second width (see Image A.2, width W2) of each of the middle portion and the upper portion (see Image A.1, middle portion and upper portion (where the upper portion is third conductive pattern 245)) of the first conductive pattern (see Image A.2).
With regards to claim 20, A_Lee teaches the semiconductor device of claim 18, wherein the lower spacer structure (see A_Lee Fig. 24, second filling pattern 810, second capping pattern 795, first air spacer 800, and first spacer 730) includes air (see A_Lee [0097]: “Thus, the first air spacer 800 that includes a low-k material such as air”).
Claims 1-3, 8, 9, and 11 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee et al. (Patent No.: 12,414,289), hereinafter as B_Lee.
The applied reference has a common applicant with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
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Image B, close up of B_Lee Fig. 27 showcasing upper, middle, and lower portions
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Image C, close up of B_Lee Fig. 27 showcasing coplanarity between the middle portion and the insulation pattern structure
With regards to claim 1, B_Lee teaches a semiconductor device, comprising: an active pattern (see B_Lee Fig. 27, active pattern 103) disposed on a substrate (see B_Lee Fig. 27, substrate 100); a gate structure (see B_Lee Fig. 27, gate structure 170) disposed on an upper portion of the active pattern (see B_Lee Fig. 27);
a bit line structure (see B_Lee Fig. 27, bit line structure 395; and B_Lee col. 5, ln. 7-11: “In addition, the bit line structure 395 may include an insulation structure disposed on the conductive structure and including the first mask 275, the first etch stop pattern 365 and the first capping pattern 385 sequentially stacked on the conductive structure.”) disposed on the active pattern (see B_Lee Fig. 27), wherein the bit line structure includes a first conductive pattern (see B_Lee Fig. 27, third conductive pattern 245), a second conductive pattern (see B_Lee Fig. 27, fourth conductive pattern 265) and an insulation structure (see B_Lee Fig. 27, first mask 275, first etch stop pattern 365 and first capping pattern 385) stacked on each other in a vertical direction substantially perpendicular to an upper surface of the substrate (see B_Lee Fig. 27);
a lower spacer structure (see B_Lee Fig. 27, spacer structure 465) disposed on a lower portion of a sidewall of the bit line structure (see B_Lee Fig. 27); an upper spacer structure (see B_Lee Fig. 27, fourth spacer 490 and fifth capping pattern 714) disposed on the lower spacer structure (see B_Lee Fig. 27), wherein the upper spacer structure is disposed on an upper portion of the sidewall of the bit line structure (see B_Lee Fig. 27); a contact plug structure (see B_Lee Fig. 27, upper contact plug 549 and lower contact plugs 475) disposed on the active pattern (see B_Lee Fig. 27), wherein the contact plug structure is spaced apart from the bit line structure (see B_Lee Fig. 27);
and a capacitor (see B_Lee Fig. 27, capacitor 670) disposed on the contact plug structure (see B_Lee Fig. 27), wherein the lower spacer structure includes: a first spacer (see B_Lee Fig. 27, second spacer 435) partially covering a sidewall of the first conductive pattern (see B_Lee Fig. 27), and including air (see B_Lee col. 7, ln. 55-57 “Thus, a second spacer 435 including air may be formed between the first and third spacers 400 and 450, and may be referred to as an air spacer 435.”); and a second spacer (see B_Lee Fig. 27, third spacer 450) disposed on the first spacer (see B_Lee Fig. 27).
With regards to claim 2, the semiconductor device of claim 1, wherein the first conductive pattern (see B_Lee Fig. 27, third conductive pattern 245) includes: a lower portion (see Image B, lower portion) contacting an upper surface of the active pattern (see B_Lee Fig. 27, active pattern 103); a middle portion (see Image B, middle portion) disposed on the lower portion (see Image B); and an upper portion (see Image B, upper portion) disposed on the middle portion (see Image B), and wherein the first spacer (see Image B and B_Lee Fig. 27, second spacer 435) covers a sidewall of the lower portion of the first conductive pattern (see Image B), and the second spacer (see Image B and B_Lee Fig. 27, third spacer 450) covers a sidewall of the middle portion of the first conductive pattern (see Image B).
With regards to claim 3, B_Lee teaches the semiconductor device of claim 2, wherein the second spacer (see B_Lee Fig. 27, third spacer 450) covers a sidewall of the upper portion (see Image B, upper portion) of the first conductive pattern (see B_Lee Fig. 27, third conductive pattern 245; and see Image B).
With regards to claim 8, B_Lee teaches the semiconductor device of claim 2, further comprising: an isolation pattern (see B_Lee Fig. 27, isolation pattern 112) disposed on the substrate (see B_Lee Fig. 27, substrate 100) and covering a sidewall of the active pattern (see B_Lee Fig. 27); and an insulation pattern structure (see B_Lee Fig. 27, first insulation pattern structure 215) disposed on the active pattern (see B_Lee Fig. 27, active pattern 103) and the isolation pattern (see B_Lee Fig. 27), wherein the gate structure (see B_Lee Fig. 27, gate structure 170) extends in a first direction (see B_Lee Fig. 27, first direction D1) substantially parallel to the upper surface of the substrate and is disposed on the upper portion of the active pattern and an upper portion of the isolation pattern (see B_Lee Fig. 27), and wherein the bit line structure (see B_Lee Fig. 27, bit line structure 395) extends in a second direction (see B_Lee Fig. 27, second direction D2) and is disposed on the active pattern and the insulation pattern structure (see B_Lee Fig. 27), wherein the second direction is substantially parallel to the upper surface of the substrate and crosses the first direction (see B_Lee Fig. 27).
With regards to claim 9, B_Lee teaches the semiconductor device of claim 8, wherein the bit line structure (see B_Lee Fig. 27, bit line structure 395) further includes: a third conductive pattern (see B_Lee Fig. 27, second barrier pattern 255) disposed on the insulation pattern structure (see B_Lee Fig. 27, first insulation pattern structure 215; and B_Lee Fig. 27), wherein the third conductive pattern is disposed on the upper portion of the first conductive pattern (see B_Lee Fig. 27, third conductive pattern 245; and Image B).
With regards to claim 11, B_Lee teaches the semiconductor device of claim 8, wherein an upper surface of the middle portion (see Image B, middle portion) of the first conductive pattern (see B_Lee Fig. 27, third conductive pattern 245) is substantially coplanar with an upper surface of the insulation pattern structure (see B_Lee Fig. 27, first insulation pattern structure 215; and see Image C).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 4 is rejected under 35 U.S.C. 103 as being obvious over B_Lee in view of Park (Pub. No. US 20190122980 A1).
The applied reference B_Lee has a common applicant with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
With regards to claim 4, B_Lee teaches the semiconductor device of claim 2, further comprising a third spacer (see B_Lee Fig. 27, first spacer 400) disposed below the first spacer (see B_Lee Fig. 27, second spacer 435) and contacting the sidewall of the lower portion (see Image B, lower portion) of the first conductive pattern (see B_Lee Fig. 27, third conductive pattern 245).
B_Lee does not teach that the third spacer includes a polymer that decomposes at a temperature equal to or less than about 300°C.
Park teaches a spacer (Park Fig. 2a, char spacer PBC) that includes a polymer that decomposes at a temperature equal to or less than about 300°C (the graft polymers GP are in the polymer brush layer PBL (see Park [0078]), which is etched to form the polymer brush patterns PB (see Park [0079]), which forms the char spacer PBC when thermally processed (see Park Abstract). See Park [0085]: " To form the char spacer PBC, a plurality of graft polymers GP forming the polymer brush pattern PB may be thermally processed in the absence of oxygen. At this time, thermal processing temperature may be the same or similar to the pyrolysis temperature of the graft polymers GP. For example, deposition for forming the second insulating spacer film 146L may be performed at about 250° C. to about 1,000° C. in the absence of oxygen so that the char spacer PBC is formed from the polymer brush pattern PB.". The temperature 250° C is less than 300° C, so the spacer can be made of a polymer that decomposes below 300° C.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the third spacer of B_Lee with the material taught by Park in order to decrease the permittivity of the spacer structure (see Park [0100]: “According to the embodiment described with reference to FIGS. 4 through 18, a structure may be obtained in which an insulating spacer 140 including a char spacer PBC having very low permittivity (e.g., a permittivity of about 3 or less, e.g., less than about 3, 2.5, 2, or 1.5) is between a conductive line structure 130 and a conductive plug 460 and extends in a length direction of a bit line BL, and so the load capacitance between a plurality of conductive patterns in a cell miniaturized due to high integration density may be minimized.”).
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Claims 5 and 6 are rejected under 35 U.S.C. 103 as being obvious over B_Lee in view of Wu et al. (Pub. No.: US 20240213152 A1), hereinafter as Wu.
The applied reference B_Lee has a common applicant with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
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Image D, close up of Wu Fig. 5 showcasing upper, middle, and lower portions
With regards to claim 5, B_Lee teaches the semiconductor device of claim 2.
B_Lee does not teach that each of the lower portion, the middle portion and the upper portion of the first conductive pattern has a shape of a cylinder, a square pillar or a square pillar with rounded vertices.
Wu teaches a bit line structure (see Wu Fig.1, bit line contact structures 2, connection layer 31, first barrier layer 32, conductive layer 33, and top isolation layer 34) including a first conductive pattern (see Wu Fig.1, bit line contact structures 2), a second conductive pattern (see Wu Fig.1, connection layer 31) and an insulation structure (see Wu Fig.1, top isolation layer 34) stacked on each other in a vertical direction substantially perpendicular to an upper surface of a substrate (see Wu Fig.1, substrate 1), wherein the first conductive pattern includes: a lower portion (see Image D, lower portion); a middle portion (see Image D, middle portion) disposed on the lower portion (see Wu Fig.1 and Image D); and an upper portion (see Image D, upper portion) disposed on the middle portion (see Wu Fig.1 and Image D).
Wu also teaches that the lower portion (see Image D, lower portion), the middle portion (see Image D, middle portion) and the upper portion (see Image D, upper portion) of the first conductive pattern (see Wu Fig.1, bit line contact structures 2) has a shape of a cylinder, a square pillar or a square pillar with rounded vertices (see Wu Fig. 4 and Wu [0059]: “The bit line contact structures 2 are filled in the corresponding bit line contact holes 11. The bit line contact hole 11 may be a round hole, a square hole or a special-shaped hole. The embodiment of the present disclosure does not limit the shape and size of the bit line contact hole 11.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the first conductive pattern of B_Lee with the shape taught by Wu in order to connect the bit line to specific regions of the active area and insulate the first conductive pattern on all sides.
With regards to claim 6, B_Lee teaches the semiconductor device of claim 2.
B_Lee does not teach that each of the lower portion and the middle portion of the first conductive pattern has a shape of a cylinder, a square pillar or a square pillar with rounded vertices, and the upper portion of the first conductive pattern has a shape of a rectangular pillar or a rectangular pillar with rounded vertices.
Wu teaches a bit line structure (see Wu Fig.1, bit line contact structures 2, connection layer 31, first barrier layer 32, conductive layer 33, and top isolation layer 34) including a first conductive pattern (see Wu Fig.1, bit line contact structures 2), a second conductive pattern (see Wu Fig.1, connection layer 31) and an insulation structure (see Wu Fig.1, top isolation layer 34) stacked on each other in a vertical direction substantially perpendicular to an upper surface of a substrate (see Wu Fig.1, substrate 1), wherein the first conductive pattern includes: a lower portion (see Image D, lower portion); a middle portion (see Image D, middle portion) disposed on the lower portion (see Wu Fig.1 and Image D); and an upper portion (see Image D, upper portion) disposed on the middle portion (see Wu Fig.1 and Image D).
Wu also teaches that the lower portion (see Image D, lower portion) and the middle portion (see Image D, middle portion) of the first conductive pattern (see Wu Fig.1, bit line contact structures 2) has a shape of a cylinder, a square pillar or a square pillar with rounded vertices (see Wu Fig. 4 and Wu [0059]: “The bit line contact structures 2 are filled in the corresponding bit line contact holes 11. The bit line contact hole 11 may be a round hole, a square hole or a special-shaped hole. The embodiment of the present disclosure does not limit the shape and size of the bit line contact hole 11.”), and the upper portion (see Image D, upper portion) of the first conductive pattern (see Wu Fig.1, bit line contact structures 2) has a shape of a rectangular pillar or a rectangular pillar with rounded vertices (see Wu Fig. 4 and Wu [0059]: “The bit line contact structures 2 are filled in the corresponding bit line contact holes 11. The bit line contact hole 11 may be a round hole, a square hole or a special-shaped hole. The embodiment of the present disclosure does not limit the shape and size of the bit line contact hole 11.” A square hole is a rectangular hole, so the upper portion of the first conductive pattern has a rectangular pillar shape).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the first conductive pattern of B_Lee with the shape taught by Wu in order to connect the bit line to specific regions of the active area and insulate the first conductive pattern on all sides.
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Claim 10 is rejected under 35 U.S.C. 103 as being obvious over B_Lee in view of Yoon et al. (Pub. No.: US 20220181457 A1), hereinafter as Yoon.
The applied references B_Lee and Yoon have a common applicant with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
With regards to claim 10, B_Lee teaches the semiconductor device of claim 9.
B_Lee does not teach that each of the first and third conductive patterns includes polysilicon doped with n-type impurities.
Yoon teaches a first and third conductive patterns (see Yoon Fig. 17, first conductive pattern 416; and see Yoon Fig. 17, third conductive pattern 420) that includes polysilicon doped with n-type impurities (see Yoon [0158] and [0161]: “The first conductive pattern 416 may include, e.g., polysilicon doped with N-type impurities such as arsenic and/or phosphorus.” “The third conductive pattern 420 may include, e.g., polysilicon doped with an N-type impurities.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the first and third conductive patterns of B_Lee with the material taught by Yoon in order to allow the first and third conductive patterns to merge into one pattern (see Yoon [0161]: “The third conductive pattern 420 may include, e.g., polysilicon doped with an N-type impurities. For example, the first to third conductive patterns 416, 418, and 420 may include polysilicon, which is the same material. Thus, the first to third conductive patterns 416, 418, and 420 may be merged into one pattern, e.g. merged homogenously into one pattern.”).
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Claims 13, 14, and 16 are rejected under 35 U.S.C. 103 as being obvious over A_Lee in view of Kim et al. (Patent No.: US 11706910 B2), hereinafter as Kim.
The applied references A_Lee and Kim have a common applicant with the instant application. Based upon the earlier effectively filed date of the references, they constitute prior art under 35 U.S.C. 102(a)(2).
With regards to claim 13, A_Lee teaches a semiconductor device, comprising: an active pattern (see A_Lee Fig. 24, active pattern 103) disposed on a substrate (see A_Lee Fig. 24, substrate 100); an isolation pattern (see A_Lee Fig. 24, isolation pattern 112) disposed on the substrate (see A_Lee Fig. 24), wherein the isolation pattern covers a sidewall of the active pattern (see A_Lee Fig. 24);
a gate structure (see A_Lee Fig. 2, gate structure 170) disposed on an upper portion of the active pattern and an upper portion of the isolation pattern (see A_Lee Fig. 2), wherein the gate structure extends in a first direction (see A_Lee Fig. 2, first direction D1) substantially parallel to an upper surface of the substrate (see A_Lee Fig. 2); an insulation pattern structure (see A_Lee Fig. 24, fourth pad 725 and gate mask 160) disposed on the active pattern, the isolation pattern and the gate structure (see A_Lee Figs. 24 and 2);
a bit line structure (see A_Lee Fig. 24, bit line structure 395 consisting of: a first capping pattern 385, first etch stop pattern 365, a first mask 275, a fourth conductive pattern 265, a second barrier pattern 255, and a third conductive pattern 245; and a first filling pattern 750. Examiner notes that the first filling pattern 750 has conductive material as seen in A_Lee [0043] “The first filling pattern 750 includes a conductive material,”), wherein the bit line structure includes a first conductive pattern structure (see A_Lee Fig. 24, a third conductive pattern 245 and a first filling pattern 750), a second conductive pattern (see A_Lee Fig. 24, a fourth conductive pattern 265) and an insulation structure (see A_Lee Fig. 24, first mask 275, first etch stop pattern 365, and first capping pattern 385) sequentially stacked in a vertical direction substantially perpendicular to the upper surface of the substrate (see A_Lee Fig. 24);
a lower spacer structure (see A_Lee Fig. 24, second filling pattern 810, second capping pattern 795, first air spacer 800, and first spacer 730) disposed on a lower portion of a sidewall of the bit line structure (see A_Lee Fig. 24), and including a first spacer (see A_Lee Fig. 24, first air spacer 800), a second spacer (see A_Lee Fig. 24, second capping pattern 795) and a third spacer (see A_Lee Fig. 24, second filling pattern 810);
an upper spacer structure (see A_Lee Fig. 24, spacer structure 855; and A_Lee [0083]: “The air gap 835 may be referred as a second air spacer 835, and the second, third and fifth spacers 835, 820 and 840 form a spacer structure 855”) disposed on the lower spacer structure and on an upper portion of the sidewall of the bit line structure (see A_Lee Fig. 24);
a contact plug structure (see A_Lee Fig. 19, lower contact plugs 475, metal silicide pattern 500, upper contact plug 549, and first pad 700; see A_Lee [0023], where the first pad 700 is made of conductive materials: “The first pad 700 includes, for example, at least one of doped polysilicon, a metal such as tungsten or ruthenium, etc., a metal nitride such as titanium nitride or tantalum nitride, etc., or graphene.” ; and see A_Lee [0076]: “Referring to FIGS. 22 and 23, in an embodiment, the second metal layer 540 and the third barrier layer 530 are patterned to form an upper contact plug 549,”) disposed on the active pattern, and spaced apart from the bit line structure (see A_Lee Fig. 24);
and a capacitor (see A_Lee Fig. 24, capacitor 670) disposed on the contact plug structure (see A_Lee Fig. 24), wherein the first conductive pattern structure includes a lower portion (see Image A.1, lower portion), a middle portion (see Image A.1, middle portion) and an upper portion (see Image A.1, upper portion, where the upper portion is third conductive pattern 245) sequentially stacked on each other in the vertical direction (see Image A.1), and wherein a first width (see Image A.2, width W1), in the first direction, of the lower portion of the first conductive pattern structure (see Image A.1, lower portion) is greater than a second width (see Image A.2, width W2), in the first direction, of the middle portion of the first conductive pattern structure (see Image A.1, middle portion).
A_Lee does not teach that the bit line structure extends on the active pattern and the insulation pattern structure in a second direction, wherein the second direction is substantially parallel to the upper surface of the substrate and crosses the first direction.
Kim teaches an insulation pattern structure (see Kim Fig. 2, first insulation pattern 175, second insulation pattern 185, third insulation pattern 195, and gate mask 150) disposed on an active pattern (see Kim Fig. 2, active pattern 105), an isolation pattern (see Kim Fig. 2, isolation pattern 110) and a gate structure (see Kim Fig. 2, gate structure 160) and a bit line structure (see Kim Fig. 2, bit line structure 325) extending on the active pattern and the insulation pattern structure in a second direction (see Kim Figs. 1&2, the bit line structure 325 on the left of cross-sectional view A-A’ corresponds with the bit line structure 325 on the left of cross-sectional view B-B’, as seen in Kim Figs. 1&2. In cross-sectional view B-B’, that bit line structure is disposed on gate mask 150, which is part of the insulation pattern structure, as seen in Kim Fig. 2. In cross-sectional view A-A’, that same bit line structure is disposed on active pattern 105. Both bit line structures extend in a second direction, as seen in Kim Fig. 2.), wherein the second direction is substantially parallel to the upper surface of the substrate and crosses the first direction (see Kim Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to substitute the insulation pattern structure of A_Lee with the insulation pattern structure taught by Kim in order to insulate the bit line structure from the gate structure and other structures below the bit line structure besides the active pattern.
With regards to claim 14, A_Lee teaches the semiconductor device of claim 13, wherein the upper spacer structure (see A_Lee Fig. 24, spacer structure 855; and A_Lee [0083]: “The air gap 835 may be referred as a second air spacer 835, and the second, third and fifth spacers 835, 820 and 840 form a spacer structure 855”) is disposed on a sidewall of the upper portion (see Image A.1, upper portion, where the upper portion is third conductive pattern 245) of the first conductive pattern structure (see A_Lee Fig. 24, a third conductive pattern 245 and a first filling pattern 750), and wherein a third width (see Image A.2, width W3), in the first direction (see A_Lee Fig. 2, first direction D1), of the upper portion (see Image A.1, upper portion, where the upper portion is third conductive pattern 245) of the first conductive pattern structure is substantially the same as the second width (see Image A.2, width W2), in the first direction, of the middle portion (see Image A.1, middle portion) of the first conductive pattern (see Image A.2).
With regards to claim 16, A_Lee teaches the semiconductor device of claim 13, wherein the first spacer (see A_Lee Fig. 24, first air spacer 800) includes air (see A_Lee [0097]: “Thus, the first air spacer 800 that includes a low-k material such as air”).
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Claim 17 is rejected under 35 U.S.C. 103 as being obvious over A_Lee in view of Park.
The applied reference A_Lee has a common applicant with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
With regards to claim 17, A_Lee teaches the semiconductor device of claim 13, wherein the lower spacer structure (see A_Lee Fig. 24, second filling pattern 810, second capping pattern 795, first air spacer 800, and first spacer 730) further includes a fourth spacer (see A_Lee Fig. 24, first spacer 730) that is disposed below the first spacer (see A_Lee Fig. 24, first air spacer 800; and see A_Lee Fig. 24), and contacts a sidewall of the lower portion (see Image A.1, lower portion) of the first conductive pattern structure (see A_Lee Fig. 24, a third conductive pattern 245 and a first filling pattern 750).
A_Lee does not teach that the fourth spacer includes a polymer that decomposes at a temperature equal to or less than about 300°C.
Park teaches a spacer (Park Fig. 2a, char spacer PBC) that includes a polymer that decomposes at a temperature equal to or less than about 300°C (the graft polymers GP are in the polymer brush layer PBL (see Park [0078]), which is etched to form the polymer brush patterns PB (see Park [0079]), which forms the char spacer PBC when thermally processed (see Park Abstract). See Park [0085]: " To form the char spacer PBC, a plurality of graft polymers GP forming the polymer brush pattern PB may be thermally processed in the absence of oxygen. At this time, thermal processing temperature may be the same or similar to the pyrolysis temperature of the graft polymers GP. For example, deposition for forming the second insulating spacer film 146L may be performed at about 250° C. to about 1,000° C. in the absence of oxygen so that the char spacer PBC is formed from the polymer brush pattern PB.". The temperature 250° C is less than 300° C, so the spacer can be made of a polymer that decomposes below 300° C.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the fourth spacer of A_Lee with the material taught by Park in order to decrease the permittivity of the spacer structure (see Park [0100]: “According to the embodiment described with reference to FIGS. 4 through 18, a structure may be obtained in which an insulating spacer 140 including a char spacer PBC having very low permittivity (e.g., a permittivity of about 3 or less, e.g., less than about 3, 2.5, 2, or 1.5) is between a conductive line structure 130 and a conductive plug 460 and extends in a length direction of a bit line BL, and so the load capacitance between a plurality of conductive patterns in a cell miniaturized due to high integration density may be minimized.”).
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Conclusion
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/E.T.B./Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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