DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
For Examiner’s Interview fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html).
Status of claim(s) to be treated in this office action:
Independent: 1.
Pending: 1-11.
Information Disclosure Statement
Applicant’s IDS(s) submitted on 11/17/2023 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has/have considered by the examiner and made of record.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5, 8-10 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Zhu et al., US Patent 11475837 B2;in view of Wang et al., US PG pub. 20220069041 A1.
Re: Independent Claim 1, Zhu discloses a) using a stack comprising, in succession:
a substrate (10, fig. 7), incorporating n-type thin-film transistors (11, fig. 7;column 11, lines 57-67 and column 12, lines 1-15) each comprising a drain, a source and a gate;
an interconnecting structure (interconnect via structure connected to source and drain of transistor 11, fig. 8), electrically connected to the n-type thin-film transistors (11, fig. 7), and comprising:
a common anode (31, fig. 9), electrically connected to the sources of the n-type thin-film transistors (11, fig. 7);
vias (13, fig. 8), each electrically connected to a drain of one n-type thin-film transistor (11, fig. 7);
b) forming a set of anode (31, fig. 9) layers and a set of electrical contact pads (see annotated figure 7 below) on a surface of the interconnecting structure (interconnect via structure connected to source and drain of transistor 11, fig. 8), the anode (31, fig. 9) layers being spaced apart from one another so as to form a network of rows and of columns, each anode (31, fig. 9) layer being electrically connected to the common anode (31, fig. 9), each electrical contact pad being adjacent to one anode (31, fig. 9) layer and being electrically connected to one via;
c) forming a set of stacks of organic semiconductor layers (33, fig. 12), each stack of organic semiconductor layers (33, fig. 12) extending over one anode (31, fig. 9) layer and around said anode (31, fig. 9) layer, at distance from an electrical contact pad adjacent to said anode (31, fig. 9) layer;
d) forming a cathode layer (34, fig. 11) extending over the surface of the interconnecting structure (interconnect via structure connected to source and drain of transistor 11, fig. 8), over the set of stacks of organic semiconductor layers (33, fig. 12) and over the set of electrical contact pads (see annotated figure 7 below);
e) successively forming a capping layer (70, fig. 4) and an encapsulating layer (40, fig. 4) on the cathode layer (34, fig. 11).
Zhu is silent regarding: f) locally etching the encapsulating layer, the capping layer and the cathode layer (34, fig. 11) until the surface of the interconnecting structure (interconnect via structure connected to source and drain of transistor 11, fig. 8) is reached, so as to electrically isolate the anode (31, fig. 9) layers therebetween from the cathode layer (34, fig. 11) and to form a matrix array of pixels, each pixel comprising one anode (31, fig. 9) layer and one electrical contact pad adjacent to said anode (31, fig. 9) layer.
Wang teaches an etching to the encapsulating layer (70, fig. 1), the capping layer (30, fig. 9) and the cathode layer (60, fig. 9) until the surface of the interconnecting structure (110, fig. 9 and fig. 10) is reached, so as to electrically isolate the anode layers (40, fig. 9) therebetween from the cathode layer (60, fig. 9).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a transmittance region opening since this can improve light emission and transmission include high transparency area.
Re: Claim 2, Zhu and Wang discloses all the limitations of claim 1 on which this claim depends. Zhu is silent regarding: wherein step f) is executed by ion beam etching.
Wang discloses wherein step f) is executed by ion beam etching (¶049 dry-etching).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include ion beam etching since dry etching offer excellent defined sidewall trenches prevent any over etching.
Re: Claim 3, Zhu and Wang discloses all the limitations of claim 1 on which this claim depends. Zhu is silent regarding: wherein step f) is preceded by a step of forming a photosensitive etch mask on the encapsulating layer formed in step e), the photosensitive etch mask being designed to define the matrix array of pixels.
Wang discloses wherein step f) is preceded by a step of forming a photosensitive etch mask on the encapsulating layer formed in step e), the photosensitive etch mask being designed to define the matrix array of pixels (¶0051).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include the use of photosensitive etch mask to pattern of the pixel defining layer film since photoresist mask can provide high resolution patterning prevent any inaccuracy and defect to the patterning.
Re: Claim 5, Zhu and Wang discloses all the limitations of claim 1 on which this claim depends. Zhu is silent regarding: wherein step f) forms etched regions; and step f) is followed by a step g) of filling the etched regions with an encapsulating material.
Wang discloses, fig. 14, wherein step f) forms etched regions; and step f) is followed by a step g) of filling the etched regions with an encapsulating material (80, fig. 14).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include encapsulating material in the etched trench since this can protect the display element and TFT from being damage.
Re: Claim 8, Zhu and Wang discloses all the limitations of claim 1 on which this claim depends. Zhu further discloses: wherein step d) is executed so that the cathode layer (34, fig. 11) is made of silver Ag (column 16, lines 1-12).
Re: Claim 9, Zhu and Wang discloses all the limitations of claim 1 on which this claim depends. Zhu further discloses: wherein steps d) and e) are executed so that the cathode layer (34, fig. 11), the capping layer and the encapsulating layer have a thickness.
Zhu is silent regarding: the cathode layer, the capping layer and the encapsulating layer have a total thickness of 75 nm or less.
However, thickness range would have been obvious to an ordinary artisan practicing the invention because, absent evidence of disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 105 USPQ 223, 235 (CCPA 1955). Furthermore, the specification contains no disclosure of either the critical nature of the claimed dimensions of any unexpected results arising therefrom. Where patentability is aid to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2sd 1934, 1936 (Fed. Cir. 1990). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the display device of Zhu et al., as modified above to include thickness such as 75nm or less formed above the TFT device since such modification would have only involved a mere change in working range which involves only routine skill in the art one would have been motivated to make such modification to make those layer to have a thinner cathode, capping and encapsulation layer thickness to achieve the predictable result of miniaturization the display device thereby improve the high-density integration.
Re: Claim 10, Zhu and Wang discloses all the limitations of claim 1 on which this claim depends. Zhu further discloses: step c) is executed with a shadow mask (column 13, lines 3-6) step d) is executed without a shadow mask (column 13, lines 6-11).
Claim(s) 4 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Zhu et al., US Patent 11475837 B2;in view of Wang et al., US PG pub. 20220069041 A1; further in view of Cartlidge et al., US PG pub. 20060192081 A1.
Re: Claim 4, Zhu and Wang discloses all the limitations of claim 1 on which this claim depends. Zhu and Wang is silent regarding: wherein step b) is executed so that the network of rows and of columns has a pitch less than or equal to 10 µm.
Cartlidge discloses the CMOS array of pixel with pixels of approximately 5 microns a projected pixel-pitch of 1 um (¶0137-¶0143).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a pixel pitch of less then 10 µm can enables ultra-high density display. By reducing the space between the pixels, this high density maximizes the pixel count within a small area, significantly improving resolution and image clarity for high precision imaging device.
Claim(s) 6 and 7 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Zhu et al., US Patent 11475837 B2;in view of Wang et al., US PG pub. 20220069041 A1; further in view of McCormick et al., US PG pub. 20060061272 A1.
Re: Claim 6 and 7, Zhu and Wang discloses all the limitations of claim 1 on which this claim depends. Zhu and Wang is silent regarding: wherein step e) is executed so that the capping layer (70, fig. 4) is made of silicon monoxide SiO and the encapsulating layer is made of alumina Al2O3.
McCormick teaches an organic light emitting device wherein a capping layer (22, fig. 3) and encapsulating layer (34, fig. 3) covering the light emitting device (14, 16, 18, fig. 3), wherein the capping layer is made of silicon monoxide SiO (¶0078) and the encapsulating layer is made of alumina Al2O3 (¶0039).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include capping layer to be made of silicon monoxide and encapsulating layer made of alumina since both material have excellent transparency allow more light the escape the device rather than trapped inside the layers thereby improving light efficiency.
Claim(s) 11 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Zhu et al., US Patent 11475837 B2;in view of Wang et al., US PG pub. 20220069041 A1; further in view of Shinokawa et al., US PG pub.20200006661 A1.
Re: Claim 11, Zhu and Wang discloses all the limitations of claim 10 on which this claim depends. Zhu is silent regarding: wherein step c) is followed by a step of removing the shadow mask in an inert atmosphere.
Shinokawa teaches using the method of removing thin film in an inert atmosphere to form organic functional layer above the pixel electrode (¶0630-¶0631).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include the process of using inert gas to remove film this can prevent any unwanted oxidation build up during the removing process.
Annotated figure 7 of Zhu et al., US patent 11475837 B2.
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Prior art made of record and not relied upon are considered pertinent to current application disclosure.
* (“Jinta US PG pub. 20230217710 A1”) Discloses an image display device includes a plurality of pixels arranged two-dimensionally. A pixel in a first pixel region including some pixels among the plurality of pixels includes a first light emitting region, a second light emitting region having a higher visible light transmittance than the first light emitting region, a first self-light emitting element that emits light from the first light emitting region, a second self-light emitting element that emits light from the second light emitting region, and a pixel circuit that controls light emission and light turn-off of the first self-light emitting element and the second self-light emitting element. A pixel in a second pixel region other than the first pixel region among the plurality of pixels includes a third light emitting region having a lower visible light transmittance than the second light emitting region, and a third self-light emitting element emitting light from the third light emitting region.
* (“Kim et al., US PG pub. 20210202592 A1”) discloses an organic light emitting display device includes a transparent base member, a touch sensor which includes a touch electrode disposed above the transparent base member and a touch protection layer which covers the touch electrode, a black matrix which is disposed below or above the touch sensor and defines a plurality of opening areas, a plurality of color filters which is disposed on the same plane as the black matrix and corresponds to the plurality of opening areas, a first buffer layer disposed above the upper one of the touch sensor and the plurality of color filters, a thin film transistor disposed above the first buffer layer, and an organic light emitting element which is disposed above the thin film transistor and corresponds to the plurality of opening areas.
* (“Chung et al., US Patent 10074705 B2”) discloses a method of manufacturing a transparent display device, a substrate including a pixel region and a transmission region may be provided. A first electrode may be formed on the substrate in the pixel region, and a display layer may be formed on the first electrode. A second electrode facing the first electrode may be formed on the display layer, and a capping structure including a first capping layer and a second capping layer may be formed on the second electrode. The first capping layer may be formed on the second electrode in the pixel region and a first region of the transmission region by using a mask that has an opening, the mask may be shifted, and the second capping layer may be formed on the second electrode in the pixel region and a second region of the transmission region by using the shifted mask.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZ CHIU whose telephone number is 571-272-8656. The examiner can normally be reached on M-F, 9:00AM to 5:00PM (EST).
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/TSZ K CHIU/Examiner, Art Unit 2898 Tsz.Chiu@uspto.gov
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898