DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-18 are pending and are rejected.
Priority
Provisional:
Current application has PROVISIONAL application 63/426,643 filled on 11/18/2022.
Drawings
Drawings filled on 11/17/2023 are acceptable for the examination purpose.
Claim Objections
Claim(s) are objected to because of the following informalities:
Regarding claim(s) 7:
Claim recites, a means for copying, using the test jig with the pins, an electronic storage element of the IoT device; and a means for transmitting the copy of the electronic storage element to an electronic device.
The first limitation states that a copy/read/retrieve is performed from an electronic storage element. The next limitation states that “the copy of the electronic storage element” is transmitted such that meaning of this limitation is not clear and erroneous. It is not clear how a copy of the physical electronic storage element can be transmitted. This limitation includes typographical error and doesn’t clearly state whether data has been copied from electronic storage element and that “copied” data has been transmitted. It is erroneous, because claim states a copy of a physical “electronic storage element” is transmitted.
For the examination purpose, it is construed that the data from the electronic storage element has been copied and transmitted.
Appropriate correction is required.
Regarding claim(s) 13:
Claim recites, copying, using the test jig with the pins, an electronic storage element of the IoT device; and transmitting the copy of the electronic storage element to an electronic device. These limitations are objected to for the same reasons as described above in claim 7.
For the examination purpose, it is construed that the data from the electronic storage element has been copied and transmitted.
Appropriate correction is required.
Regarding claim(s) 14-18:
Claims recite, The method of claim 13. There is a typographical error, because claim 13 is not a method claim, it is a non-transitory computer readable medium.
For the examination purpose, the limitation, The method of claim 13 is construed as, The non-transitory computer readable medium of claim 13.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
Claim 7:
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f), is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f):
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f), is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f), is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f), except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f), except as otherwise indicated in an Office action.
The claim limitation uses the term “means” for performing the claimed function without reciting sufficient structure to perform the recited function. The term “means” is not modified by sufficient structure, material, or acts for performing the claimed function. Such claim limitation(s) is/are in claim 7:
a means for measuring a CT scan
a means for analyzing the CT scan
a means for copying,
a means for transmitting the copy of the electronic storage element
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f), it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
a means for measuring a CT scan being interpreted to cover the corresponding structure described in the specification paragraph 93: A Computed Tomography (CT) Scan of the Echo Dot 2 board was used to find these hidden connections. Table III lists all details about the CT scan hardware and the corresponding software used. By analyzing the traces revealed in the CT scan hidden connections for VCCQ and RST BGA pins were identified. Metal shielding was used as the GND connection. The VDD pin substitutes for the VCC pin.
a means for analyzing the CT scan being interpreted to cover the corresponding structure described in the specification paragraph 94: 3.2.1 Logic Analyzer: Once a connection was established to all the ISP pins a logic analyzer was used to check the signal data of the ISP connection (FIG. 12 ). The above stated method cross-compares the BGA 221 pinout sheet from section 3.1 and the CT-Scan images. The logic analyzer was also used to verify the individual pin voltages of recently identified ISP pins. The valid range for VCC and VCCQ are shown in Table IV.
a means for copying, being interpreted to cover the corresponding structure described in the specification paragraph 82: After testing the connections with an oscilloscope and logic analyzer, the soldered wires were connected to an eMMC reader. The cMMC reader was used to obtain a full data dump from the memory chip. More details are available in subsection 3.3. Data extraction from an onboard memory chip using ISP connections is considered relatively nondestructive as compared to chip-off.
However, the limitation a means for transmitting the copy of the electronic storage element, doesn’t have corresponding structure described in the specification as performing the claimed function. Therefore, this limitation is rejected under 35 U.S.C. 112(a)/(b). Please refer to the 35 U.S.C. 112 rejection section.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f).
Claim limitation(s) that recite(s) sufficient structure(s); therefor, this/these limitation(s)/element(s) is/are not interpreted under 35 U.S.C. 112(f):
Claim 7:
This application includes one or more claim limitations that use the word "means" but are nonetheless not being interpreted under 35 U.S.C. 112(f) because the claim limitation(s) recite(s) sufficient structure, materials, or acts to entirely perform the recited function. Such claim limitation(s) is/are: “a means for printing a 3D test jig” and “a means for assembling the test jig” in claim 7.
Because this/these claim limitation(s) is/are not being interpreted under 35 U.S.C. 112(f), it/they is/are not being interpreted to cover only the corresponding structure, material, or acts described in the specification as performing the claimed function, and equivalents thereof.
If applicant intends to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) applicant may: (1) amend the claim limitation(s) to remove the structure, materials, or acts that performs the claimed function; or (2) present a sufficient showing that the claim limitation(s) does/do not recite sufficient structure, materials, or acts to perform the claimed function.
Claim Rejections - 35 USC § 112
35 U.S.C. 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 7-12 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim limitations invoke 35 U.S.C. 112(f) but the written description fails to disclose the corresponding structure:
Claim 7:
Claim limitation “a means for transmitting the copy of the electronic storage element to an electronic device” invokes 35 U.S.C. 112(f) as described above. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function.
The specification is devoid of any structure that performs the function. In particular, the specification doesn’t provide any details of any structure that performs the claimed function of transmitting the copy of the electronic storage element to an electronic device. There is no disclosure of any particular structure, either explicitly or inherently, to perform the claimed function of transmitting the copy of the electronic storage element to an electronic device.
As would be recognized by those of ordinary skill in the art, the term transmitting the copy of the electronic storage element to an electronic device can be performed in any number of ways in hardware, software or a combination of the two. The specification does not provide sufficient details such that one of ordinary skill in the art would understand which structure or structures perform(s) the claimed function of transmitting the copy of the electronic storage element to an electronic device.
Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b).
Appropriate correction is required.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Dependent claims 8-12:
Based on their dependencies in claim 7, claims 8-12 are also rejected under 35 U.S.C. 112(b) for the same reasons.
35 U.S.C. 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 7-12 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor at the time the application was filed, had possession of the claimed invention.
Claim limitations invoke 35 U.S.C. 112(f) but the written description fails to disclose the corresponding structure:
Claim 7:
As described above, the disclosure does not provide adequate structure to perform the claimed function of transmitting the copy of the electronic storage element to an electronic device. The specification does not demonstrate that applicant has made an invention that achieves the claimed function because the invention is not described with sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor had possession of the claimed invention.
Appropriate correction is required.
Dependent claims 8-12:
Based on their dependencies in claim 7, claims 8-12 are also rejected under 35 U.S.C. 112(a) for the same reasons.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filling date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
Determining the scope and contents of the prior art.
Ascertaining the differences between the prior art and the claims at issue.
Resolving the level of ordinary skill in the pertinent art.
Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2, 5-8, 10-14 and 16-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li, Z et al., "A Common but Flexible Method for IoT Device Forensics," IEEE Global Communications Conference (GLOBECOM), Madrid, Spain, December 2021, pp. 1-7 [online], [retrieved on 05 March 2026]. Retrieved from the Internet, [hereinafter Li] and further in view of Armistead (US4852131A) [hereinafter ARMISTEAD].
Regarding claim 1:
LI discloses, A method for downloading the memory of an IoT device without powering up the IoT device, the method comprising: [page 1, abstract: forensic process for most of the IoT devices and utilize the up-to-date 3D print technique combined with the PoGo pins and Epoxy to customize a safe evidence acquisition tool for interface-lack IoT devices….
Page 3, column 1, ¶3: Retrieve forensically sound data multiple times from the prototype device via the external or extended pins.];
measuring a…scan of a printed circuit board associated with the IoT device; analyzing the…scan to determine visible and hidden connection points to and from at least one memory chip on the printed circuit board; [page 5, column 2, ¶4 – page 6, column 1, ¶1: Our proposal here is to utilize the exposed or to be extended pins of the on-board storage chip. The original PCB design may already extend the internal storage pins to external GPIO pins (Fig. 6),… Fig. 8 demonstrates one way to manually extend the storage pins when external pins are not available. First, a 3D print is conducted to create a transparent case to hold the minuscule IoT device and fix its position. Second, a transparent case cover is printed with holes pointing to the storage pins and the necessary µP pins. Third, we use PoGo (spring) pins to contact the storage pins and fix their positions to the case cover by using epoxy. Forth, we connect the reader to the extended (PoGo) pins.];
printing a structure of a test jig specific to the printed circuit board; [page 1, column 2, ¶6: Provide a forensic tool customizing method by utilizing 3D prints + PoGo pins + Epoxy….
Page 2, column 2, ¶8: Use a 3D-printer to create a case to hold/fix/protect the IoT device…
Page 3, column 1, ¶1: Use PoGo pins to contact the accurate positions of the internal µP and storage pins through the accurate holes of a 3D-printed transparent cover. 3D-print can provide fast and cost-effective prototyping for a customized design, which is required due to the diversity of modern IoT devices.];
assembling the test jig including adding pins into the structure for contacting at least one required connection point on the printed circuit board; [Page 3, column 1, ¶1: Use PoGo pins to contact the accurate positions of the internal µP and storage pins through the accurate holes of a 3D-printed transparent cover. 3D-print can provide fast and cost-effective prototyping for a customized design, which is required due to the diversity of modern IoT devices.];
reading data from the at least one memory chip on the printed circuit board, using the test jig with the pins; and creating a copy of the data from the at least one memory chip to an electronic device. [Page 3, column 1, ¶3: Retrieve forensically sound data multiple times from the prototype device via the external or extended pins. Generate hash sum or checksum to verify the integrity.
Examiner notes that LI teaches reading and retrieving data that is data has been copied for further processing], but doesn’t explicitly disclose, and
ARMISTEAD discloses, measuring a CT scan of a printed circuit board associated with the IoT device; analyzing the CT scan to determine visible and hidden connection points to and from at least one memory chip on the printed circuit board; [column 2, lines 54-57, 62-68: means and a process of non-destructively inspecting and generating feature image data of mechanical/electrical interconnections of electronic devices to printed circuit or wiring boards…a computed tomography (CT) system…scanning radiation in thinner slices through device interconnections and capable of detecting attenuated radiation from which to generate data representing slice images with a higher resolution. The CT system image data are analyzed automatically according to the invention by providing image data analyzing means…].
Therefore, it would have been obvious to one of ordinary skill in the art before the filling date of the claimed invention to have combined the capability of measuring a CT scan of a printed circuit board associated with the IoT device; analyzing the CT scan to determine visible and hidden connection points to and from at least one memory chip on the printed circuit board in order to obtain high resolution scan of the PCB and to have the advantage of non-destructively generating high resolution feature images of the interconnections of printed circuit or wiring boards to easily identify hidden connection points to and from at least one memory chip on the printed circuit board taught by ARMISTEAD with the method taught by LI as discussed above in order to have reasonable expectation of success such as to obtain high resolution scan of the PCB and to have the advantage of non-destructively generating high resolution feature images of the interconnections of printed circuit or wiring boards to easily identify hidden connection points to and from at least one memory chip on the printed circuit board [ARMISTEAD column 2 lines 67-68: generate data representing slice images with a higher resolution…
column 3, lines 58-59: computed tomography system 30 having very high spatial resolution].
Regarding claim 2:
LI and ARMISTEAD disclose, The method of claim 1, and
LI further discloses, wherein the IoT device is a smart home or commercial-grade IoT device. [page 3, column 1, ¶6 : Besides the aforementioned SoCs, the focus of our experiments is different ways to retrieve forensically sound evidence from different types of IoT devices,
Examiner notes that LI discloses, various IOT devices including smart home and commercial grade (e.g.; surveillance camera, speaker etc.)].
Regarding claim 5:
LI and ARMISTEAD disclose, The method of claim 1, and
LI further discloses, wherein the assembling step includes the use of spring-loaded pins contacting the connection points on the printed circuit board. [page 6, column 1, ¶1: Third, we use PoGo (spring) pins to contact the storage pins and fix their positions to the case cover by using epoxy. Forth, we connect the reader to the extended (PoGo) pins…
Page 3, column 1, ¶1: Use PoGo pins to contact the accurate positions of the internal µP and storage pins through the accurate holes of a 3D-printed transparent cover. 3D-print can provide fast and cost-effective prototyping for a customized design, which is required due to the diversity of modern IoT devices.].
Regarding claim 6:
LI and ARMISTEAD disclose, The method of claim 1, and
LI further discloses, wherein the at least one memory chip is attached to the printed circuit board. [ Page 3, column 1, ¶1: Use PoGo pins to contact the accurate positions of the internal µP and storage pins through the accurate holes of a 3D-printed transparent cover.].
Regarding claim 7:
LI discloses, A system for downloading the memory of an IoT device without powering up the IoT device, the system comprising: [page 1, abstract: forensic process for most of the IoT devices and utilize the up-to-date 3D print technique combined with the PoGo pins and Epoxy to customize a safe evidence acquisition tool for interface-lack IoT devices….
Page 3, column 1, ¶3: Retrieve forensically sound data multiple times from the prototype device via the external or extended pins.];
a means for measuring a…scan of a printed circuit board associated with the IoT device; a means for analyzing the…scan to determine any hidden connections; [page 5, column 2, ¶4 – page 6, column 1, ¶1: Our proposal here is to utilize the exposed or to be extended pins of the on-board storage chip. The original PCB design may already extend the internal storage pins to external GPIO pins (Fig. 6),… Fig. 8 demonstrates one way to manually extend the storage pins when external pins are not available. First, a 3D print is conducted to create a transparent case to hold the minuscule IoT device and fix its position. Second, a transparent case cover is printed with holes pointing to the storage pins and the necessary µP pins. Third, we use PoGo (spring) pins to contact the storage pins and fix their positions to the case cover by using epoxy. Forth, we connect the reader to the extended (PoGo) pins.];
a means for printing a 3D test jig specific to the printed circuit board; [page 1, column 2, ¶6: Provide a forensic tool customizing method by utilizing 3D prints + PoGo pins + Epoxy….
Page 2, column 2, ¶8: Use a 3D-printer to create a case to hold/fix/protect the IoT device…
Page 3, column 1, ¶1: Use PoGo pins to contact the accurate positions of the internal µP and storage pins through the accurate holes of a 3D-printed transparent cover. 3D-print can provide fast and cost-effective prototyping for a customized design, which is required due to the diversity of modern IoT devices.];
a means for assembling the test jig including adding pins for contacting the printed circuit board; [Page 3, column 1, ¶1: Use PoGo pins to contact the accurate positions of the internal µP and storage pins through the accurate holes of a 3D-printed transparent cover. 3D-print can provide fast and cost-effective prototyping for a customized design, which is required due to the diversity of modern IoT devices.];
a means for copying, using the test jig with the pins, an electronic storage element of the IoT device; [Page 3, column 1, ¶3: Retrieve forensically sound data multiple times from the prototype device via the external or extended pins. Generate hash sum or checksum to verify the integrity.
Examiner notes that LI teaches reading and retrieving data that is data has been copied for further processing], but doesn’t explicitly disclose, and
ARMISTEAD discloses, a means for measuring a CT scan of a printed circuit board associated with the IoT device; a means for analyzing the CT scan to determine any hidden connections; a means for transmitting the copy of the electronic storage element to an electronic device. [column 2, lines 54-57, 62-68: means and a process of non-destructively inspecting and generating feature image data of mechanical/electrical interconnections of electronic devices to printed circuit or wiring boards…a computed tomography (CT) system…scanning radiation in thinner slices through device interconnections and capable of detecting attenuated radiation from which to generate data representing slice images with a higher resolution. The CT system image data are analyzed automatically according to the invention by providing image data analyzing means…
column 7, lines 54-57: image data comparing computer 61 uses the component defect severity variables to update the three defect records forming the component defect vector, and, in step 5I, stores the defect vector in the database memory 68.
Examiner notes the claim objections set forth in the current office action, and it is construed that the data from the electronic storage element has been copied and transmitted.
Examiner further notes the 35 USC § 112 rejections for the limitation “means for transmitting” specification not defining sufficient structure and details. In broadest reasonable interpretation, it is construed that, the data is copied and retrieved using any hardware or software means. Regarding the limitation transmitting to an electronic device, in broadest reasonable interpretation, it is construed that data is captured/retrieved by any electronic device (e.g.; retrieved data recording)].
Therefore, it would have been obvious to one of ordinary skill in the art before the filling date of the claimed invention to have combined the a means for measuring a CT scan of a printed circuit board associated with the IoT device; a means for analyzing the CT scan to determine any hidden connections; a means for transmitting the copy of the electronic storage element to an electronic device in order to obtain high resolution scan of the PCB and to have the advantage of non-destructively generating high resolution feature images of the interconnections of printed circuit or wiring boards to easily identify hidden connection points to and from at least one memory chip on the printed circuit board taught by ARMISTEAD with the system taught by LI as discussed above in order to have reasonable expectation of success such as to obtain high resolution scan of the PCB and to have the advantage of non-destructively generating high resolution feature images of the interconnections of printed circuit or wiring boards to easily identify hidden connection points to and from at least one memory chip on the printed circuit board [ARMISTEAD column 2 lines 67-68: generate data representing slice images with a higher resolution…
column 3, lines 58-59: computed tomography system 30 having very high spatial resolution].
Regarding claim 8:
LI and ARMISTEAD disclose, The system of claim 7, and
LI further discloses, wherein the IoT device comprises a printed circuit board and has at least one memory chip for storing data. [Page 3, column 1, ¶1: Use PoGo pins to contact the accurate positions of the internal µP and storage pins through the accurate holes of a 3D-printed transparent cover.].
Regarding claim 10:
LI and ARMISTEAD disclose, The system of claim 7, and
LI further discloses, wherein the printing means comprises a 3D printer. [Page 2, column 2, ¶8: Use a 3D-printer to create a case to hold/fix/protect the IoT device].
Regarding claim 11:
LI and ARMISTEAD disclose, The system of claim 7, and
LI further discloses, wherein the assembling means uses spring-loaded pin connectors, for contacting the printed circuit board. [page 6, column 1, ¶1: Third, we use PoGo (spring) pins to contact the storage pins and fix their positions to the case cover by using epoxy. Forth, we connect the reader to the extended (PoGo) pins…
Page 3, column 1, ¶1: Use PoGo pins to contact the accurate positions of the internal µP and storage pins through the accurate holes of a 3D-printed transparent cover. 3D-print can provide fast and cost-effective prototyping for a customized design, which is required due to the diversity of modern IoT devices.].
Regarding claim 12:
LI and ARMISTEAD disclose, The system of claim 7, and
LI further discloses, wherein the electronic storage element comprises an eMMC/eMCP chip or other memory chip. [Examiner notes that claim requires only one of the optional elements separated by or, and only one of them is given the patentable weight.
LI discloses, electronic storage element can be any memory chip.
Page 3, column 1, ¶1: Use PoGo pins to contact the accurate positions of the internal µP and storage pins through the accurate holes of a 3D-printed transparent cover…
page 3, column 1, ¶5: the flash storage is integrated to the µP,].
Regarding claim 13:
LI discloses, . A non-transitory computer readable medium for downloading the memory of an IoT device without powering up the IoT device, the non-transitory computer readable medium stores instructions that once executed by a processor, cause the processor to perform the steps of: [page 1, abstract: forensic process for most of the IoT devices and utilize the up-to-date 3D print technique combined with the PoGo pins and Epoxy to customize a safe evidence acquisition tool for interface-lack IoT devices….
Page 3, column 1, ¶3: Retrieve forensically sound data multiple times from the prototype device via the external or extended pins.];
measuring a…scan of a printed circuit board associated with the IoT device; analyzing the…scan to determine any hidden connections; [page 5, column 2, ¶4 – page 6, column 1, ¶1: Our proposal here is to utilize the exposed or to be extended pins of the on-board storage chip. The original PCB design may already extend the internal storage pins to external GPIO pins (Fig. 6),… Fig. 8 demonstrates one way to manually extend the storage pins when external pins are not available. First, a 3D print is conducted to create a transparent case to hold the minuscule IoT device and fix its position. Second, a transparent case cover is printed with holes pointing to the storage pins and the necessary µP pins. Third, we use PoGo (spring) pins to contact the storage pins and fix their positions to the case cover by using epoxy. Forth, we connect the reader to the extended (PoGo) pins.];
printing a mold for a test jig specific to the printed circuit board; [page 1, column 2, ¶6: Provide a forensic tool customizing method by utilizing 3D prints + PoGo pins + Epoxy….
Page 2, column 2, ¶8: Use a 3D-printer to create a case to hold/fix/protect the IoT device…
Page 3, column 1, ¶1: Use PoGo pins to contact the accurate positions of the internal µP and storage pins through the accurate holes of a 3D-printed transparent cover. 3D-print can provide fast and cost-effective prototyping for a customized design, which is required due to the diversity of modern IoT devices.];
assembling the test jig including adding pins for contacting the printed circuit board; [Page 3, column 1, ¶1: Use PoGo pins to contact the accurate positions of the internal µP and storage pins through the accurate holes of a 3D-printed transparent cover. 3D-print can provide fast and cost-effective prototyping for a customized design, which is required due to the diversity of modern IoT devices.];
copying, using the test jig with the pins, an electronic storage element of the IoT device; [Page 3, column 1, ¶3: Retrieve forensically sound data multiple times from the prototype device via the external or extended pins. Generate hash sum or checksum to verify the integrity.
Examiner notes that LI teaches reading and retrieving data that is data has been copied for further processing], but doesn’t explicitly disclose, and
ARMISTEAD discloses, measuring a CT scan of a printed circuit board associated with the IoT device; analyzing the CT scan to determine any hidden connections; transmitting the copy of the electronic storage element to an electronic device. [column 2, lines 54-57, 62-68: means and a process of non-destructively inspecting and generating feature image data of mechanical/electrical interconnections of electronic devices to printed circuit or wiring boards…a computed tomography (CT) system…scanning radiation in thinner slices through device interconnections and capable of detecting attenuated radiation from which to generate data representing slice images with a higher resolution. The CT system image data are analyzed automatically according to the invention by providing image data analyzing means…
column 7, lines 54-57: image data comparing computer 61 uses the component defect severity variables to update the three defect records forming the component defect vector, and, in step 5I, stores the defect vector in the database memory 68.
Examiner notes the claim objections set forth in the current office action, and it is construed that the data from the electronic storage element has been copied and transmitted.
Examiner further notes that, regarding the limitation transmitting to an electronic device, in broadest reasonable interpretation, it is construed that data is captured/retrieved by any electronic device (e.g.; retrieved data recording)].
Therefore, it would have been obvious to one of ordinary skill in the art before the filling date of the claimed invention to have combined the capability of measuring a CT scan of a printed circuit board associated with the IoT device; analyzing the CT scan to determine any hidden connections; transmitting the copy of the electronic storage element to an electronic device in order to obtain high resolution scan of the PCB and to have the advantage of non-destructively generating high resolution feature images of the interconnections of printed circuit or wiring boards to easily identify hidden connection points to and from at least one memory chip on the printed circuit board taught by ARMISTEAD with the system taught by LI as discussed above in order to have reasonable expectation of success such as to obtain high resolution scan of the PCB and to have the advantage of non-destructively generating high resolution feature images of the interconnections of printed circuit or wiring boards to easily identify hidden connection points to and from at least one memory chip on the printed circuit board [ARMISTEAD column 2 lines 67-68: generate data representing slice images with a higher resolution…
column 3, lines 58-59: computed tomography system 30 having very high spatial resolution].
Regarding claim 14:
LI and ARMISTEAD disclose, The non-transitory computer readable medium of claim 13, and
LI further discloses, wherein the IoT device comprises a printed circuit board and has at least one memory chip for storing data. [Page 3, column 1, ¶1: Use PoGo pins to contact the accurate positions of the internal µP and storage pins through the accurate holes of a 3D-printed transparent cover.].
Regarding claim 16:
LI and ARMISTEAD disclose, The non-transitory computer readable medium of claim 13, and
LI further discloses, wherein the printing step is performed by a 3D printer. [Page 2, column 2, ¶8: Use a 3D-printer to create a case to hold/fix/protect the IoT device].
Regarding claim 17:
LI and ARMISTEAD disclose, The non-transitory computer readable medium of claim 13, and
LI further discloses, wherein the assembling step includes the use of spring-loaded pin connectors, for contacting the printed circuit board. [page 6, column 1, ¶1: Third, we use PoGo (spring) pins to contact the storage pins and fix their positions to the case cover by using epoxy. Forth, we connect the reader to the extended (PoGo) pins…
Page 3, column 1, ¶1: Use PoGo pins to contact the accurate positions of the internal µP and storage pins through the accurate holes of a 3D-printed transparent cover. 3D-print can provide fast and cost-effective prototyping for a customized design, which is required due to the diversity of modern IoT devices.].
Regarding claim 18:
LI and ARMISTEAD disclose, The non-transitory computer readable medium of claim 13, and
LI further discloses, wherein the electronic storage element comprises an eMMC/eMCP chip or other memory chip. [Examiner notes that claim requires only one of the optional elements separated by or, and only one of them is given the patentable weight.
LI discloses, electronic storage element can be any memory chip.
Page 3, column 1, ¶1: Use PoGo pins to contact the accurate positions of the internal µP and storage pins through the accurate holes of a 3D-printed transparent cover…
page 3, column 1, ¶5: the flash storage is integrated to the µP,].
Claim(s) 3, 9 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over LI and ARMISTEAD, and further in view of YASUZAWA (US20100327879A1) [hereinafter YASUZAWA].
Regarding claim 3:
LI and ARMISTEAD disclose, The method of claim 1, and
LI further discloses, wherein the test jig comprises…for holding the printed circuit board during the reading step. ; [page 1, column 2, ¶6: Provide a forensic tool customizing method by utilizing 3D prints + PoGo pins + Epoxy….
Page 2, column 2, ¶8: Use a 3D-printer to create a case to hold/fix/protect the IoT device…
Page 3, column 1, ¶1: Use PoGo pins to contact the accurate positions of the internal µP and storage pins through the accurate holes of a 3D-printed transparent cover. 3D-print can provide fast and cost-effective prototyping for a customized design, which is required due to the diversity of modern IoT devices.], but LI and ARMISTEAD do not explicitly disclose, and
YASUZAWA discloses, wherein the test jig comprises multiple layers for holding the printed circuit board during the reading step. [¶18: the circuit test jig includes: a holding plate disposed between the circuit board and the print board and holds a plurality of conductive members that transmit signals between a group of terminals of the printed board and a group of terminals of the circuit board; and an elastic plate in which through holes are formed therein disposed at least one of between the holding plate and the circuit board or between the holding plate and the printed board.].
Therefore, it would have been obvious to one of ordinary skill in the art before the filling date of the claimed invention to have combined the test jig comprises multiple layers for holding the printed circuit board during the reading step in order to have the advantage of using this layered structure to have uniform contact of the metal Pogo pins and reduce the loads on the connectors taught by YASUZAWA with the method taught by LI and ARMISTEAD as discussed above in order to have reasonable expectation of success such as to have the advantage of using this layered structure to have uniform contact of the metal Pogo pins and reduce the loads on the connectors [YASUZAWA ¶67: because the loads that are applied to the LSI chip 31 and the print board 33 due to pin load repulsion of the metal Pogo pins can be efficiently dispersed, the loads on the metal Pogo pins 20 can be reduced to support uniform contact of the metal Pogo pins 20.].
Regarding claim 9:
LI and ARMISTEAD disclose, The system of claim 7, and
LI further discloses, wherein the test jig comprises…for pins and for holding the printed circuit board during the copying step. [page 1, column 2, ¶6: Provide a forensic tool customizing method by utilizing 3D prints + PoGo pins + Epoxy….
Page 2, column 2, ¶8: Use a 3D-printer to create a case to hold/fix/protect the IoT device…
Page 3, column 1, ¶1: Use PoGo pins to contact the accurate positions of the internal µP and storage pins through the accurate holes of a 3D-printed transparent cover. 3D-print can provide fast and cost-effective prototyping for a customized design, which is required due to the diversity of modern IoT devices.], but LI and ARMISTEAD do not explicitly disclose, and
YASUZAWA discloses, wherein the test jig comprises multiple layers for pins and for holding the printed circuit board during the copying step. [¶18: the circuit test jig includes: a holding plate disposed between the circuit board and the print board and holds a plurality of conductive members that transmit signals between a group of terminals of the printed board and a group of terminals of the circuit board; and an elastic plate in which through holes are formed therein disposed at least one of between the holding plate and the circuit board or between the holding plate and the printed board.].
Therefore, it would have been obvious to one of ordinary skill in the art before the filling date of the claimed invention to have combined the test jig comprises multiple layers for holding the printed circuit board during the reading step in order to have the advantage of using this layered structure to have uniform contact of the metal Pogo pins and reduce the loads on the connectors taught by YASUZAWA with the system taught by LI and ARMISTEAD as discussed above in order to have reasonable expectation of success such as to have the advantage of using this layered structure to have uniform contact of the metal Pogo pins and reduce the loads on the connectors [YASUZAWA ¶67: because the loads that are applied to the LSI chip 31 and the print board 33 due to pin load repulsion of the metal Pogo pins can be efficiently dispersed, the loads on the metal Pogo pins 20 can be reduced to support uniform contact of the metal Pogo pins 20.].
Regarding claim 15:
LI and ARMISTEAD disclose, The non-transitory computer readable medium of claim 13, and
LI further discloses, wherein the test jig comprises…for pins and for holding the printed circuit board during the copying step. [page 1, column 2, ¶6: Provide a forensic tool customizing method by utilizing 3D prints + PoGo pins + Epoxy….
Page 2, column 2, ¶8: Use a 3D-printer to create a case to hold/fix/protect the IoT device…
Page 3, column 1, ¶1: Use PoGo pins to contact the accurate positions of the internal µP and storage pins through the accurate holes of a 3D-printed transparent cover. 3D-print can provide fast and cost-effective prototyping for a customized design, which is required due to the diversity of modern IoT devices.], but LI and ARMISTEAD do not explicitly disclose, and
YASUZAWA discloses, wherein the test jig comprises multiple layers for pins and for holding the printed circuit board during the copying step. [¶18: the circuit test jig includes: a holding plate disposed between the circuit board and the print board and holds a plurality of conductive members that transmit signals between a group of terminals of the printed board and a group of terminals of the circuit board; and an elastic plate in which through holes are formed therein disposed at least one of between the holding plate and the circuit board or between the holding plate and the printed board.].
Therefore, it would have been obvious to one of ordinary skill in the art before the filling date of the claimed invention to have combined the test jig comprises multiple layers for holding the printed circuit board during the reading step in order to have the advantage of using this layered structure to have uniform contact of the metal Pogo pins and reduce the loads on the connectors taught by YASUZAWA with the system taught by LI and ARMISTEAD as discussed above in order to have reasonable expectation of success such as to have the advantage of using this layered structure to have uniform contact of the metal Pogo pins and reduce the loads on the connectors [YASUZAWA ¶67: because the loads that are applied to the LSI chip 31 and the print board 33 due to pin load repulsion of the metal Pogo pins can be efficiently dispersed, the loads on the metal Pogo pins 20 can be reduced to support uniform contact of the metal Pogo pins 20.].
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over LI and ARMISTEAD, and further in view of Suto et al. (US20180095109A1) [hereinafter Suto].
Regarding claim 4:
LI and ARMISTEAD disclose, The method of claim 1, but LI and ARMISTEAD do not explicitly disclose, and
LI further discloses, wherein the jig…produced by a 3D printer [Page 2, column 2, ¶8: Use a 3D-printer to create a case to hold/fix/protect the IoT device], but LI and ARMISTEAD do not explicitly disclose, and
Suto discloses, wherein the jig and its layers are produced by a 3D printer. [¶31: The test fixtures may be produced using an additive manufacturing process, such as three-dimensional (3D) printing. For example, a test fixture may be, or include, an interface (called an interconnect or translator) that is additively-manufactured using co-printed dielectric material (e.g., electrically non-conductive material) and electrically-conductive material….
¶39: Referring to FIG. 3, electrical connections between test pins of the test system's receiver interface and test pad locations on the UUT are implemented through conductive structures that are created, in whole or in part, through an additive manufacturing (e.g., 3D printing) process…
¶32: electrically non-conductive (or, simply “non-conductive”) layers are printed on a base plate. The base plate may become part of the test fixture, or it may be removed, as described herein. In an example, the lower test fixture interface to the test system is implemented by the base plate. For example, the base plate may provide the mechanical and electrical foundation upon which layers of material may be added by additive manufacturing to form the test fixture.].
Therefore, it would have been obvious to one of ordinary skill in the art before the filling date of the claimed invention to have combined the jig and its layers are produced by a 3D printer in order to reduce the cost and time to construct an appropriate test fixture/jig taught by Suto with the method taught by LI and ARMISTEAD as discussed above in order to have reasonable expectation of success such as to reduce the cost and time to construct an appropriate test fixture/jig [Suto ¶18: The foregoing may reduce the cost of an ICT cell and also may reduce the time to construct an appropriate test fixture.].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is listed in the PTO-892 Notice of Reference Cited document.
Huang (US6091253A) - Jig for electrically bridging between a circuit board and a tester during testing of the circuit board:
Column 1, lines 57-60: provide a working plate for supporting the circuit board properly and bringing the circuit board into contact with the probes simultaneously while performing the testing process..
Prokopp (US20030020506A1) - Testing device for printed circuit boards:
¶16: features a circuit board tester in which arranged between the two sets of contact fingers is a holder comprising portions for accommodating at least two circuit boards to be tested. At least one of the circuit boards to be tested is insertable in the holder means with its front side, and the other circuit board to be tested with its rear side, facing one of the two sets of contact fingers. The controller is configured such that with both sets of contact fingers the circuit board test points on both the front and rear sides of the circuit board to be tested can be contacted during a test procedure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED SHAFAYET whose telephone number is (571)272-8239. The examiner can normally be reached M-F 8:30 AM-5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kenneth Lo can be reached at (571) 272-9774. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/M.S./
Patent Examiner,
Art Unit 2116
/KENNETH M LO/Supervisory Patent Examiner, Art Unit 2116