DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
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Status of claim(s) to be treated in this office action:
Independent: 1, 11 and 16.
Pending: 1-20.
Withdrawn: 10 and 15
Information Disclosure Statement
Applicant’s IDS(s) submitted on 11/17/2023 & 5/28/2024 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has/have considered by the examiner and made of record.
Election/Restrictions
Applicant’s election without traverse of Species I Claim 1-20 in the reply filed on 5/5/2026 is acknowledged. Claim 10 and claim 15 wherein the horizontal insulating pattern has an air gap therein, related to Species III, therefore claim 10 and 15 is withdrawn from consideration.
Specification
The disclosure is objected to because of the following informalities:
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: GATE-ALL-AROUND FIELD EFFECT TRANSISTORS WITH INNER SPACER AND A MASK INSULATING PATTERN.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-9, 11, 13-14 and 16-20 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Kim et al., US PG pub. 20210217848 A1.
Re: Independent Claim 1, Kim discloses a substrate (100, fig. 3) including an active pattern (105, fig. 3); first and second semiconductor patterns (126c and 126b, fig. 4) on the active pattern (105, fig. 3) and vertically spaced apart from each other; a source/drain pattern (230, fig. 4) connected to the first and second semiconductor patterns (126c and 126b, fig. 4); a gate electrode (290, fig. 4) between the first and second semiconductor patterns (126c and 126b, fig. 4); and a gate insulating pattern (270, fig. 4) enclosing the gate electrode (290, fig. 4), wherein the gate insulating pattern (270, fig. 4) includes: a high-k dielectric pattern (270, fig. 4) enclosing the gate electrode (290, fig. 4), an inner spacer (220, fig. 4) between the high-k dielectric pattern (270, fig. 4) and the source/drain pattern (230, fig. 4), a mask insulating pattern (260, fig. 4) having an etch selectivity with respect to the inner spacer (220, fig. 4) between the high-k dielectric pattern (270, fig. 4) and the inner spacer (220, fig. 4).
Re: Claim 2, Kim disclose(s) all the limitations of claim 1 on which this claim depends. Kim further discloses: wherein the mask insulating pattern (260, fig. 4) has a side surface facing the inner spacer (220, fig. 4); and the side surface of the mask insulating pattern (260, fig. 4) has a profile that is concave toward the gate electrode (290, fig. 4).
Re: Claim 3, Kim disclose(s) all the limitations of claim 1 on which this claim depends. Kim further discloses: wherein the mask insulating pattern (260, fig. 4) is spaced apart from the first semiconductor pattern (126c, fig. 4).
Re: Claim 5, Kim disclose(s) all the limitations of claim 1 on which this claim depends. Kim further discloses: wherein at least a portion of the mask insulating pattern (260, fig. 4) is buried in the inner spacer (220, fig. 4).
Re: Claim 6, Kim disclose(s) all the limitations of claim 1 on which this claim depends. Kim further discloses: wherein the inner spacer (220, fig. 4) covers at least one of a top and bottom surface of the mask insulating pattern (260, fig. 4).
Re: Claim 7, Kim disclose(s) all the limitations of claim 1 on which this claim depends. Kim further discloses: wherein the inner spacer (220, fig. 4) has an outer side surface facing the gate electrode (290, fig. 4); and the mask insulating pattern (260, fig. 4) protrudes from the outer side surface of the inner spacer (220, fig. 4) toward the gate electrode (290, fig. 4).
Re: Claim 8, Kim disclose(s) all the limitations of claim 1 on which this claim depends. Kim further discloses: a horizontal insulating pattern (top and bottom portion of 260, fig. 4) between the high-k dielectric pattern (270, fig. 4) and the first semiconductor pattern (126c, fig. 4) and extending to a region between the first semiconductor pattern (126c, fig. 4) and the inner spacer (220, fig. 4).
Re: Claim 9, Kim disclose(s) all the limitations of claim 8 on which this claim depends. Kim further discloses: wherein the horizontal insulating pattern (top and bottom portion of 260, fig. 4) extends to a region between the inner spacer (220, fig. 4) and the source/drain pattern (230, fig. 4).
Re: Independent Claim 11, Kim discloses a substrate (100, fig. 3) including an active pattern (105, fig. 3); first and second semiconductor patterns (126c and 126b, fig. 4) on the active pattern (105, fig. 3) and vertically spaced apart from each other; a source/drain pattern (230, fig. 4) connected to the first and second semiconductor patterns (126c and 126b, fig. 4); a gate electrode (290, fig. 4) between the first and second semiconductor patterns (126c and 126b, fig. 4); and a gate insulating pattern (270, fig. 4) enclosing the gate electrode (290, fig. 4), wherein the gate insulating pattern (270, fig. 4) includes: a high-k dielectric pattern (270, fig. 4) enclosing the gate electrode (290, fig. 4), an inner spacer (220, fig. 4) between the high-k dielectric pattern (270, fig. 4) and the source/drain pattern (230, fig. 4), a mask insulating pattern (260, fig. 4) spaced apart from the first semiconductor pattern (126c, fig. 4) and between the high-k dielectric pattern (270, fig. 4) and the inner spacer (220, fig. 4).
Re: Claim 13, Kim disclose(s) all the limitations of claim 11 on which this claim depends. Kim further discloses: wherein the inner spacer (220, fig. 4) has an outer side surface facing the gate electrode (290, fig. 4); and the mask insulating pattern (260, fig. 4) protrudes from the outer side surface of the inner spacer (220, fig. 4) toward the gate electrode (290, fig. 4).
Re: Claim 14, Kim disclose(s) all the limitations of claim 11 on which this claim depends. Kim further discloses: a horizontal insulating pattern (top and bottom portion of 260, fig. 4) between the high-k dielectric pattern (270, fig. 4) and the first semiconductor pattern (126c, fig. 4) and extending to a region between the first semiconductor pattern (126c, fig. 4) and the inner spacer (220, fig. 4).
Re: Independent Claim 16, Kim discloses a substrate (100, fig. 3) including an active pattern (105, fig. 3); a plurality of semiconductor patterns stacked on the active pattern (105, fig. 3) and vertically spaced apart from each other; a source/drain pattern (230, fig. 4) connected to the semiconductor patterns; a gate electrode (290, fig. 4) between first and second semiconductor patterns (126c and 126b, fig. 4) of the semiconductor patterns; and a gate insulating pattern (270, fig. 4) enclosing the gate electrode (290, fig. 4), wherein the gate insulating pattern (270, fig. 4) includes: a high-k dielectric pattern (270, fig. 4) enclosing the gate electrode (290, fig. 4), an inner spacer (220, fig. 4) between the high-k dielectric pattern (270, fig. 4) and the source/drain pattern (230, fig. 4), a mask insulating pattern (260, fig. 4) between the high-k dielectric pattern (270, fig. 4) and the inner spacer (220, fig. 4), and a horizontal insulating pattern (top and bottom portion of 260, fig. 4) between the high-k dielectric pattern (270, fig. 4) and the first semiconductor pattern (126c, fig. 4) and extending to a region between the first semiconductor pattern (126c, fig. 4) and the inner spacer (220, fig. 4).
Re: Claim 17, Kim disclose(s) all the limitations of claim 16 on which this claim depends. Kim further discloses: wherein the horizontal insulating pattern (top and bottom portion of 260, fig. 4) is between the mask insulating pattern (260, fig. 4) and the first semiconductor pattern (126c, fig. 4).
Re: Claim 18, Kim disclose(s) all the limitations of claim 16 on which this claim depends. Kim further discloses: wherein the horizontal insulating pattern (top and bottom portion of 260, fig. 4) extends to a region between the gate electrode (290, fig. 4) and the first semiconductor pattern (126c, fig. 4) horizontally.
Re: Claim 19, Kim disclose(s) all the limitations of claim 16 on which this claim depends. Kim further discloses: wherein the gate electrode (290, fig. 4) comprises an upper gate electrode (290, fig. 4) on an uppermost semiconductor pattern; the gate insulating pattern (270, fig. 4) includes an upper gate insulating pattern (270, fig. 4) between the uppermost semiconductor pattern and the upper gate electrode (290, fig. 4); and the upper gate insulating pattern (270, fig. 4) does not include the same material as the mask insulating pattern (260, fig. 4).
Re: Claim 20, Kim disclose(s) all the limitations of claim 16 on which this claim depends. Kim further discloses: wherein the horizontal insulating pattern (top and bottom portion of 260, fig. 4) is a first horizontal insulating pattern (top and bottom portion of 260, fig. 4); the semiconductor device further includes a second horizontal insulating pattern (top and bottom portion of 260, fig. 4) between the high-k dielectric pattern (270, fig. 4) and the second semiconductor pattern (126b, fig. 4); and the first horizontal insulating pattern (top and bottom portion of 260, fig. 4) and the second horizontal insulating pattern (top and bottom portion of 260, fig. 4) are spaced apart from each other.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 and 12 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kim et al., US PG pub. 20210217848 A1; in view of Ha et al., US PG pub. 20200013870 A1.
Re: Claim 4, Kim disclose(s) all the limitations of claim 1 on which this claim depends. Kim is silent regarding: wherein the mask insulating pattern includes silicon nitride, silicon oxynitride, silicon carbon nitride, silicon carbon oxynitride, aluminum oxide, lanthanum oxide, or titanium oxide.
Ha discloses a mask insulating pattern (Gs, fig. 2A; ¶0051, SiN) having an etch selectivity with respect to the inner spacer (110, fig. 2A) between the high-k dielectric pattern (FE, fig. 2A) and the inner spacer (110, fig. 2A).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a silicon nitride layer therebetween can suppress short channel effect and improve tunneling barrier better than silicon oxide.
Re: Claim 12, Kim disclose(s) all the limitations of claim 11 on which this claim depends. Kim is silent regarding: wherein the mask insulating pattern includes silicon nitride, silicon oxynitride, silicon carbon nitride, silicon carbon oxynitride, aluminum oxide, lanthanum oxide, and titanium oxide.
Ha discloses a mask insulating pattern (Gs, fig. 2A; ¶0051, SiN) having an etch selectivity with respect to the inner spacer (110, fig. 2A) between the high-k dielectric pattern (FE, fig. 2A) and the inner spacer (110, fig. 2A).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a silicon nitride layer therebetween can suppress short channel effect and improve tunneling barrier better than silicon oxide.
Prior art made of record and not relied upon are considered pertinent to current application disclosure.
* (“Liu et al., US PG pub. 20180350932 A1”) Discloses a transistor with one or more additional spacers, or inner-gate spacers, as referred to herein. The additional spacers may be formed between the gate and original spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion, a middle portion, and an upper portion. In some such cases, the lower and upper portions of the gate may be wider between the original spacers than the middle portion of the gate, which may be as a result of the additional spacers being located between the middle portion of the gate and the original spacers. In some such cases, the gate may approximate an I-shape, custom-character-shape, custom-character-shape, ⊥-shape, L-shape, or J-shape, for example.
* (“Ching et al., US Patent 9881993 B2”) discloses a a semiconductor device having a horizontal gate all around structure on a bulk substrate is provided. The method comprises forming a plurality of fins on a bulk substrate wherein each fin comprises a vertical slice of substrate material and a plurality of channel layers above the vertical slice of substrate material. The plurality of channel layers includes a top channel layer above a bottom channel layer. Each channel layer comprises a first sublayer of removable semiconductor material overlaid by a second sublayer of semiconductor material. The method further comprises providing shallow trench isolation (STI) material between the vertical slices of the bulk substrate in the plurality of fins, depositing poly material around a central portion of the plurality of fins, forming source and drain regions, and forming an interlayer dielectric layer (ILD0). The method also comprises removing the poly material, forming a plurality of channels from the channel layers, and forming a gate around the channels.
*(“Yang et al., US Patent 11437371 B2”) discloses a fin structure including a fin base portion and a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer on the fin base portion, a second semiconductor layer above the first semiconductor layer, and a sacrificial semiconductor layer between the first and second semiconductor layers. The method further includes replacing the sacrificial semiconductor layer with a negative capacitance (NC) layer and forming gate electrodes around the NC layer, the first semiconductor layer, and the second semiconductor layer. The NC layer includes an NC dielectric material.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZ CHIU whose telephone number is 571-272-8656. The examiner can normally be reached on M-F, 9:00AM to 5:00PM (EST).
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/TSZ K CHIU/Examiner, Art Unit 2898 Tsz.Chiu@uspto.gov
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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