DETAILED ACTION
This action is responsive to the communication filed 16 March 2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of Applicant' s Information Disclosure Statement(s) (IDS). The IDS(es) has/have been considered.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Election/Restrictions
Applicant’s election without traverse of the Species 2 (FIGS. 5/6) embodiment in the reply filed on 20 May 2025 is acknowledged.
Regarding Applicant’s listing of claims 1-8 and 11-20 as readable on the elected species, however, the Examiner respectfully notes that claims 11-16 do not belong to the elected species 2 embodiment.
Claim 11 recites the limitation “wherein at least one of the plurality of back side power pads is connected to at least one of the plurality of back side dummy pads.” Applicant’s elected species 2 embodiment is depicted in FIGS. 5/6, however, which shows in FIG. 2, of which FIGS. 5 and 6 are cross-sections, wherein the dummy pads are not connected to the power pads.
Accordingly, claims 9-16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 17, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent Publication No. 2022/0130802 (published Apr. 28, 2022) (hereinafter “Jun”).
Regarding independent claim 1, Jun discloses: A semiconductor chip (FIGS. 2/3/4/9, depicting a semiconductor package, [0019]) comprising:
a semiconductor substrate (FIGS. 2/3/4/9, e.g. substrate 310, [0033]) including an active surface (FIGS. 2/3/4/9, e.g., lowermost surface of the first substrate 310, [0033]) and an inactive surface facing the active surface (FIGS. 2/3/4/9, e.g., uppermost surface of the first substrate 310 facing the lowermost surface of substrate 310);
a multi wiring layer (FIGS. 2/3/4/9, semiconductor device layer 320, [0033]) arranged on the active surface of the semiconductor substrate (FIGS. 2/3/4/9, depicting wherein the semiconductor device layer 320 is arranged on the lowermost surface of the first substrate 310), and including a wiring structure (FIGS. 2/3/4/9, e.g., the plurality of conductive lines CL forming a wiring structure, [0057]) having at least two layers (FIGS. 2/3/4/9, depicting wherein the plurality of conductive lines CL includes at least two layers) and including a conductive wiring (FIGS. 2/3/4/9, depicting the conductive line CL connected to the chip pad CPa/b, [0038]) and a dummy wiring (FIGS. 2/3/4/9, depicting the conductive line CL connected to the dummy pad TP, [0044]);
a lower protection layer (FIGS. 2/3/4/9, depicting, e.g., a lowermost insulating layer ML, [0036]) arranged on a front surface of the multi wiring layer (FIGS. 2/3/4/9, depicting wherein the insulating layer ML is arranged on a surface of the semiconductor device layer 320), and including a conductive medium pad connected to the conductive wiring (FIGS. 2/3/4/9, depicting wherein the insulating layer ML includes, e.g., the chip pad CPb1 connected to the conductive line CL);
an upper protection layer (FIGS. 2/3/4/9, depicting, e.g., an uppermost insulating layer ML) on the inactive surface of the semiconductor substrate (FIGS. 2/3/4/9, depicting wherein the insulating layer ML is arranged on a surface of the first substrate 310);
a plurality of through vias configured to penetrate the semiconductor substrate and the upper protection layer (FIGS. 2/3/4/9, penetration electrodes TSV, [0038]), and including a plurality of power through vias (FIGS. 2/3/4/9, depicting wherein the penetration electrodes TSV may receive no signal, control, power, or ground signals, [0053]), a plurality of signal through vias (FIGS. 2/3/4/9, depicting wherein the penetration electrodes TSV may receive no signal, control, power, or ground signals, [0053]), and a plurality of dummy through vias (FIGS. 2/3/4/9, depicting wherein the penetration electrodes TSV may receive no signal, control, power, or ground signals, [0053]); and
a plurality of back side pads arranged on a rear surface of the upper protection layer (FIGS. 2/3/4/9, depicting, e.g., chip pads CPa and dummy pads TPa arranged on a surface of the uppermost insulating layer ML), and connected to the plurality of through vias (FIGS. 2/3/4/9, depicting wherein the chip pads CPa and dummy pads TPa are connected to the penetration electrodes TSV),
wherein the plurality of dummy through vias are connected to the wiring structure (FIGS. 2/3/4/9, depicting wherein the plurality of penetration electrodes are connected to the plurality of connection lines CL).
Regarding claim 2, Jun further discloses wherein the plurality of dummy through vias are connected to the dummy wiring (FIGS. 2/3/4/9, depicting the conductive line CL connected to the dummy pad TP, and further wherein the penetration electrode TSV which may receive no signal, control, power, or ground signals is connected to the conductive line CL connected to the dummy pad TP, [0044]), and the dummy wiring is connected to the conductive wiring (FIGS. 2/3/4/9, depicting wherein the conductive line CL connected to the dummy pad TP is connected to the conductive line connected to the chip pad CPb1/2).
Regarding claim 3, Jun further discloses a plurality of front side pads (FIGS. 2/3/4/9, depiciting, e.g., those chip pads CPa of the buffer chip 200 opposite the chip pads CPb, [0028]) including a plurality of front side power pads (FIGS. 2/3/4/9, depicting wherein the chip pads CPa opposite the chip pads CPb may receive no signal, control, power, or ground signals, [0053]), a plurality of front side signal pads (FIGS. 2/3/4/9, depicting wherein the chip pads CPa opposite the chip pads CPb may receive no signal, control, power, or ground signals, [0053]), and a plurality of front side dummy pads (FIGS. 2/3/4/9, depicting wherein the chip pads TPa opposite the dummy pads TPb may receive no signal, control, power, or ground signals, [0053]), and arranged on a front surface of the lower protection layer (FIGS. 2/3/4/9, depicting wherein the chip pads CPa are arranged on a surface of the lowermost insulating layer ML), wherein each of the plurality of front side power pads and the plurality of front side signal pads is connected to the conductive medium pad (FIGS. 2/3/4/9, depicting wherein the chip pads CPa are connected to the chip pads CPb).
Regarding claim 4, Jun further discloses a dummy medium pad arranged in the lower protection layer (FIGS. 2/3/4/9, depicting, e.g., dummy pad TPb arranged in the lowermost insulating layer ML), and connected to the dummy wiring (FIGS. 2/3/4/9, depicting, e.g., dummy pad TPb connected to the connection line CL), wherein the plurality of front side dummy pads are connected to the dummy medium pad (FIGS. 2/3/4/9, depicting wherein the dummy pads TPb are connected to the dummy pads TPa).
Regarding claim 5, Jun further discloses wherein at least one of the plurality of dummy through vias is, in a plan view, arranged between two signal through vias selected from among the plurality of signal through vias (FIGS. 2/3/4/9, depicting wherein, in a plan view, e.g., FIG. 9, at least one of the penetration electrodes TSV connected to the dummy pads TPa/b is arranged between one of the penetration electrodes TSV connected to the chip pads CPa/b).
Regarding independent claim 17, Jun discloses: A semiconductor package comprising:
a first semiconductor chip (FIGS. 2/3/4/9, e.g., semiconductor chip 300, [0028]); and
a second semiconductor chip on the first semiconductor chip (FIGS. 2/3/4/9, e.g., semiconductor chip 500, [0028]),
wherein the first semiconductor chip (FIGS. 2/3/4/9, semiconductor chip 300) comprises:
a first semiconductor substrate (FIGS. 2/3/4/9, e.g. substrate 310, [0033]) including a first active surface (FIGS. 2/3/4/9, e.g., lowermost surface of the first substrate 310, [0033]) and a first inactive surface, which are opposite to each other (FIGS. 2/3/4/9, e.g., uppermost surface of the first substrate 310 opposite to the lowermost surface of substrate 310);
a first dummy wiring (FIGS. 2/3/4/9, depicting the conductive line CL connected to the dummy pad TP, [0044]) arranged in a first multi wiring layer (FIGS. 2/3/4/9, semiconductor device layer 320, [0033]) on the first active surface of the first semiconductor substrate (FIGS. 2/3/4/9, depicting wherein the semiconductor device layer 320 is arranged on the lowermost surface of the first substrate 310);
a plurality of first back side dummy pads arranged on the first inactive surface of the first semiconductor substrate (FIGS. 2/3/4/9, depicting, e.g., dummy pads TPa arranged on an uppermost surface of the substrate 310); and
a plurality of first dummy through vias configured to penetrate the first semiconductor substrate (FIGS. 2/3/4/9, penetration electrodes TSV, wherein the penetration electrodes TSV may receive no signal, control, power, or ground signals, [0053], [0038]) and connected to the first dummy wiring and the plurality of first back side dummy pads (FIGS. 2/3/4/9, depicting wherein the penetration electrodes TSV are connected to the conductive line CL connected to the dummy pad TP and the dummy pads TPa),
wherein the second semiconductor chip (FIGS. 2/3/4/9, semiconductor chip 500) comprises:
a second semiconductor substrate (FIGS. 2/3/4/9, e.g. substrate 510, [0033]) including a second active surface (FIGS. 2/3/4/9, e.g., lowermost surface of the substrate 510, [0033]) and a second inactive surface, which are opposite to each other (FIGS. 2/3/4/9, e.g., uppermost surface of the first substrate 510 opposite to the lowermost surface of substrate 510);
a second dummy wiring (FIGS. 2/3/4/9, depicting the conductive line CL connected to the dummy pad TP, [0044]) arranged in a second multi wiring layer (FIGS. 2/3/4/9, semiconductor device layer 520, [0033]) on the second active surface of the second semiconductor substrate (FIGS. 2/3/4/9, depicting wherein the semiconductor device layer 520 is arranged on the lowermost surface of the first substrate 510); and
a plurality of second front side dummy pads connected to the second dummy wiring (FIGS. 2/3/4/9, depicting, e.g., dummy pads TPb arranged connected to the conductive line CL connected to the dummy pad TP), and arranged on a front surface of the second multi wiring layer (FIGS. 2/3/4/9, depicting wherein the dummy pads dummy pads TPb arranged on a lowermost surface of the semiconductor device layer 520), and
wherein the plurality of first back side dummy pads are respectively connected to the plurality of second front side dummy pads (FIGS. 2/3/4/9, depicting wherein the dummy pads TPa are connected to the dummy pads TPb).
Regarding claim 20, Jun further discloses wherein the first semiconductor chip (FIGS. 2/3/4/9, semiconductor chip 300) further comprises a first conductive wiring arranged in the first multi wiring layer (FIGS. 2/3/4/9, depicting the conductive line CL connected to the connection pad CPa/b, [0038]), and wherein the first dummy wiring is connected to the first conductive wiring in the first multi wiring layer (FIGS. 2/3/4/9, depicting wherein the conductive line CL connected to the dummy pad TP is connected to the conductive line connected to the chip pad CPb1/2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-8, 18, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Jun in view of U.S. Patent Publication No. 2014/0264918 (filed Mar. 15, 2013) (hereinafter “Huang”).
Regarding claim 6, Jun does not specifically disclose wherein the plurality of dummy through vias are, in a plan view, arranged to surround at least one of the plurality of signal through vias.
In the same field of endeavor, Huang discloses a semiconductor chip (FIGS. 1/10, chip 1, [0019]) including a configuration of vias, wherein in one configuration, a plurality of dummy vias surround at least one of a plurality of signal vias (FIG. 10, depicting a plurality of through silicon vias TSV, wherein dummy TSVs surround at least one signal TSV, [0029]). Regarding the configuration of the vias, in [0029], Huang states: “the adjacent dummy TSVs can also be connected by one or more first-level RDLs forming a linear (as shown in FIG. 9) or irregular-shaped (not shown) heat dissipating structure, thereby improving heat dissipation.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed semiconductor package of Jun by substituting the via configuration of Huang in order to improve heat dissipation within the semiconductor package. See Huang [0029].
Regarding claim 7, Jun further discloses wherein the plurality of back side pads (FIGS. 2/3/4/9, depicting, e.g., chip pads CPa and dummy pads TPa arranged on a surface of the uppermost insulating layer ML) comprise: a plurality of back side power pads respectively connected to the plurality of power through vias (FIGS. 2/3/4/9, depicting, e.g., chip pads CPa that may receive no signal, control, power, or ground signals which are connected to the penetration electrodes TSV, [0053]); a plurality of back side signal pads respectively connected to the plurality of signal through vias (FIGS. 2/3/4/9, depicting, e.g., chip pads CPa that may receive no signal, control, power, or ground signals which are connected to the penetration electrodes TSV, [0053]); and a plurality of back side dummy pads respectively connected to the plurality of dummy through vias (FIGS. 2/3/4/9, depicting, e.g., dummy pads TPa that may receive no signal, which are connected to the penetration electrodes TSV, [0053]).
Jun does not specifically disclose wherein the plurality of back side dummy pads comprise a dot pad connected to one of the plurality of dummy through vias, and a line pad connected to two or more of the plurality of dummy through vias.
In the same field of endeavor, Huang discloses a semiconductor chip (FIGS. 1/10, chip 1, [0019]) including a configuration of vias, wherein in one configuration, a plurality of dummy pads comprise a dot pad connected to one of the plurality of dummy through vias, and a line pad connected to two or more of the plurality of dummy through vias (FIGS. 2/10, depicting a plurality of through silicon vias TSV, wherein the configuration of TSVs includes a configuration of dummy TSVs wherein a first level RDL 10 forms a dot pad connected to a singular one of the dummy TSVs, and wherein a first level RDL 10 forms a line pad connected to two or more of the dummy TSVs, [0029]). Regarding the configuration of the vias, in [0029], Huang states: “the adjacent dummy TSVs can also be connected by one or more first-level RDLs forming a linear (as shown in FIG. 9) or irregular-shaped (not shown) heat dissipating structure, thereby improving heat dissipation.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed semiconductor package of Jun by substituting the via configuration of Huang in order to improve heat dissipation within the semiconductor package. See Huang [0029].
Regarding claim 8, Jun in view of Huang further discloses wherein the line pad is, in a plan view, is arranged to surround at least one of the plurality of back side signal pads (Jun FIGS. 2/3/4/9; Huang FIGS. 2/10; depicting wherein the first level RDL 10 forming a line pad connected to two or more of the dummy TSVs surrounds a signal TSV, such that the dummy pads TPa forming a line pad as taught by Huang would surround a chip pad CPa that may receive no signal, control, power, or ground signals, [0053]).
Regarding claim 18, Jun does not specifically disclose wherein the plurality of first back side dummy pads comprise a dot pad connected to one of the plurality of first dummy through vias, and a line pad connected to two or more of the plurality of first dummy through vias.
In the same field of endeavor, Huang discloses a semiconductor chip (FIGS. 1/10, chip 1, [0019]) including a configuration of vias, wherein in one configuration, a plurality of dummy pads comprise a dot pad connected to one of the plurality of dummy through vias, and a line pad connected to two or more of the plurality of dummy through vias (FIGS. 2/10, depicting a plurality of through silicon vias TSV, wherein the configuration of TSVs includes a configuration of dummy TSVs wherein a first level RDL 10 forms a dot pad connected to a singular one of the dummy TSVs, and wherein a first level RDL 10 forms a line pad connected to two or more of the dummy TSVs, [0029]). Regarding the configuration of the vias, in [0029], Huang states: “the adjacent dummy TSVs can also be connected by one or more first-level RDLs forming a linear (as shown in FIG. 9) or irregular-shaped (not shown) heat dissipating structure, thereby improving heat dissipation.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed semiconductor package of Jun by substituting the via configuration of Huang in order to improve heat dissipation within the semiconductor package. See Huang [0029].
Regarding claim 19, Jun in view of Huang further discloses wherein the first semiconductor chip (FIGS. 2/3/4/9, semiconductor chip 300) further comprises:
a plurality of first signal through vias configured to penetrate the first semiconductor substrate (FIGS. 2/3/4/9, depicting wherein the penetration electrodes TSV may receive no signal, control, power, or ground signals, [0053]); and
a plurality of first back side signal pads (FIGS. 2/3/4/9, depicting, e.g., chip pads CPa that may receive no signal, control, power, or ground signals which are connected to the penetration electrodes TSV, [0053]) arranged on the first inactive surface of the first semiconductor substrate (FIGS. 2/3/4/9, depicting wherein the chip pads CPa that may receive no signal, control, power, or ground signals which are connected to the penetration electrodes TSV are arranged on an uppermost surface of the substrate 310), and connected to the plurality of first signal through vias (FIGS. 2/3/4/9, depicting wherein the chip pads CPa that may receive no signal, control, power, or ground signals which are connected to the penetration electrodes TSV that may receive no signal, control, power, or ground signals), and
wherein the line pad is, in a plan view, arranged to surround at least one of the plurality of first back side signal pads (Jun FIGS. 2/3/4/9; Huang FIGS. 2/10; depicting wherein the first level RDL 10 forming a line pad connected to two or more of the dummy TSVs surrounds a signal TSV, such that the dummy pads TPa forming a line pad as taught by Huang would surround a chip pad CPa that may receive no signal, control, power, or ground signals, [0053]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: U.S. Patent Publication Nos. 2016/0181201 (disclosing a plurality of ground through vias and connection pad configuration similar to that of the instant application).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM D WEILAND whose telephone number is (703)756-4760. The examiner can normally be reached Monday - Friday 9am-5pm.
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/ADAM D WEILAND/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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