Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This is a Non-Final Action of the instant application 18/512,428 (hereinafter the ‘428 application), filed 11/17/2023, and assigned to Hong Kong Applied Science and Technology Research Institute Company Limited.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Bhattacharya et al, U.S. Patent Publication No. 2018/0285484, hereinafter Bhattacharya, and Ajitomi et al., U.S. Patent No. 9,258,137, hereinafter Ajitomi.
With regard to claim 1, which teaches “A speed bridge for emulation hardware”; Bhattacharya teaches the use of a communication interface 350 (while additionally referring to it as a speed bridge / a transactor / a speed-rate adapter) to compensate for speed differences between computing environments on different sides (see paragraphs 9, 10, 13, 39, 42, and 63).
With regard to claim 1, which teaches the speed bridge “comprising: a virtual host comprising a host data flow controller and a host virtual emulator; a virtual DUT comprising a DUT data flow controller and a DUT virtual emulator;” Bhattacharya teaches the emulator being connected to one or more target systems to form a protype of the system the user is designing through the use of a provided testbench (see paragraphs 39 and 47), with the target system generating and verifying test data, wherein the system is further provided with a data flow control circuitry for adapting speeds and buffering content sent between the high speed end and low speed end (see paragraphs 39 and 45-47 and figure 1A). Bhattacharya further teaches a device under test DUT model being integrated into one or more emulator 130 and provided with a data flow control circuitry for adapting speeds and buffering content sent between the high speed end and low speed end (see paragraphs 39 and 45-47 and figure 1A).
With regard to claim 1, which teaches “an asynchronous communications device having a host queue and a DUT queue which allows the virtual host to communicate with the virtual DUT”; Bhattacharya further teaches caching signal activity in the system between high speed ends and low speed ends to buffer content for use when the other system is ready (see paragraphs 39-42, 47, and 63).
While Bhattacharya describes each of the network ends being simulated / modeled / emulated on the same central communication device (supra), Ajitomi further explicitly provides for a central bridge apparatus comprising multiple virtual devices continually maintained so as to allow for direct interaction with a control point (see column 4, lines 3-15 and column 6, lines 34-64 and figure 4). It would be obvious to one of ordinary skill in the art at the time of the inventions to store multiple emulators on one bridge to enable communication without the need for continual access to the actual device or it’s data.
With regard to claim 2, which teaches “further comprising: a physical host which communicates with the virtual DUT; and a physical DUT which communicates with the virtual host”; Bhattacharya further teaches communication with the actual physical host / workstation system as well as the target systems and enabling communication between the emulators and each of the host / workstation system and the target systems (see paragraphs 39, 42, and 45-57 and figure 1A).
With regard to claim 3, which teaches “wherein the DUT virtual emulator has a DUT virtual emulator memory which stores a fixed DUT output associated with a fixed DUT input, such that if the virtual host sends the fixed DUT input to the virtual DUT, the DUT virtual emulator returns the fixed DUT output without communicating with the physical DUT”; Ajitomi further teaches storing in a memory on the bridge apparatus information that could be requested from the actual end device, that is simulated on the bridge and whether or not the requested data is “fixed” or “variable”. If the data is “fixed” the response is sent from the locally stored data without querying the actual device, whereas if the data is “variable” the device may need to be polled first to determine the state. (see column 8, line 26 through column 9, line 31 and figure 4-6).
With regard to claims 4 and 5, which teach “wherein the host virtual emulator has a host virtual emulator memory which stores a fixed host output associated with a fixed host input, such that if the virtual DUT sends the fixed host input to the virtual host, the host virtual emulator returns the fixed host output without communicating with the physical host”; Ajitomi further teaches storing in a memory on the bridge apparatus information that could be requested from the actual end device, that is simulated on the bridge and whether or not the requested data is “fixed” or “variable”. If the data is “fixed” the response is sent from the locally stored data without querying the actual device, whereas if the data is “variable” the device may need to be polled first to determine the state. (see column 8, line 26 through column 9, line 31 and figure 4-6).
With regard to claim 6, which teaches “wherein the host virtual emulator automatically responds to timing-critical inputs from the physical DUT”; Bhattacharya further that the emulator automatically responds to inputs form the physical devices (see paragraph 47).
With regard to claims 7 and 8, which teach “wherein the host virtual emulator periodically sends a synchronization message to the physical DUT”; Ajitomi teaches continually periodically sending synchronization messages to the device (see column 5, lines 4-13).
With regard to claim 12, which teaches “wherein the virtual host further comprises a host pause frame insert such that the host pause frame insert can send a host pause frame protocol to the asynchronous communications device which will cause a virtual host input signal to be queued”; Bhattacharya further teaches dealing with the unsynchronized clocks by pausing and caching data (waiting till ready) the transfer of information between the network elements operating at different speeds (see paragraphs 39-41).
With regard to claims 13 and 14, which teach “wherein the virtual DUT further comprises a DUT pause frame insert such that the DUT pause frame insert can send a DUT pause frame protocol to the asynchronous communications device which will cause a virtual DUT input signal to be queued”; Bhattacharya further teaches dealing with the unsynchronized clocks by pausing and caching data (waiting till ready) the transfer of information between the network elements operating at different speeds (see paragraphs 39-41).
Claims 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Bhattacharya et al, U.S. Patent Publication No. 2018/0285484, hereinafter Bhattacharya, Ajitomi et al., U.S. Patent No. 9,258,137, hereinafter Ajitomi, and Kim “Automatic Generation of Software / Hardware Co-Emulation Interface for Transaction-Level Communication”.
With regard to claim 9, which teaches “wherein the host data flow controller receives a first signal having a first clock speed from the virtual DUT and converts the first signal to a second signal having a second clock speed before transmitting the second signal to the physical DUT”; Bhattacharya and Ajitomi teach a system simulating devices with different clock speeds by pausing and transactionally dealing with requests (supra), but don’t specifically discuss changing the clock speed. Kim teaches a system for DUT emulation and testing via a test bench (see pages 196, 197, and 199), similar to that of Bhattacharya and Ajitomi, but further teaches dealing with different clocks by changing one or more of the clocks to a second clock speed to avoid the clock skew problem (see pages 198-199). It would be obvious to one of ordinary skill in the art at the time to use the clock syncing as done in Kim, in the system of Bhattacharya and Ajitomi in order to run the two emulated systems together on a common timing as an alternate means for dealing with different clock timings.
With regard to claims 10 and 11, which teach “wherein the DUT data flow controller receives a first signal having a first clock speed from the virtual host and converts the first signal to a second signal having a second clock speed before transmitting the second signal to the physical host”; Bhattacharya and Ajitomi teach a system simulating devices with different clock speeds by pausing and transactionally dealing with requests (supra), but don’t specifically discuss changing the clock speed. Kim teaches a system for DUT emulation and testing via a test bench (see pages 196, 197, and 199), similar to that of Bhattacharya and Ajitomi, but further teaches dealing with different clocks by changing one or more of the clocks to a second clock speed to avoid the clock skew problem (see pages 198-199). It would be obvious to one of ordinary skill in the art at the time to use the clock syncing as done in Kim, in the system of Bhattacharya and Ajitomi in order to run the two emulated systems together on a common timing as an alternate means for dealing with different clock timings.
Summary
Claims 1-14 are REJECTED.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Roy et al., U.S. Patent No. 10,430,215 and Duru et al, U.S. Publication No. 2022/0382942.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DENNIS G BONSHOCK whose telephone number is (571)272-4047. The examiner can normally be reached M-F 7:15 - 4:45.
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/DENNIS G BONSHOCK/Primary Examiner, Art Unit 3992
