Prosecution Insights
Last updated: April 19, 2026
Application No. 18/512,649

AMPLIFIER ASSEMBLY WITH REDUCED GAIN VARIATION, FRONT-END MODULE, AND MOBILE DEVICE INCLUDING THE SAME

Non-Final OA §102§103
Filed
Nov 17, 2023
Examiner
NGUYEN, HIEU P
Art Unit
2843
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Skyworks Solutions Inc.
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
2y 1m
To Grant
97%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allow Rate
1123 granted / 1220 resolved
+24.0% vs TC avg
Moderate +5% lift
Without
With
+5.1%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
25 currently pending
Career history
1245
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
54.9%
+14.9% vs TC avg
§102
28.6%
-11.4% vs TC avg
§112
5.3%
-34.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1220 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The information disclosure statement filed on 07/09/2024 has been considered and placed in the application file. Claim Rejections - 35 USC § 102 (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim s 1-6, 8 and 18-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lehtola (U.S. 12,506,450 ). Regarding claim 1, Lehtola (hereinafter, Ref~ 450 ) discloses (please see Fig . 1-6 and related text for details ) a n amplifier assembly (e.g., 200 of Fig. 2) comprising: an amplifying transistor (204 of Fig. 2) configured to amplify a radio frequency signal (RFIN of Fig. 2) when powered by a supply signal (VBAT/VCC) and biased by a biasing signal (disposed at base of transistor 204 of Fig. 2) ; and a biasing circuit (202 of Fig. 2) configured to control the biasing signal based on a level of the supply signal, the biasing circuit including a reference transistor (see transistor disposed at the base of transistor 208 of Fig. 2) which is mirrored with the amplifying transistor to control a current (collector to emitter current of 204 of Fig. 2) flowing through the amplifying transistor such as to compensate a gain variation of the amplifier assembly , meeting claim 1 . Regarding claim 2 , Ref~450 supports the claimed “ wherein the biasing circuit is further configured to increase a gain of the amplifying transistor when the level of the supply signal decreases by increasing a reference current flowing through the reference transistor ”, since it is configured in the same manner compared to the claimed one, meeting claim 2 . Regarding claim 3 , Ref~450 discloses t he amplifier assembly of claim 1 wherein the biasing circuit includes an input node (disposed at base of transistor 208 of Fig. 2) configured to receive an input current dependent on the level of the supply signal and an output node (disposed at base of transistor 204 of Fig. 2) connected to the amplifying transistor to provide the biasing signal , meeting claim 3 . Regarding claim 4 , Ref~450 discloses t he amplifier assembly of claim 3 wherein the biasing circuit further includes a diode (see bottom diode from 202 of Fig. 2) disposed between the reference transistor and the input node , meeting claim 4 . Regarding claim 5 , Ref~450 discloses t he amplifier assembly of claim 3 wherein the biasing circuit further includes an additional transistor (208 of Fig. 2) disposed between the output node and the input node , meeting claim 5 . Regarding claim 6 , Ref~450 discloses t he amplifier assembly of claim 3 wherein the input node is connected to a current source (upper diode of 202 of Fig. 2 broadly can be read as the claimed current source, since it is configured to provide current to base of transistor 208 ) dependent on the level of the supply signal , meeting claim 6 . Regarding claim 8 , Ref~450 discloses t he amplifier assembly of claim 1 further comprising multiple stages of amplifiers, and the amplifying transistor is disposed at a first stage of the amplifier assembly as shown in Fig. 1, meeting claim 8 . Regarding claim 18-20, limitations from these claims can be rejected in the same manner as described above in claims 1-6 and 8, since same features/limitations are being presented here and the system of Ref~450 can be employed in the claimed “ mobile device” having transceiver as shown in Fig. 8, meeting claim 18-20 . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim s 9-15 and 17 are rejected under 35 U.S.C. 103 as being obvious over Lehtola (U.S. 12,506,450). Regarding claim 9 , limitations from the claim can be rejected in the same manner as described above in claim 1, since same features are being presented except for the claimed “ package board ” . However, these are normal design feature in the field depending on custom specifications and such feature would be required for most application in the amplifying field to at least provide electrical connection and/or mechanical support and/or thermal management for the system, meeting claim 9 . Regarding claim 10 , Ref~450 discloses t he radio frequency module of claim 9 wherein the radio frequency module is a front-end module as shown in Fig. 8, meeting claim 10 . Regarding claims 1 1 -15 and 17, limitations from these claims can be rejected in the same manner as described above in claims 2-6 and 8, since same/identical limitations are being presented here, meeting claims 11-15 and 17 . Allowable Subject Matter Claims 7 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT HIEU P NGUYEN whose telephone number is 571-272-8577. The examiner can normally be reached on FILLIN "Work schedule?" \* MERGEFORMAT Monday-Friday 8:30AM-6:00PM . If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached on 571-272-5918. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). /HIEU P NGUYEN/ Primary Examiner, Art Unit 2843
Read full office action

Prosecution Timeline

Nov 17, 2023
Application Filed
Mar 13, 2026
Non-Final Rejection — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12603618
SIGNAL AMPLIFYING CIRCUIT AND SIGNAL PROCESSING SYSTEM AND ANALOG-TO-DIGITAL CONVERTING SYSTEM COMPRISING THE SAME
2y 5m to grant Granted Apr 14, 2026
Patent 12603616
POWER AMPLIFIER MODULE WITH INTERLEAVED WIREBONDS
2y 5m to grant Granted Apr 14, 2026
Patent 12597899
SWITCHING AMPLIFIER
2y 5m to grant Granted Apr 07, 2026
Patent 12597898
HIGH-FREQUENCY CIRCUIT AND COMMUNICATION DEVICE
2y 5m to grant Granted Apr 07, 2026
Patent 12597891
CASCODED HIGH-VOLTAGE AMPLIFIER
2y 5m to grant Granted Apr 07, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
97%
With Interview (+5.1%)
2y 1m
Median Time to Grant
Low
PTA Risk
Based on 1220 resolved cases by this examiner. Grant probability derived from career allow rate.

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