DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
For Examiner’s Interview fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html).
Status of claim(s) to be treated in this office action:
Independent: 1 and 11.
Pending: 1-16.
Withdrawn: 11-16.
Information Disclosure Statement
Applicant’s IDS(s) submitted on 11/6/2025, 11/17/2023 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has/have considered by the examiner and made of record.
Election/Restrictions
Applicant’s election without traverse of Species I Claim 1-19 in the reply filed on 5/11/2026 is acknowledged.
Specification
The disclosure is objected to because of the following informalities:
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR DEVICE INCLUDING ADJACENT N-CHANNEL MOSFETS SURROUNDED BY A DEEP TRENCH ISOLATION STRUCTURE.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 5, 6, 8 and 10 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Morii et al., US PG pub. 20150041960 A1.
Re: Independent Claim 1, Morii discloses 1, a semiconductor substrate (sub, fig. 16);
a first semiconductor element (high-voltage MOS transistor, fig. 16) formed on the semiconductor substrate (sub, fig. 16), the first semiconductor element (high-voltage MOS transistor, fig. 16) being an N-channel type MOSFET (NWP);
a second semiconductor element (CMOS transistor, fig. 16) formed on the semiconductor substrate (sub, fig. 16) and disposed next to the first semiconductor element (high-voltage MOS transistor, fig. 16), the second semiconductor element (CMOS transistor, fig. 16) being an N-channel type MOSFET (NWR);
and a deep trench isolation (DTR, fig. 16) formed in the semiconductor substrate (sub, fig. 16) and surrounding the first semiconductor element (high-voltage MOS transistor, fig. 16) and the second semiconductor element (CMOS transistor, fig. 16) in plan view (fig. 1).
wherein the first semiconductor element (high-voltage MOS transistor, fig. 16) is connected to a first circuit (¶0038; output driver), and wherein the second semiconductor element (CMOS transistor, fig. 16) is connected to a second circuit (¶0056; I/O circuit) different from the first circuit (¶0038; output driver).
Re: Claim 5, Morii disclose(s) all the limitations of claim 1 on which this claim depends. Morii further discloses: wherein in a first direction along a main surface of the semiconductor substrate (sub, fig. 16), the second semiconductor element (CMOS transistor, fig. 16) is disposed between the first semiconductor element (high-voltage MOS transistor, fig. 16) and the deep trench isolation (DTR, fig. 16), wherein the first semiconductor element (high-voltage MOS transistor, fig. 16) includes: a first gate electrode (GE, fig. 16) extending in a second direction, the second direction intersecting with the first direction and being along the main surface of the semiconductor substrate (sub, fig. 16); a first source region (NR, fig. 16); and a first drain region (PR, fig. 16), wherein the second semiconductor element (CMOS transistor, fig. 16) includes: a second gate electrode (GE, fig. 16) extending in the second direction; a second source region (NR, fig. 16); and a second drain region (PR, fig. 16), wherein the deep trench isolation (DTR, fig. 16) extends in the first direction, and wherein the deep trench isolation (DTR, fig. 16), the first gate electrode (GE, fig. 16), the first source region (NR, fig. 16), the first drain region (PR, fig. 16), the second gate electrode (GE, fig. 16), the second source region (NR, fig. 16) and the second drain region (PR, fig. 16) are disposed in the second direction.
Re: Claim 6, Morii disclose(s) all the limitations of claim 1 on which this claim depends. Morii further discloses: wherein in plan view (fig. 1), a planar shape of the deep trench isolation (DTR, fig. 16) is a rectangle.
Re: Claim 8, Morii disclose(s) all the limitations of claim 1 on which this claim depends. Morii further discloses: wherein the first semiconductor element (high-voltage MOS transistor, fig. 16) is formed in a region to which a compressive stress (¶0117) is applied by the deep trench isolation (DTR, fig. 16).
Re: Claim 10, Morii disclose(s) all the limitations of claim 1 on which this claim depends. Morii further discloses: wherein the deep trench isolation (DTR, fig. 16) is formed in a trench (TI, fig. 16) reaching from a surface of a semiconductor layer to the semiconductor substrate (sub, fig. 16).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 and 7 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Morii et al., US PG pub. 20150041960 A1.
Re: Claim 2, Morii disclose(s) all the limitations of claim 1 on which this claim depends. Morii is silent regarding: wherein the first circuit (¶0038; output driver) has a first precision, wherein the second circuit (¶0056; I/O circuit) has a second precision, and wherein the first precision is higher than the second precision. The precision exist exclusively tied to the current flowing through the MOSFET which is an on-state characteristic, the precision is a current ratio, although these limitations have been considered by the Examiner, they pertain to the manner in which the device operates. It has been held that a claim containing a recitation pertaining to the manner of operation is not deemed to patentably distinguish the claimed device from a prior art device that is structurally identical. The device of Young is structurally identical to the Applicant’s claimed device. In addition, since the only distinction between the Applicant's claimed device and Morii's is recited in functional language, it is incumbent upon the Applicant to demonstrate that Morii’s device is not capable of operating as claimed. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that such functional distinctions do not confer patentability when compared with prior art devices like Morii’s.
Re: Claim 7, Morii disclose(s) all the limitations of claim 1 on which this claim depends. Morii is silent regarding: wherein the first semiconductor element (high-voltage MOS transistor, fig. 16) is spaced more than 10 μm apart from the deep trench isolation (DTR, fig. 16). However, thickness range it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention because, absent evidence of disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 105 USPQ 223, 235 (CCPA 1955). Furthermore, the specification contains no disclosure of either the critical nature of the claimed dimensions of any unexpected results arising therefrom. Where patentability is aid to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2sd 1934, 1936 (Fed. Cir. 1990). It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the system of Morii et a. as modified above to include first semiconductor element spaced more than 10 μm apart from the deep trench isolation since such a modification would have only involved a mere change in working ranges which involves only routine skill in the art. one would have been motivated to make such modification to spaced apart the DTI and semiconductor element this can prevent cause of leakage and latch-up in the MOS transistor.
Claim(s) 3-4 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Morii et al., US PG pub. 20150041960 A1; in view of Chijiiwa et al., US PG pub. 20060011956 A1.
Re: Claim 3, Morii disclose(s) all the limitations of claim 1 on which this claim depends. Morii is silent regarding: wherein the first circuit (¶0038; output driver) is an analog circuit, and wherein the second circuit (¶0056; I/O circuit) is a digital circuit.
Chijiiwa teaches digital circuit (16, fig. 1) and analog circuit (14, fig. 1) can be connect to transistor device.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include analog circuit since analog circuit can reduce noise and digital circuit for digital signal processing.
Re: Claim 4, Morii disclose(s) all the limitations of claim 1 on which this claim depends. Morii is silent regarding: wherein the first circuit (¶0038; output driver) is configured by a pair transistor, and wherein the second circuit (¶0056; I/O circuit) is configured by a transistor different from the pair transistor.
Chijiiwa teaches a first circuit 16, fig. 2 by pair transistor and wherein the second circuit 14, fig. 2 configured by a transistor different than first circuit.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include analog circuit since analog circuit can reduce noise and digital circuit for digital signal processing.
Claim(s) 9 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Morii et al., US PG pub. 20150041960 A1; in view of Erratico US PG pub. 20020014678 A1.
Re: Claim 9, Morii disclose(s) all the limitations of claim 1 on which this claim depends. Morii is silent regarding: wherein the semiconductor device includes a bipolar transistor, a CMOS and a DMOS.
Erratico discloses that BiCMOS can be using with a power device in Morii (¶0003).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a bipolar-CMOS-DMOS (BCD technology since BCD technology allows for the integration of several output power devices, which is particularly advantageous when it is necessary to construct half-bridge or whole-bridge circuits both of the single-phase and three-phase type, or when a large number of parallel outputs are required (¶0003).
Prior art made of record and not relied upon are considered pertinent to current application disclosure.
* (“Meiser et al., US Patent 9825148 B2”) Discloses a semiconductor device includes forming a transistor in a semiconductor substrate having a first main surface. The transistor is formed by forming a source region, forming a drain region, forming a channel region, forming a drift zone, and forming a gate electrode adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the first main surface, between the source region and the drain region. Forming the semiconductor device further includes forming a conductive layer, a portion of the conductive layer being disposed beneath the gate electrode and insulated from the gate electrode.
* (“Onoda US PG pub. 20070241387 A1”) discloses an SOI substrate is comprised of a support substrate, a buried insulating layer and a semiconductor layer. A 1poly-type memory cell has a pair of source/drain regions, a floating gate electrode layer, and a control gate impurity diffusion region. An isolation insulating layer extends from a surface of the semiconductor layer to reach the buried insulating layer while surrounding the periphery of the control gate impurity diffusion region thereby to separate a region in which the source/drain regions are formed and the control gate impurity diffusion region from each other. Therefore, a nonvolatile semiconductor can be obtained which can prevent a parasitic bipolar operation and is suitable for higher integration.
* (“Qiao et al., US patent. 10510747 B1”) discloses a BCD semiconductor device includes devices integrated on a single chip. The devices include a first high voltage nLIGBT device, a second high voltage nLIGBT device, a first high voltage nLDMOS device, a second high voltage nLDMOS device, a third high voltage nLDMOS device, a first high voltage pLDMOS device and low voltage NMOS, PMOS and PNP devices, and a diode device. A dielectric isolation is applied to the high voltage nLIGBT, nLDMOS and pLDMOS devices to realize a complete isolation between the high and low voltage devices. The nLIGBT, nLDMOS, NPN and low voltage NMOS and PMOS are integrated on the substrate of a single chip. The isolation region composed of the dielectric, the second conductivity type buried layer, the dielectric trench, and the first conductivity type implanted region realizes full dielectric isolation of high and low voltage devices. The six types of high voltage transistors have multiple channels.
* (“Levin et al., US PG pub. 20130320443 A1”) discloses a double-diffused metal oxide semiconductor (DMOS) structure is configured as an open drain output driver having electrostatic discharge (ESD) protection and a reverse voltage blocking diode inherent in the structure and without requiring metal connections for the ESD and reverse voltage blocking diode protections.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZ CHIU whose telephone number is 571-272-8656. The examiner can normally be reached on M-F, 9:00AM to 5:00PM (EST).
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/TSZ K CHIU/Examiner, Art Unit 2898 Tsz.Chiu@uspto.gov
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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