DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-7 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Schaefer et al., US PGPub 2020/0258566, in view of Chendake et al., US PGPub 2024/0030910, further in view of Walker, US PGPub 2006/0181957.
With respect to claim 1, Schaefer teaches an apparatus comprising:
a command counter circuit configured to count a first quantity of refresh commands (par. 86, “refresh detection circuit 335 may count the quantity of refresh commands received from host device 305”);
a threshold determination circuit configured to set a threshold quantity of target refresh commands based on the refresh multiplier value (pars. 14-15, the refresh threshold is an indication of a target refresh rate. This is partially based on the refresh multiplier, as the refresh multiplier is adjusted when the refresh rate does not meet the threshold);
a comparator circuit configured to receive the first quantity from the command counter, receive the threshold quantity from the threshold determination circuit, compare the first quantity to the threshold quantity, and set a state of a fault flag based at least in part on the comparison (par. 104, the controller corresponds to the comparator circuit, the controller comparing the refresh rate to the threshold, and setting a flag based on the refresh rate being below the threshold. Par. 97 teaches counting the refreshes).
a timer circuit (par. 97, refresh detection circuit) configured to provide timing signals to the comparator circuit, wherein the command counter circuit is configured to count the first quantity of refresh commands during a time period based on the timing signals (par. 97, the refresh detection circuit counts the quantity of refresh indications over a time window specified in an operative threshold).
Schaefer fails to teach a voltage controlled oscillator circuit configured to provide a clock signal to the timer circuit, wherein the timer circuit is configured to provide the timing signals based on the clock signal.
Chendake teaches:
a voltage controlled oscillator circuit configured to provide a clock signal to the timer circuit, wherein the timer circuit is configured to provide the timing signals based on the clock signal (par. 31, a voltage-controlled oscillator provides a clock signal to the timer unit 130).
Schaefer and Chendake fail to teach a temperature sensor configured to set a value of the refresh multiplier value.
Walker teaches:
a temperature sensor configured to set a value of a refresh multiplier value (par. 27, the temperature sensing circuit sets a value of the refresh rate multiplier, as shown in table 3).
It would have been obvious to one of ordinary skill in the art, having the teachings of Schaefer and Chendake before him before the earliest effective filing date, to modify the timing apparatus of Schaefer with the timing apparatus of Chendake, as the clock signal from an internal clock unit allows synchronization of timing signals, as disclosed by Chendake in par. 99. Further, it would have been obvious, also having the teachings of Walker before him before the earliest effective filing date, to modify the timing apparatus of Schaefer and Chendake with the timing apparatus of Walker, in order to improve processor performance and reduce power consumption, as taught by Walker in par. 10.
With respect to claim 2, Schaefer, Chendake and Walker teach all limitations of the parent claim. Schaefer further teaches the apparatus of claim 1, wherein the threshold determination circuit is configured to store the second quantity of target refresh commands performed within the time period (par. 97, “In some cases, this may include refresh detection circuit counting the quantity of refresh indications received, over the time window specified in the operative threshold, and comparing the counted refresh commands to the quantity of commands defined in the operative threshold. In some cases, this may include refresh detection circuit counting the quantity of refresh indications received until the count reaches a certain quantity, and comparing the time to receive the certain quantity of refresh commands to a time duration defined in the operative threshold. A quantity of received refresh commands and a time duration over which the quantity of refresh commands is received may be determined according to an internal (e.g., on die) timer such as an oscillator, counter, or the like”).
With respect to claim 3, Schaefer, Chendake and Walker teach all limitations of the parent claim. Schaeffer further teaches the apparatus of claim 1, wherein the threshold determination circuit is configured to calculate the threshold quantity of target refresh commands by dividing the constant value by the refresh multiplier value (pars. 14-15, the threshold is based on the minimum quantity of refresh commands for the time window (the constant value of the claim), the quantity of refresh commands is based on the quantity of rows refreshed by the memory device in response to one refresh command (refresh multiplier). In other words, the threshold is determined by dividing the quantity of refresh commands by the refresh multiplier).
With respect to claim 4, Schaefer, Chendake and Walker teach all limitations of the parent claim. Schaeffer further teaches the apparatus of claim 1, wherein the threshold determination circuit comprises a table configured to map the refresh multiplier value to the threshold quantity of target refresh commands (par. 51, the refresh threshold is mapped to refresh multiplier based on a condition such as temperature).
With respect to claim 5, Schaefer, Chendake and Walker teach all limitations of the parent claim. Schaeffer further teaches the apparatus of claim 1, wherein the command counter circuit and the threshold determination circuit are configured to be reset by a preset signal from the timer circuit (pars. 117-118, the memory device exits the mode after a time period expires, the memory exits the second mode and resets to the first mode).
With respect to claim 6, Schaefer, Chendake and Walker teach all limitations of the parent claim. Schaeffer further teaches the apparatus of claim 1, wherein the refresh multiplier value is based at least in part on a temperature of a memory device comprising the apparatus (par. 51).
With respect to claim 7, Schaefer, Chendake and Walker teach all limitations of the parent claim. Schaeffer further teaches the apparatus of claim 1, further comprising a pin configured to couple the apparatus to an external controller, wherein the comparator circuit is configured to provide a real time flag to the pin based at least in part on the comparison (par. 104, the controller corresponds to the comparator circuit, the controller comparing the refresh rate to the threshold, and sends a real time flag to the host pin based on the refresh rate being below the threshold).
With respect to claim 21, Schaefer, Chendake and Walker teach all limitations of the parent claim. Walker further teaches the apparatus of claim 1,
the refresh multiplier value is based at least in part on a temperature outside of a memory device comprising the apparatus; or the refresh multiplier value is based at least in part on a combination of a temperature of a memory device comprising the apparatus and a temperature outside of the memory device (par. 22, the temperature is measured adjacent to (outside) the DRAM array 104, the refresh multiplier based on the temperature, as described in par. 27).
Claim(s) 8, 11-13 and 22-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shaeffer, in view of Chendake, further in view of Mayer et al., US PGPub 2020/0159441, further in view of Song et al., US PGPub 2022/0199150.
With respect to claim 8, Schaeffer teaches a memory, comprising:
a mode register comprising a first register and a second register, the second register configured to store a fault flag (par. 84, the threshold storage 330 comprises mode registers, and par. 81, the threshold storage 330 includes error flag information); and
a refresh watchdog circuit configured to:
receive the refresh multiplier value (par. 14, the memory receives a refresh command from the host including a refresh multiplier),
determine a threshold value based on the refresh multiplier value (pars. 14-15, the refresh threshold is an indication of a target refresh rate. This is partially based on the refresh multiplier, as the refresh multiplier is adjusted when the refresh rate does not meet the threshold),
receive and count a quantity of refresh commands (par. 87),
compare the count of the one or more refresh commands to the threshold value, set a state of the fault flag based at least in part on the comparison, the state of the fault flag configured to indicate the count of the one or more refresh commands is less than the threshold value (par. 104, the controller corresponds to the comparator circuit, the controller comparing the refresh rate to the threshold, and setting a flag based on the refresh rate being below the threshold. Par. 97 teaches counting the refreshes).
a timer circuit (par. 97, refresh detection circuit) configured to provide timing signals to the refresh watchdog circuit (par. 97, the refresh detection circuit counts the quantity of refresh indications over a time window specified in an operative threshold).
the refresh watchdog circuit is configured to receive and count the quantity of refresh commands within a time period (par. 97, the refresh detection circuit counts the quantity of refresh indications over a time window specified in an operative threshold).
Schaeffer fails to specifically teach first and second timing signals, and a voltage controlled oscillator circuit to provide a clock signal to the timer circuit.
Chendake teaches:
a timer circuit configured to provide a first timing signal and a second timing signal (par. 98, the timer unit 130 produces the first and second timing signals T_VAL1 and T_VAL2)
a voltage controlled oscillator circuit configured to provide a clock signal to the timer circuit, wherein the first and the second timing signals are provided based on the clock signal, wherein a time period comprises a time between the first timing signal and the second timing signal (pars. 31 and 98, a voltage-controlled oscillator provides a clock signal to the timer unit 130, the timer unit 130 produces the first and second timing signals, T_VAL1 and T_VAL2, the time period comprising the time between them)
Schaeffer and Chendake fail to teach the first register configured to store a refresh multiplier value or receiving the refresh multiplier value from the mode register.
Mayer teaches:
the first register configured to store a refresh multiplier value, wherein the refresh multiplier value is based at least in part on a temperature of the memory (par. 93, parameters are stored in one or more mode registers, and par. 101, a row multiplier for refresh operations, based in part on a temperature, is one of the parameters), and
receive the refresh multiplier value from the mode register (par. 101).
Schaeffer, Chendake and Mayer fail to teach a temperature sensor configured to set the refresh multiplier value, and the refresh multiplier value acting as a pointer to a table that maps the refresh multiplier value to the threshold value.
Song teaches:
the refresh multiplier value is based at least in part on a temperature measured by a temperature sensor (pars. 62-63, the temperature sensor measures the temperature, and the refresh rate, varied by the refresh rate multiplier, is set).
determine a threshold value based on the refresh multiplier value, the refresh multiplier value acting as a pointer to a table that maps the refresh multiplier value to the threshold value (pars. 62-66, the threshold value of the claim corresponds to the refresh rate of Song, which is a function of the refresh rate multiplier. In this example, the refresh rate is 2M when the refresh rate multiplier is 2, the refresh rate is M when the refresh rate multiplier is 1, and the refresh rate is (1/2)M when the refresh multiplier is 1/2. This function may be considered a table, with the refresh rate multiplier pointing to one of the three refresh rates of the table).
It would have been obvious to one of ordinary skill in the art, having the teachings of Schaefer and Chendake before him before the earliest effective filing date, to modify the timing apparatus of Schaefer with the timing apparatus of Chendake, as the clock signal from an internal clock unit allows synchronization of timing signals, as disclosed by Chendake in par. 99. It would have been obvious to one of ordinary skill in the art, also having the teachings of Mayer before the earliest effective filing date, to modify the memory refresh system of Schaeffer and Chendake with the memory refresh system of Mayer, in order to align the refresh rate to temperature which improves power consumption, as taught by Mayer in par. 101. Further, it would have been obvious, also having the teachings of Song before him before the earliest effective filing date, to modify the timing apparatus of Schaefer, Chendake and Mayer with the timing apparatus of Song, in order to consume less power, as taught by Song in par. 65.
With respect to claim 11, Schaeffer, Chendake, Mayer and Song teach all limitations of the parent claim. Schaeffer further teaches the memory of claim 8, wherein the refresh watchdog circuit is configured to calculate the threshold value by dividing a constant value by the refresh multiplier value (pars. 14-15, the threshold is based on the minimum quantity of refresh commands for the time window (the constant value of the claim), the quantity of refresh commands is based on the quantity of rows refreshed by the memory device in response to one refresh command (refresh multiplier). In other words, the threshold is determined by dividing the quantity of refresh commands by the refresh multiplier).
With respect to claim 12, Schaeffer, Chendake, Mayer and Song teach all limitations of the parent claim. Song further teaches the memory of claim 8, wherein the refresh watchdog circuit is configured to determine the threshold value by accessing the table that maps the refresh multiplier value to the threshold value (pars. 62-66, the threshold value of the claim corresponds to the refresh rate of Song, which is a function of the refresh rate multiplier. In this example, the refresh rate is 2M when the refresh rate multiplier is 2, the refresh rate is M when the refresh rate multiplier is 1, and the refresh rate is (1/2)M when the refresh multiplier is 1/2. This function may be considered a table, with the refresh rate multiplier pointing to one of the three refresh rates of the table).
With respect to claim 13, Schaeffer, Chendake, Mayer and Song teach all limitations of the parent claim. Schaeffer further teaches the memory of claim 8, wherein the refresh multiplier value is inversely proportional to a refresh rate (pars. 113-114, the controller can either increase the rate at which refresh occurs, or adjust the row multiplier so a larger quantity of memory cells are refreshed in response to a single refresh command).
With respect to claim 22, Schaeffer, Chendake, Mayer and Song teach all limitations of the parent claim. Song further teaches the memory of claim 8, wherein the refresh watchdog circuit is further configured to write the state of the fault flag to a mode register (par. 45, the operation parameters stored in the mode register corresponding to the fault flag).
With respect to claim 23, Schaeffer, Chendake, Mayer and Song teach all limitations of the parent claim. Song further teaches the memory of claim 8, wherein the temperature sensor is configured to set a value of the refresh multiplier value (pars. 62-63).
Claim(s) 14, 16-20 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shaeffer, in view of Chendake, further in view of Mayer et al., further in view of Walker.
With respect to claim 14, Schaeffer teaches a method, comprising:
receiving the refresh multiplier value (par. 14, the memory receives a refresh command from the host including a refresh multiplier);
receiving and counting one or more refresh commands, the count representing a number of refresh command received during a time (pars. 14 and 97);
comparing the count of the one or more refresh commands to a threshold value based on the refresh multiplier value (pars. 14-15, the refresh threshold is an indication of a target refresh rate. This is partially based on the refresh multiplier, as the refresh multiplier is adjusted when the refresh rate does not meet the threshold. Par. 97 further discloses comparing the count); and
setting a state of a fault flag based at least in part on the comparison (par. 104, setting a flag based on the refresh rate being below the threshold.).
Schaefer discloses receiving and counting one or more refresh commands, the count representing a number of refresh commands received during a time, which is determined according to an internal timer, but fails to specifically teach a first timing signal and a second timing signal. Chendake teaches:
receiving, from a timer circuit, a first timing signal and a second timing signal (par. 98, the timer unit 130 produces the first and second timing signals T_VAL1 and T_VAL2);
As Schaeffer discloses counting one or more refresh commands, the count representing a number of refresh commands received during a time, and Chendake disclose a first timing signal and a second timing signal, the combination of Schaeffer and Chendake disclose receiving and counting one or more refresh commands, the count representing a number of refresh commands received during a time between the first timing signal and the second timing signal.
Schaeffer and Chendake fail to specifically teach that the refresh multiplier is received from a mode register.
Mayer teaches:
storing in a mode register, a refresh multiplier value (par. 93, the mode registers store the adjusted parameter values, and par. 101, the adjusted parameters include a row multiplier for refresh operations)
receiving, from the mode register, the refresh multiplier value (par. 101, receiving the row multiplier for refresh operations).
Schaeffer, Chendake and Mayer fail to teach the refresh multiplier value is received from a temperature sensor.
Walker teaches:
a refresh multiplier value received from a temperature sensor (par. 27, the temperature sensing circuit sets a value of the refresh rate multiplier, as shown in table 3)
It would have been obvious to one of ordinary skill in the art, having the teachings of Schaefer and Chendake before him before the earliest effective filing date, to modify the timing apparatus of Schaefer with the timing apparatus of Chendake, as the clock signal from an internal clock unit allows synchronization of timing signals, as disclosed by Chendake in par. 99. It would have been obvious to one of ordinary skill in the art, also having the teachings of Mayer before the earliest effective filing date, to modify the memory refresh system of Schaeffer and Chendake with the memory refresh system of Mayer, in order to align the refresh rate to temperature which improves power consumption, as taught by Mayer in par. 101. Further, it would have been obvious, also having the teachings of Walker before him before the earliest effective filing date, to modify the timing apparatus of Schaefer, Chendake and Mayer with the timing apparatus of Walker, in order to improve processor performance and reduce power consumption, as taught by Walker in par. 10.
With respect to claim 16, Schaeffer, Chendake, Mayer and Walker teach all limitations of the parent claim. Walker further teaches the method of claim 14, further comprising:
measuring a temperature of a memory, a temperature outside of the memory, or a temperature of the memory and a temperate outside the memory (par. 22, sensing the temperature of the DRAM array dye); and
setting a value of the refresh multiplier based on the measured temperature memory or outside of the memory, or a combination of the measured temperatures of the memory and outside the memory (par. 27).
With respect to claim 17, Schaeffer, Chendake, Mayer and Walker teach all limitations of the parent claim. Schaeffer further teaches the method of claim 14, further comprising: calculating the threshold value by dividing a constant value by the refresh multiplier value (pars. 14-15, the threshold is based on the minimum quantity of refresh commands for the time window (the constant value of the claim), the quantity of refresh commands is based on the quantity of rows refreshed by the memory device in response to one refresh command (refresh multiplier). In other words, the threshold is determined by dividing the quantity of refresh commands by the refresh multiplier).
With respect to claim 18, Schaeffer, Chendake, Mayer and Walker teach all limitations of the parent claim. Schaeffer further teaches the method of claim 14, further comprising: determining the threshold value by accessing a table that maps the refresh multiplier value to the threshold value (par. 51, the refresh threshold is mapped to refresh multiplier based on a condition such as temperature).
With respect to claim 19, Schaeffer, Chendake, Mayer and Walker teach all limitations of the parent claim. Schaeffer further teaches the method of claim 14, wherein the refresh multiplier value is inversely proportional to a refresh rate (pars. 113-114, the controller can either increase the rate at which refresh occurs, or adjust the row multiplier so a larger quantity of memory cells are refreshed in response to a single refresh command).
With respect to claim 20, Schaeffer, Chendake, Mayer and Walker teach all limitations of the parent claim. Schaeffer further teaches the method of claim 14, further comprising: providing a real time flag to a pin based at least in part on the comparison (par. 104, the controller corresponds to the comparator circuit, the controller comparing the refresh rate to the threshold, and sends a real time flag to the host pin based on the refresh rate being below the threshold).
With respect to claim 24, Schaeffer, Chendake, Mayer and Walker teach all limitations of the parent claim. Schaeffer further teaches the method of claim 17, wherein the constant value is an expected number of refresh commands per refresh cycle (par. 15, the minimum quantity of refresh commands corresponding to an expected number of refresh commands per cycle).
Response to Arguments
Applicant's arguments filed 12/29/2025 have been fully considered but they are not persuasive.
The arguments on page 8 are directed towards independent claim 1 not being obvious based on Schaefer and Chendake due to the new limitation “a temperature sensor configured to set a value of a refresh multiplier value.” These arguments are moot, as the new Walker reference has been supplied to teach this limitation.
The arguments on pages 8-9 are directed towards independent claim 8 not being obvious based on Schaefer, Chendake, Mayer and Gans, due to the limitation “the refresh multiplier value acting as a pointer to a table that maps the refresh multiplier value to the threshold value.” These arguments are moot, as the new Song reference has been supplied to teach this limitation.
The arguments on pages 9-10 are directed towards independent claim 14 not being obvious based on Schaefer, Chendake and Mayer, due to the new limitation “storing, in a mode register, a refresh multiplier value received from a temperature sensor” These arguments are moot, as the new Walker reference has been supplied to teach setting a refresh multiplier value received from a temperature sensor.
Conclusion
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/RYAN DARE/Examiner, Art Unit 2136